Intro to FPGA Design Using MATLAB and Simulink Published
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Transcript of Intro to FPGA Design Using MATLAB and Simulink Published
1 © 2011 The MathWorks, Inc.
Introduction to FPGA Design
Using MATLAB and Simulink
Eric Cigan – MathWorks
Jordon Inkeles – Altera
2
FPGA Designer System Designer
Algorithm Design
Fixed-Point
Timing and Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
RTL Design
IP Interfaces
Hardware Architecture
Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back Annotation Implement Design
Map
Place & Route
Synthesis
FPGA Hardware
FPGA Requirements
Hardware Specification
Test Stimulus
Separate Views of FPGA Design
3
MATLAB® and Simulink®
System and Algorithm Design
Model-Based Design for FPGAs
Algorithm Design
Fixed-Point
Timing and Control Logic
Architecture Exploration
Algorithms / IP
System Test Bench
Environment Models
Algorithms / IP
Analog Models
Digital Models
RTL Design
IP Interfaces
Hardware Architecture
Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back Annotation Implement Design
Map
Place & Route
Synthesis
FPGA Hardware
FPGA Requirements
Hardware Specification
Test Stimulus
4
MATLAB® and Simulink®
Algorithm and System Design
Model-Based Design for FPGAs
RTL Design
IP Interfaces
Hardware Architecture
Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back Annotation Implement Design
Map
Place & Route
Synthesis
FPGA Hardware
Automatic HDL
Code Generation
RTL
5
MATLAB® and Simulink®
Algorithm and System Design
Model-Based Design for FPGAs
Verification
Functional Simulation
Static Timing Analysis
Timing Simulation
Behavioral Simulation
Back Annotation Implement Design
Map
Place & Route
Synthesis
FPGA Hardware
Behavioral
Cosimulation
Automatic HDL
Code Generation
RTL
6
MATLAB® and Simulink®
Algorithm and System Design
Model-Based Design for FPGAs
Verification
Static Timing Analysis
Timing Simulation
Back Annotation Implement Design
Map
Place & Route
Synthesis
FPGA Hardware
Implement Design
Map
Place & Route
Synthesis
Back Annotation
Functional Simulation
Verification
Static Timing Analysis
Timing Simulation
Functional Simulation
Behavioral
Cosimulation
Automatic HDL
Code Generation
RTL
7
FPGA Hardware
Model-Based Design for FPGAs
FPGA Hardware
MATLAB® and Simulink®
Algorithm and System Design
Implement Design
Map
Place & Route
Synthesis
Back Annotation
Verification
Static Timing Analysis
Timing Simulation
Functional Simulation
Behavioral
Cosimulation
Automatic HDL
Code Generation
RTL
8
Model-Based Design with FPGA Workflows
MathWorks®
– HDL Coder™
Altera®
– DSP Builder
– DSP Builder Advanced Blockset
9
HDL Coder
HDL code generation from MATLAB code, Simulink models, and Stateflow charts
– Target-independent HDL code
– IEEE 1376 compliant VHDL
– IEEE 1364-2001 compliant Verilog
Verification
– Generate HDL test bench
– Cosimulate with Mentor Graphics® ModelSim® or Cadence® Incisive®
Workflow integration
– Integration with FPGA implementation tools e.g., Quartus® II
– Optimize for area/speed
– Generate bit stream
– Back-annotation of timing to Simulink model
MATLAB®, Simulink ®, Stateflow®
Algorithm and System Design
Link for ModelSim
HDL
HDL Coder™
HDL Verifier™
FPGA ASIC FPGA ASIC
HDL
Veri
fy
Veri
fy
Gen
era
te
10
Digital Down Converter
DDC accepts
– A high sample rate passband signal
(may be 50 to 100 Msps)
DDC produces
– A low sample-rate baseband signal
ready for demodulation
HDL
HW Implementation Model
Fixed-Point Model
MATLAB/Simulink
Algorithm Model
11
Fixed-Point Analysis Digital Down Converter
Convert floating-point to fixed-point models
– Automatic tracking of signal range (also intermediate quantities)
– Fraction lengths recommendation
Bit-true models in the same environment
– Quantify the impact of fixed point quantization
Find and fix issues
with fixed point
easily
12
Automatic HDL Code Generation Digital Down Converter
Automatically generate bit true,
cycle accurate HDL code from
Simulink, MATLAB, and Stateflow
Full traceability between
model and HDL code
13
Simulink Library Support for HDL HDL Supported Blocks Over 170 blocks supported
Core Simulink Blocks – Basic and Array Arithmetic, Look-Up Table,
Signal Routing (Mux/Demux, Delay, Selector),
Logic & Bit Operations, Dual and single port
RAM, FIFO, CORDIC
Signal Processing Blocks – NCO, FFT, Digital Filters (FIR, IIR, Multi-rate,
Adaptive), Rate Change (Up-/Down-sample),
Statistics (Min/Max)
Communications Blocks – Psuedo-random Sequence Generator,
Modulator / Demodulator, Interleaver / Deinterleaver, Viterbi Decoder
14
MATLAB Function Block – Subset of the MATLAB language
for modeling and generating HDL implementations
– MATLAB Function Block Design
Patterns for HDL
Stateflow – Tool for graphical modeling of
Mealy / Moore finite state machines
MATLAB and Stateflow HDL Supported Blocks
16
Use Cases for HDL Coder
MATLAB, Simulink , Stateflow
Algorithm and System Design
Link for ModelSim
HDL
HDL Coder
HDL Verifier
FPGA ASIC FPGA ASIC
HDL
Veri
fy
Veri
fy
Gen
era
te
System-level designers new to
hardware design
Companies/design teams that have
adopted Model-Based Design
Target-independent HDL is needed
Safety-critical applications (DO-254)
Retargeting algorithm between
software and hardware
Model includes MATLAB code or
Stateflow charts
17
Altera DSP Builder
Generates HDL optimized for Altera FPGAs from Simulink
Key Optimizations
– Silicon Architecture Aware
– Constraint Driven Design
Supports Floating Point
– Single Precision
– Double Precision
Verification
– Generate HDL test bench
– Cosimulate with ModelSim
Simulink
Algorithm and System Design
Link for ModelSim
HDL
DSP Builder
FPGA ASIC Altera
FPGA
Altera
HardCopy® ASIC
HDL
Veri
fy
Veri
fy
Gen
era
te
18
Altera DSP Builder
Simulink – Sources
– Sinks
– Continuous
– Discrete
– Nonlinear
– Math
Altera DSP Builder Advanced Blockset
Altera DSP Builder Blockset
Fixed-Point Blockset
DSP System Blockset
Simulink Coder
Communications System Blockset
Image Acquisition Toolbox
others
19
Altera DSP Builder Design Flow
MATLAB® / Simulink®
(System simulation and verification)
HDL / Hardware Domain ( Hardware implementation / RTL simulation)
20
Constraint-Driven Design (1)
1. Choose your type – Fixed or Floating Point
21
Constraint-Driven Design (2)
Use ModelIP or ModelPrim libraries
ModelIP
ModelPrim
2. Create Model
22
Constraint-Driven Design (3)
Device-independent modeling up to this level
Stratix II
AUTO
3. Select Device
23
Automatic pipelining or time sharing (ModelIP)
4. Set Frequency
Constraint-Driven Design (4)
24
Constraint-Driven Design (5)
5. Compile
25
Math.h Functions
Math.h - SIN - POW(x,y)
- COS - LDEXP
- TAN - FLOOR
- ASIN - CEIL
- ACOS - FABS
- ATAN - SQRT
- EXP - DIVIDE
- LOG - 1/SQRT
- LOG10
Implemented in Floating Point
26
Complex Functions Easily Realized in FPGA
27
Supports Single and Double Precision
Including complex (c)
28
Supports Fixed Point and Floating Point
Within the same model
29
Loop Block for “For i…” Loops
30
Nested Looping Functionality
31
Use Cases Summary
HDL Coder
System-level designers new to
hardware design
Companies that have adopted
Model-Based Design
Target-independent HDL needed
Safety-critical applications
Retargeting algorithm between
software and hardware
Model includes MATLAB code or
Stateflow charts
Altera DSP Builder
Hardware designers new to
Model-Based Design
Optimized for all Altera devices -
even ones we haven’t built yet
Constraint driven for high
performance designs
Supports floating-point
implementation
Supports integration into larger
systems with Altera Qsys
32
1. Visit mathworks.com/fpga
Get free FPGA Design Information Kit • View webinar – “Accelerate FPGA Design Using
Simulink HDL Coder”
Request trial of HDL Coder
2. Visit altera.com/dspbuilder
Technical resources
Request trial
3. Questions?
Write to [email protected]
Next Steps
MATLAB and Simulink are registered trademarks of The MathWorks, Inc. See www.mathworks.com/trademarks for a list
of additional trademarks. Other product or brand names may be trademarks or registered trademarks of their respective
holders