Reducing the cost of FPGA/ASIC Verification with MATLAB ... · PDF fileReducing the cost of...
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1 © 2015 The MathWorks, Inc.
Reducing the cost of FPGA/ASIC Verification with
MATLAB and Simulink
Graham Reith
Industry Manager – Communications, Electronics and Semiconductors
MathWorks
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Who are MathWorks?
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Motivation
Algorithm development often starts in MATLAB & Simulink
– Mathematical algorithms, complex logic and state machines
MATLAB & Simulink provide a means to
– Simulate across multiple domains
– Develop bit-true and cycle-accurate simulations
– Improve quality of testing early in design process
These models are also valuable to implementation and verification activities
– Reference models for downstream verification
– Models as the source for implementation RTL
Why repeat work that has already been done?
– More effort
– Increases risk of errors introduced through manual translation
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Agenda
Model-Based Design for FPGA and ASIC
Generating HDL Code from MATLAB and Simulink
– For prototyping and production
Verifying HDL Designs with MATLAB and Simulink
– Co-simulation with HDL simulators
– FPGA-in-the-Loop verification
Verifying HDL Designs outside MATLAB and Simulink
– Generating code for integration with SystemC/TLM and SystemVerilog/DPI-C
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Model-Based Design for FPGA and ASIC
INTEGRATION
ALGORITHM IMPLEMENTATION
AL
GO
RIT
HM
TE
ST
& V
ER
IFIC
AT
ION
RF & Analog HDL
Transistor MCU DSP FPGA ASIC
C/C++
ALGORITHM DESIGN
Environment Models
Timing and Control Logic
Digital Models RF Models Analog Models
Algorithms
REQUIREMENTS RESEARCH
• Verify designs to detect errors
earlier in development
• Reuse testbenches
• Automate regression testing
• Generate bit-accurate models
• Explore and optimize
implementation tradeoffs
• Generate efficient code
• Model multi-domain systems
• Explore and optimize system
behavior
• Collaborate across multi-
disciplinary teams
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It’s about Collaboration
Usually, many engineers get involved in different parts of the design flow:
Each brings valuable expertise from their discipline
Model-Based Design aids collaboration across the project
– integrating the workflow
– providing the backbone of a common modelling environment
Algorithms
Systems Verification
Firmware
Etc.
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A Typical Model Structure
Algorithm interacts with outside environment through other components.
Algorithm is stimulated with data
Algorithm performance is analysed.
Algorithmic System-level Testbench
Component
Model Analysis
Component
Model
Environment
Model
Data
Source
Alg
ori
thm
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Verification at the Model Level
Simulink Verification & Validation
– Coverage results for tests that have been simulated
– Interfaces to Requirements Management systems
Simulink Design Verifier
– Generation of tests to deliver coverage
– Identification of unreachable code
– Formal proof methods against objectives
Algorithmic System-level Testbench
Component
Model Analysis
Component
Model
Environment
Model
Data
Source
Alg
ori
thm
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Algorithm Development Generation of HDL Source Code
HDL Coder
– Generation of synthesible RTL HDL
(VHDL or Verilog)
Support for
– MATLAB
– Simulink
– Stateflow
Workflow Advisor
– Guides through process
– Preparing model for generation of HDL
– Configuring HDL Generation options
– Integrated with FPGA synthesis tools for
timing annotation on model
– Configurations for turnkey FPGA targets
and IP Core generation
Algorithmic System-level Testbench
Component
Model Analysis
Component
Model
Environment
Model
Data
Source
Alg
ori
thm
RTL HDL
(VHDL, Verilog)
HDL Coder
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Simulink Library Support for HDL Generation
HDL Supported Blocks
~180 blocks supported
Core Simulink – Basic and Array Arithmetic, Look-Up Tables,
Signal Routing (Mux / Demux, Delays,
Selectors), Logic & Bit Operations, Dual and
single port RAMs, FIFOs, CORDICs, Busses
Digital Signal Processing – NCOs, FFTs, Digital Filters (FIR, IIR, Multi-
rate, Adaptive, Multi-channel), Rate Changes
(Up & Down Sample), Statistics (Min / Max)
Communications – Pseudo-random Sequence Generators,
Modulators / Demodulators, Interleavers / Deinterleavers, Viterbi Decoders, Reed Solomon Encoders / Decoders, CRC Generator / Detector
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MATLAB – Relevant subset of the MATLAB
language for modeling and generating HDL implementations
– Useful MATLAB Function Block Design Patterns for HDL
Stateflow
– Modeling FSMs (Mealy, Moore)
– Different modeling paradigms
(Graphical Methods, State
Transition Tables, Truth Tables)
– Integrate MATLAB code
MATLAB & Stateflow for HDL Generation
HDL Supported Blocks
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Critical Path Highlighting and Design Review
Feedback in Simulink
Review results in synthesis tools
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Algorithm Verification Data-driven Verification of HDL Source Code
Stand-alone HDL testbench
– Stand-alone
Executable in any 3rd-party HDL simulator
– Self-contained
Instantiated algorithmic RTL HDL (DUT)
Input stimuli stream at DUT top-level interface
Expected output stream at DUT top-level
interface
– Self-testing
Checks on bit and cycle accuracy
Handwritten or generated code
– With HDL Coder, RTL HDL and standalone
testbenches are created automatically
Algorithmic System-level Testbench
Component
Model Analysis
Component
Model
Environment
Model
Data
Source
Alg
ori
thm
Stand-alone HDL Testbench
RTL HDL
(VHDL, Verilog)
input
stimuli
expected
outputs
==
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Algorithm Verification Co-simulation for Verification of HDL Source Code
Co-simulation with 3rd-party HDL
simulator
– Reuse of existing testbench in
MATLAB/Simulink
– HDL code execution in 3rd-party HDL simulator
– Flexible HDL sources
Handwritten or generated code
– Automated generation of co-simulation
infrastructure
– Automatic handshaking
Combined analysis and debugging in both
simulators
Algorithmic System-level Testbench
Component
Model
Analysis
Component
Model
Environment
Model
Data
Source
Alg
ori
thm
Co-Sim
3rd-party HDL Simulator
RTL HDL
(VHDL, Verilog)
cosimWizard
(HDL Verifier),
HDL Workflow Advisor
(HDL Coder)
HDL Verifier
==
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Algorithm Verification FPGA-in-the-Loop Verification of HDL Source Code
FIL simulation with FPGA
development board
– Reuse of existing testbench in
MATLAB/Simulink
– HDL code execution on FPGA
– Flexible HDL sources
Handwritten or generated code
– Automated generation of co-simulation
infrastructure
Encapsulation of algorithm within
GBit Ethernet MAC, or via JTAG
– Automatic handshaking
Algorithmic System-level Testbench
Component
Model
Analysis
Component
Model
Environment
Model
Data
Source
Alg
ori
thm
FIL
filWizard
(HDL Verifier),
HDL Workflow Advisor
(HDL Coder)
HDL Verifier
==
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Integrating with other Verification Activities
Verification is the single biggest cost in hardware design
– Investment in developing simulations for verification
SystemVerilog and UVM test frameworks
SystemC/TLM virtual platforms
– Shift towards ‘model-based’ verification
Enabling techniques like Constrained Random testing
Rather than recreate a behavioural model, we can reuse the assets
developed in the system models in MATLAB & Simulink
– Maintains connection with earlier part of the flow
Removes risk of manual error in test framework
Avoids duplicating effort
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SystemVerilog Testbench Environment
System Verification Reuse of models in SystemVerilog Testbench
Code generation translates models
to other languages
(e.g. C, HDL)
– Implementation code
– Verification models
For verification, C code generation is
convenient
– analog and digital models
– Wider block and langauge support for C
generation
HDL Verifier extends code
generation tools to provide wrappers
for
– SystemVerilog DPI-C
– SystemC TLM
Algorithmic System-level Testbench
Component
Model Analysis
Component
Model
Environment
Model
Data
Source
Alg
ori
thm
Component
Model
DPI-C
HDL Verifier
Embedded Coder
DPI-C DPI-C DPI-C
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Component
Component Testbench
Example: Generating DPI-C code
Configure model as
fixed-step discrete
Select target file for
Embedded Coder: systemverilog_dpi_ert.tlc
Generated files: – DPI-C wrapper of C version of
algorthm
– Makefile for DPI-C
– SystemVerilog module definition
– Testbench to verify generated
module against model data
C Source and
Header files DPI-C wrapper
Source and Heade
gcc and VC
makefiles
SystemVerilog
Testbench
SystemVerilog
Module
Reference IO
Data
DO files to
Run testbench
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Summary and Next Steps
Improving integration across the complete design flow is delivering
significant benefit to companies already. STARC (Japanese semiconductor consortium) reported 50% reduction in project timescale
Consider how you are creating your verification models today
– Does it already exist in MATLAB?
– Does MATLAB provide a quick way of producing a reference?
Consider how closely verification activities are connected to other parts of
the design flow
– How can collaboration be increased?
– Reuse of test vectors, sharing of code?
– Improving quality of testing earlier?
Contact MathWorks to
discuss and review!