Microelectronics Journal 44 (2013) 454–461

Contents lists available at SciVerse ScienceDirect

Microelectronics Journal

0026-26

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n Corr

E-m

journal homepage: www.elsevier.com/locate/mejo

Interconnect optimization to enhance the performanceof subthreshold circuits

S.D. Pable a,n, Z.H. Mohd. Hasan b, S.A. Abbasi c, A.R.M. Alamoud c

a Matoshri College of Engineering and Research Centre, Nashik, Maharastra, Indiab Z.H. College of Engineering and technology, AMU Aligarh, Indiac Department of Electrical Engineering, King Saud University, Riyadh 11421, Saudi Arabia

a r t i c l e i n f o

Article history:

Received 30 January 2012

Received in revised form

6 August 2012

Accepted 25 January 2013Available online 7 March 2013

Keywords:

Aspect ratio

Copper

Crosstalk

Interconnect

Mixed CNT bundle

92/$ - see front matter & 2013 Elsevier Ltd. A

x.doi.org/10.1016/j.mejo.2013.01.014

esponding author. Tel.: þ91 9970981824.

ail addresses: sachinp_79@yahoo.co.in, sdPab

a b s t r a c t

Subthreshold circuits are shown to be the best candidate for satisfying the ultra-low power demand of

battery-operated systems having moderate throughput. However, exponential increase in driver

resistance in subthreshold region and increased global interconnect capacitance will become a major

hurdle in improving the speed of subthreshold interconnects. Improving the speed of such low power

circuits is a major design challenge in ultra low power domain. This paper presents a comprehensive

analysis of Cu and mixed CNT bundle interconnects and investigates their performance in terms of

delay and energy delay product (EDP) for future subthreshold circuits. This paper mainly contributes

towards optimizing the geometrical (aspect ratio scaling) and process parameters of interconnects

especially for subthreshold circuits to increase their speed. Crosstalk analysis has also been carried out

with the proposed interconnect geometrical parameters. It has been found that aspect ratio scaling

significantly reduces the interconnect delay and switching energy and at minimum aspect ratio, Cu

wire performs better than even an optimized mixed CNT bundle for global interconnect length under

subthreshold conditions.

& 2013 Elsevier Ltd. All rights reserved.

1. Introduction

In recent years, most of the research work is targeted towardsminimizing the energy consumption at device and/or system levelto increase the battery life span for embedded applications. Ultra-low power (ULP) demand is mainly driven by applications likewireless sensors, body based sensors, and implanted medicalelectronics. To accomplish better power efficient designs, numer-ous power reduction techniques have been proposed in previousresearch including optimization of device parameters, architec-ture level optimization and supply voltage (VDD) scaling [1–5].Among all techniques, the most successful one is VDD scaling toeven below the threshold voltage (Vth) of the device [6–9].Subthreshold circuits are operated at VDD lower than Vth to satisfythe ULP demand of portable devices having performance as asecondary requirement. Subthreshold operation of digital circuithas become a popular design approach to achieve power efficientdesign for portable applications. Thus, in future CMOS technolo-gies, it is expected that subthreshold operation will dominateover super-threshold for ULP applications with lower operatingfrequency range. However, as VDD scales below Vth, delay

ll rights reserved.

le@gmail.com (S.D. Pable).

increases exponentially which indicates that the resistance ofsuch subthreshold device increases exponentially with thedecrease in VDD. Recently, while designing low power circuits,importance is given to operate the device at minimum energydelay point (EDP) instead of minimum energy point (MEP) toachieve moderate speed along with ULP. It is observed from Fig. 1that the minimum energy operation in subthreshold region for afan out of four (FO4) inverters results in significant penalty inspeed, which limits the expansion of application domain ofsubthreshold circuits towards Field Programmable Gate Arrays(FPGAs). It has been observed that minimum EDP for 32 nm FO4occurs at VDD¼0.4 V in subthreshold operating region.

The enhancement in integrated circuit density (Moore’s Law)and performance improvement have been achieved by evolution-ary device scaling and/or increase in chip size. Technology scalingat each node brings faster and more leaky transistors and worsensthe global interconnect performance. The interconnect becomesthe most limiting aspect affecting the functionality of ULP circuitsdue to the increase in resistance at every technology node [10,11].Carbon nanotube (CNTs) bundles have shown a lot of potential toreplace copper interconnects at nanometer technology node dueto their excellent electrical and thermal properties for superthres-hold circuits [12,13]. However, the suitability of CNT interconnectbundle as an interconnect for subthreshold operating region hasnot been established in previous research. The CNT bundle

0

2

4

6

8

0.14 0.2 0.3 0.45 0.65 1.12 2.6 7.31Delay (ns)

Ener

gy (f

J)

Emin

Dmin

Ultra low -energy

region

MDP

MEP

~50 x

~15

x

Subthreshold

region

Super threshold

region

ROI

Fig. 1. Energy delay tradeoff.

S.D. Pable et al. / Microelectronics Journal 44 (2013) 454–461 455

optimized for superthreshold region for maximum conductancemay not provide the optimum performance in subthreshold region.Hence, this paper is a first attempt to the best of our knowledge forperformance enhancement by optimization of both process andgeometric parameters of mixed CNT and Cu interconnects undersubthreshold conditions. It also explores the effect of crosstalk oninterconnect delay performance.

The rest of the paper is organized as follows. Section 2introduces previous work. Section 3 introduces subthresholdoperating region and interconnect design issues under subthres-hold conditions. Section 4 then investigates and optimize mixedCNT bundles process as well as geometry parameters under deepsubthreshold and moderate subthreshold conditions. This sectionalso compares the Cu and mixed CNT bundle in terms of speedand energy. Section 5 compares the crosstalk effect for Cu andmixed CNT bundles. Finally, section 6 concludes this paper.

2. Related work

With technology scaling, while the local interconnect capaci-tance reduces with every generation, the global interconnectcapacitance, however, increases with scaling. This is because thedie size is increasing with every generation resulting in largerglobal interconnect lengths. This increase in global interconnectlength effectively results in increase in the interconnect delay. Tocope with this problem, wires which are wider than theminimum-sized global interconnects provided by the technologyare used [10] under superthreshold conditions. Increasing thewidth of interconnect proportionally reduces its resistance perunit length, however it increases the interconnect capacitance perunit length hence this approach is not suitable for subthresholdcircuits.

The major research challenge in the subthreshold operatingregion is to take the ULP benefits obtained by aggressive voltagescaling but with minimal degradation in speed and robustness.Significant research work has been carried out on the perfor-mance enhancement of subthreshold circuits in terms of speedand robustness [6–8] by either device and/or circuit level opti-mizations. However, very little progress has been made toinvestigate and improve the performance of interconnects andclocking under subthreshold conditions [14,15]. Authors [14]address challenging design issues related with subthreshold FPGAand reported that designing functional and practical interconnectnetwork is a major challenge for subthreshold FPGA along withvariability issues and memory design. Subthreshold FPGA inter-connect resources causes almost 84% of total delay and consumes

70% of total energy [14]. Authors in [14] also reported that thedesign of reliable, low power, and fast interconnects posesa challenging area of research for subthreshold programmablelogic. Authors [15] proposed capacitive boosting technique toimprove the interconnect speed and robustness by shifting thedevice operating point to superthreshold region from subthres-hold operating region. Authors in this work successfully reported2.6 times switching speed enhancement and reduced 2.4 timesdelay sensitivity under temperature variations. However, thesepapers did not contribute towards interconnect level designunder subthreshold conditions. Authors in [16] proposed passiveVLSI interconnect layout with tapered tracks to enhance theoperating frequency by 33% and to reduce the power dissipationby 42% for superthreshold region. Authors in [11–13] investigatedthe suitability of CNT interconnects for superthreshold circuitsand proposed CNT as possible replacement for Cu wire due to itshigher conductance.

Though technology scaling improves the device performancesignificantly but the corresponding interconnect performanceimprovement is not substantial. Hence, the interconnect largelydetermines the performance of nanoscale systems [3,5]. In addi-tion, the design of long interconnect is crucial in enhancing theperformance of future subthreshold FPGA namely supply andclock signal lines.

Under superthreshold conditions, CNT interconnects showsignificant potential to replace Cu to achieve high speed as wellas lower power consumption [11–13]. However, very little pro-gress has been made to improve the speed of interconnects undersubthreshold conditions. It is well established that lower technol-ogy nodes (32/45 nm) are well suited for subthreshold applica-tions [17]. Hence, it is necessary to examine and optimize theperformance of interconnects at such a lower technology node. Atpresent, no researcher has investigated the suitability of CNTbundles as interconnect for ultra low power applications. There-fore, it is important to explore different materials (Cu, CNT, etc.)for interconnects and carry out parameter optimization to achievebest performance under subthreshold conditions. Hence, thispaper addresses the performance improvement of both Cu andCNT based interconnects by the optimization of their process andgeometrical parameters under subthreshold conditions.

3. Interconnect design issues under subthreshold conditions

3.1. Subthreshold interconnect design issues

The parasitic off-state subthreshold leakage current is used asa switching current in subthreshold operating region (VDDoVth).However, the amount of this current is very small leading toexponential rise in circuit delay, which limits the ULP circuitperformance and its application areas. The transistor outputcurrent in subthreshold region is modeled by the followingequation [18]:

ID ¼ I0eððVGS�VthþZVDSÞ=nVT Þ 1�eð�VDS=Vr Þ� �

ð1Þ

where I0 ¼ m0COXW=L ðn-1ÞV2T , ‘Vth’ is the threshold voltage, ‘n’ is

the subthreshold slope factor (n¼1þCd/Cox), Cd and Cox aredepletion and oxide capacitances respectively, ‘VT’ is the thermalvoltage and ‘Z’ is the DIBL coefficient.

As seen from (1), the subthreshold leakage current exponen-tially depends on VDD, which results in exponential increase indevice resistance [18]. Since the device is in OFF-state, itsresistance is extremely higher than the ON-state resistance undersuper-threshold region.

S.D. Pable et al. / Microelectronics Journal 44 (2013) 454–461456

Aggressive technology scaling ahead of Moore’s law increasesthe resistance of Cu wire causing delay and electromigrationproblems in super-threshold operating region [19]. However, insubthreshold region, electromigration issue is insignificant due tolower current density of subthreshold leakage current ({0.5–1 mA/mm) [19]. The effect of driver resistance on interconnectdelay can be effectively explored by the RC delay model ofinterconnect line driven by a CMOS driver and is given by [20]

Gd ¼ RdrivðCdrivþCloadÞþ0:4 RW CW L2

þðRdrivCWþRW CloadÞL ð2Þ

where Rdriv and, Cdriv is the driver resistance and capacitance, Rw

and Cw are the interconnect resistance and capacitance and Cload isthe load capacitance.

The interconnect resistance plays a significant role in deter-mining its performance under superthreshold conditions. How-ever, under subthreshold conditions, driver resistance is very highas compared to the interconnect resistance due to weak invertedchannel [21]. From (1) and (2), it has been observed that theinterconnect path delay is largely dominated by the driverresistance and the interconnect capacitance (Rw{Rdriv). Fig. 2shows the interconnect and the driver resistance comparison tohighlight the importance of driver Rdriv over RW under subthres-hold conditions [21]. Hence, it is important to reduce the deviceresistance and/or interconnect capacitance to improve the speedof interconnects for subthreshold circuits. Our previous work [21]has successfully improved the delay of FPGA interconnectresources by device optimization techniques. However, intercon-nect capacitance optimization is still unexplored. Therefore, thiswork mainly contributes towards reducing the interconnectcapacitance so as to enhance its speed.

It has been observed that inserting repeaters increases thedelay of very long line under subthreshold conditions [21]. Globalinterconnect used for clock line can reach upto several milli-meters. Hence, there is a need of performance optimization ofglobal interconnect for subthreshold buses and clock signaltransmission. The crosstalk effect may cause significant perfor-mance degradation under subthreshold operating conditions andhence crosstalk analysis has to be carried out under subthresholdconditions. In a nutshell, it is important to optimize both Cu andmixed CNT bundle for minimum capacitance rather than mini-mum conductance to extract the best performance under sub-threshold condition. This paper is a first attempt to achieveminimum capacitance for both Cu and CNT interconnect byprocess and geometric parameters optimization under subthres-hold condition. The next section explores performance of upcom-ing mixed CNT bundle used as an interconnect undersubthreshold conditions instead of Cu.

0

50

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150

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250

300

0.2/ 2

000.3

/ 400

0.4/ 6

000.5

/ 800

0.6/10

000.7

/2000

0.8/40

00

Supply Voltage(V) / Interconnect Length( m)

0.E+00

2.E+03

4.E+03

6.E+03

8.E+03

Wire

resi

stan

ce(

)

Buffer resistanceWire resistance

AOI

Buf

fer r

esis

tanc

e (M

)

Fig. 2. Buffer and wire resistances tradeoff in subthreshold region [21].

3.2. CNT interconnects

Carbon nanotube bundles as interconnect shows a lot ofpromise to replace copper interconnect due to their large con-ductivity and higher current carrying capabilities in future highspeed reliable superthreshold systems [22–24]. Our previouspaper successfully showed the suitability of SWCNT and Cuinterconnects under different subthreshold conditions [25]. CNTsare more suitable than Cu due to lower capacitance for short andintermediate interconnects under subthreshold conditions. How-ever, the performance of a realistic mixed CNT bundle undersubthreshold conditions has not been investigated. Hence, it isimportant to explore the suitability of a mixed CNT bundle forsubthreshold circuits.

CNTs can be thought of being made by rolling up a singleatomic layer of graphite to form a seamless cylinder. The resultingstructure is called a single-walled carbon nanotube (SWCNT). Ifseveral SWCNTs with varying diameter are nested concentricallyinside one another, then the resulting structure is called a multi-walled carbon nanotube (MWCNT) [26]. Authors in [27,28] showthat realistic nanotube interconnects will be a mixed bundle ofSWCNT and MWCNT. Mixed CNT bundle is a combination ofSWCNT with diameter (d) equal to 1 nm and MWCNT withmultiple shells with various diameters ‘d’ where (DminrdrDmax)as shown in Fig. 3 [27]. It is necessary to optimize the geometricaland process parameters of mixed CNT bundle to reduce itscapacitance under subthreshold operating conditions. The reduc-tion in interconnect capacitance significantly enhances the speedand also reduces the crosstalk and energy consumption.

The total capacitance of an isolated SWCNT is contributed bythe electrostatic capacitance (CE) and quantum capacitance (CQ).For given process parameters, CQ is fixed and remains constantwith varying geometrical parameters. The electrostatic capaci-tance CE is dependant on the geometry as well as processparameters. The effective bundle capacitance is given by [29]

CW ¼CEncntCQ

CEþncntCQffiCE ð3Þ

The resistance of the bundle is given by [29]

RW ¼RQ

ncnt1þ

L

L0

� �ð4Þ

where CW and RW are the effective CNT capacitance and resistancerespectively, RQ is the quantum resistance of an isolated CNT andncnt is the total number of CNTs forming the bundle.

Since the resistance and capacitance of interconnect stronglydepends on interconnect process and geometrical parameters andtherefore, improvement in subthreshold performance can be

MWCNT

Dmax

Dmin

SWCNT

d Mixed CNTBundle

Fig. 3. Mixed CNT bundles of SWCNTs and MWCNTs.

S.D. Pable et al. / Microelectronics Journal 44 (2013) 454–461 457

achieved by optimizing these parameters for minimum capaci-tance. Hence, the next section explores the optimization of mixedCNT bundle and Cu interconnects for minimum capacitance.

10

10

20

30

40

50R

esis

tanc

e (K

ohm

)

4. Optimization of copper and CNT bundle processand geometric parameters

4.1. Optimization and comparison of mixed CNT

bundle process parameters

Interconnect geometry structure, shown in Fig. 4 [30], and mixedCNT process parameters [27], are used to extract the RLC parametersfrom specific tool called ‘‘Carbon Nanotube Interconnect Analyzer’’(CNIA) [31]. The width of the interconnect is denoted by ‘W ’, thedielectric thickness (‘T ’) and height ‘H’¼(AR�W), where the aspectratio (AR) suggested by ITRS for global interconnect is taken as ‘3’[30]. The interconnect geometry structure shown in Fig. 4 gives anopportunity for redesign the values of width, thickness and heightunder subthreshold conditions. The spacing between two intercon-nect (‘S’) is assumed to be equal to the width of the interconnect [32].To account for imperfect contact, we have aggressively assumed20 kO Contact resistance (Rc) between CNTs and the metal for worstcase CNT interconnect analysis [24]. For long interconnect, 10�minimum driver size is assumed. Fig. 5 shows test setup used forinterconnect analysis. It is important to explore the appropriatemixed CNT bundle process parameters to achieve better delayperformance in case of subthreshold circuits. Mixed CNT bundleprocess parameters in [27] are optimized for maximum conductanceto increase the speed for super threshold circuits. However, forsubthreshold interconnect, the capacitance is the most vital designparameter instead of conductance. Hence, the capacitance has to beminimized for subthreshold interconnects. In the previous work, thecapacitance of mixed CNT bundle at rm¼1 is assumed to be equal tothat of Cu interconnect. However as metallic tube density decreases,the bundle capacitance reduces [24]. Therefore, it is necessary to

W

S

T

H

Ground

Ground

Fig. 4. Schematic of interconnect geometry under consideration for performance

comparison.

(RC+RQ)/2(RC+RQ) / 2

R/2 R/2

L/2 L/2

4CQ

CE Driver

Load

1 2

Fig. 5. Test bench used for performance analysis.

optimize the interconnect process parameters for minimum capaci-tance. At first, we have investigated the impact of different tubedensity and average tube diameter on subthreshold interconnectdelay and energy delay product. Fig. 6 shows the resistance as afunction of tube density and average tube diameter for 1000mm longmixed CNT bundle interconnect.

The tube density is varied from 1Eþ12 to 5Eþ12 tubes/cm2

and the average tube diameter is varied from 2 to 5 nm. Theprobability of metallic (rm) CNT is assumed to be 33% andDouter/Dinner¼0.5 is considered for the simulation purpose [27].Fig. 6 shows that the minimum tube density (1Eþ12 tubes/cm2)and the minimum avg. diameter (2 nm) corresponding to max-imum resistance. It has been observed from Fig. 7 that theminimum tube diameter gives minimum bundle capacitanceand it almost remains constant upon varying the tube densityfrom 1Eþ12 to 5Eþ12 tubes/cm2. Figs. 8 and 9 show the effect ofavg. tube diameter and tube density on delay and EDP responsesfor the interconnect test bench as shown in Fig. 5 under moderatesubthreshold conditions (VDD¼0.4 V). As shown in Fig. 8, mixedCNT interconnect bundle shows minimum delay and EDP inmoderate subthreshold region at avg. diameter¼2 nm and

23

45

23

45

x 1012

Avg. tube diameter (nm)Tube density

Fig. 6. Resistance as a function of tube density and diameter.

2

3

4

5

1

2

3

4

5

x 1012

108

109

110

111

112

Avg.tube diameter (nm)Tube density

Cap

acita

nce

(ff)

Fig. 7. Capacitance as a function of density and diameter.

2

3

4

5

1

2

3

4

5

x 1012

23

23.5

24

Avg.tube diameter (nm)Tube density

Del

ay (

ns)

Fig. 8. Delay as a function of tube density and tube diameter in moderate

subthreshold region.

23

4

51

23

45

x 1012

76

78

80

82

84

Avg. tube diameter (nm)Tube density

EDP

(e-2

5 Js

)

Fig. 9. EDP as a function of tube density and tube diameter at VDD¼0.4 V.

2

3

4

5

1

2

34

5

x 1012

260

270

280

290

300

Avg.tube diameter (nm)Tube density

Del

ay (n

s)/E

DP

(e-2

5Js)

Delay

EDP

Fig. 10. Delay and EDP as function of tube density and tube diameter at

VDD¼0.2 V.

S.D. Pable et al. / Microelectronics Journal 44 (2013) 454–461458

5Eþ12 tube density due to lower resistance and capacitance. Thedelay increases by 4.43% as the tube density varies from 5Eþ12 to1Eþ12 tubes/cm2. Also reducing the tube diameter from 5 to2 nm improves the delay by 3.56%. EDP obtained by diameter andtube density optimization for subthreshold region results in 6.7%improvement over EDP obtained with super-threshold processparameters optimized in [27].

Fig. 10 shows EDP and delay responses of mixed CNT bundleunder deep subthreshold conditions (VDD¼0.2 V). Increasing thetube diameter increases the delay by 1.7% and it remains constantwith the increase in tube density. This shows that lesser numberof tubes/bundle can be used under deep subthreshold operatingconditions due to increased driver resistance upon VDD scaling. Asmetallic CNT density decreases, the bundle capacitance reduces.Further, decrease in metallic CNT density from 33% to 10% andincreasing Douter/Dinner to 0.8 gives 6.13% improvement in delayunder deep subthreshold region. However, for moderate sub-threshold region, only marginal improvement in delay and EDPhas been observed due to significant increase in bundle resis-tance. Hence, by optimizing the process parameters of mixed CNTbundle under subthreshold conditions, the bundle capacitance isreduced by 10% with substantial increase in resistance.

It has been observed that mixed CNT bundle resistance increasesby reducing the metallic tube density due to the decrease in thenumber of metallic CNTs in a bundle. However, it reduces the bundlecapacitance which improves the interconnect performance undersubthreshold conditions. Therefore, this section concludes that, opti-mized mixed CNT bundle for minimum capacitance, and improvesboth the delay and EDP under subthreshold conditions, contrary tothe requirement of maximum conductance for superthresholdconditions.

4.2. Optimization of geometry parameter of Cu

and mixed CNT bundle

Interconnect geometrical parameters given by ITRS are typi-cally optimized for superthreshold applications by consideringthe conductance and electromigration as major design con-straints. However, the resistance of interconnect is a less sig-nificant design metric for subthreshold interconnects due to thehigher value of the driver resistance under subthreshold condi-tions. Hence, any decrease in interconnect capacitance with amoderate increase in resistance can improve the performance ofsubthreshold circuits. This can be achieved by using interconnectswith smaller aspect ratios. For super-threshold operating region,higher aspect ratio is preferred to avoid electromigration. Aselectromigration problem is negligible in subthreshold region,aspect ratio scaling gives an opportunity to improve the perfor-mance of subthreshold interconnect in terms of delay and EDP.From (5) and (7) it is clearly observed that reducing the inter-connect height decreases the interconnect capacitance.

Ct ¼ 2Cgþ2Cc ð5Þ

Cg ¼ eW

Hþ2:04

s

sþ0:54h

� �1:77 t

tþ4:53

� �0:07" #

ð6Þ

Cc ¼ e 1:41ðt=sÞe�4s

sþ 0:54Hþ2:37W

Wþ0:31s

� �0:28 H

Hþ8:96s

� �0:76

e�2s

sþ 6H

" #

ð7Þ

where, Ct is the total wire capacitance, Cg is the plate capacitanceper unit area, and Cc is the fringing capacitance per unit area [33].

It is necessary to investigate the effect of interconnect heightscaling on interconnect capacitance so that suitable aspect ratio

S.D. Pable et al. / Microelectronics Journal 44 (2013) 454–461 459

can be chosen under subthreshold conditions. Fig. 5 shows theinterconnect structure used for the performance comparison ofmixed CNT bundle and Cu interconnects. This section mainlycontributes towards exploring the effect of AR scaling on thecapacitance and hence the delay of Cu and mixed CNT bundle.

Fig. 11 shows the effect of AR scaling on the capacitance of mixedCNT bundle optimized in [27] for superthreshold region, mixed CNTbundle optimized in the above section for subthreshold circuits andCu interconnect. As shown in Fig. 11, the opt. mixed CNT bundleshows significant reduction in capacitance over mixed CNT bundleoptimized in [27] and Cu at AR¼3. Hence, for ITRS defined AR, mixedCNT bundle performs better than Cu at lower metallic density.However for AR¼1, the capacitance of Cu interconnect is lower thaneven that of optimized mixed CNT bundle for subthreshold circuits. Itis important to investigate the performance of opt. mixed CNT bundleand Cu interconnects over a wide range of global interconnectlengths. It has been observed from Fig. 12 that Cu performs betterthan mixed CNT bundle interconnect at AR¼1 under subthresholdconditions. The reduction of AR to 1 also saves 33% area.

The optimization of geometry parameter (Height) reduces theinterconnect capacitance much more significantly compared to theoptimization of process parameters of a mixed CNT bundle. However,the above comparison further reveals that scaled Cu performs muchbetter than conventional and optimized mixed CNT bundle undersubthreshold conditions. Hence, it is proposed that Cu wire is more

1 1.5 2 2.5 3400

500

600

700

800

900

1000

Aspect Ratio

Cap

acita

nce

(fF)

Opt.mixed CNT bundleMixed CNT bundle [25]Cu

L=5000um

Fig. 11. Capacitance as a function of aspect ratio.

500 1000 1500 2000150

200

250

300

350

400

450

Interconnect length (um)

Del

ay (n

s)

500 1000 1500 2000

20

25

30

Interconnect length (um)

Del

ay (n

s)

Opt. mixed CNT bundleCuMixed CNT bundle [25]

AR=1VDD=0.2V

VDD=0.4V

Fig. 12. Delay performance for different interconnect lengths.

suitable for long interconnect applications instead of a mixed CNTbundle under subthreshold conditions contrary to superthresholdconditions.

5. Effect of crosstalk on subthreshold interconnectperformance

As integration densities of on chip interconnect increases atevery technology node, crosstalk effect becomes more pro-nounced [33,34]. In order to keep crosstalk minimum, thecapacitance between two wires should not be too large [19]. Thisis feasible by breaking a long interconnect by inserting inter-mediate buffers. However, under subthreshold conditions, insert-ing repeaters increases the delay and switching energy and hencethis technique is not suitable for subthreshold circuits [21].Another approach of reducing the crosstalk is to use shieldingwire [35] which also increases the capacitive load and therefore,the delay [19]. To study the effect of crosstalk on victim line, wehave simulated the test setup shown in Fig. 13 [36] for differentsignal directions on aggressor 1, aggressor 2, and victim lines andcorresponding results are listed in Table 1. The driver sizeconsidered for the simulation purpose is 10x the minimum driversize [4] to drive a 5 mm interconnect length [37]. The intercon-nect geometry parameters at 32 nm technology node which areused to extract RLC values of interconnect are width¼70 nm,Interlayer dielectric thickness (ILD)¼154 nm [30], spacingbetween the interconnect is assumed to be equal to its width [32].

The delay variation due to crosstalk introduced by adjacent signaltransition is reduced by 31.58% for Cu and 20% for mixed CNTinterconnects at AR¼1 over AR¼3. This is due to decrease incapacitance by AR scaling. To study the effect of crosstalk ontransition-less victim line, a victim line is kept at low logic levelwhereas a low to high transition is applied on both the aggressorlines. The corresponding crosstalk induced noise is shown fordifferent AR in Fig. 14 and 15 for Cu and mixed CNT bundlerespectively. It is important to investigate and compare the effect ofadjacent signal transitions on delay and PDP of Cu and mixed CNTvictim lines due to crosstalk. Fig. 14, Fig. 15, and Table 1 effect ofcrosstalk for Cu and mixed CNT bundle. It is observed from Table 1that if subthreshold interconnect lines are running parallel to thewires with high frequency signal, then the crosstalk effect reducesover same frequency signal transition in opposite direction. It has alsobeen observed from Table 1 that the crosstalk has a large impact ondelay and PDP performance of subthreshold global interconnect.Hence, there is a need to reduce the crosstalk so that subthresholdcircuits perform well even for complex parallel interconnect archi-tecture like in FPGA.

It has been observed that mixed CNT bundle interconnect doesnot provide significant improvement in crosstalk-induced glitchover Cu due to higher coupling capacitance than the Cu wire atreduced AR. Therefore, it is clear from the above analysis that

Aggressor 1

CloadCw

Rw Lw

Cc

Rw Lw

Cw Cload

Rw Lw

Cw Cload

Aggressor 2

Victim Cc

Fig. 13. Schematic of equivalent circuit to model crosstalk between

adjacent wires.

Table 1Effect of signal transition on performance of global interconnect at AR¼1.

Aggressors transition Victim transition Mixed CNT bundle Cu

Delay (ns) PDP (fJ) Delay (ns) PDP (fJ)

Without aggressor Low to high 78.09 8.23 67.23 6.43

Low to high High to low 147.51 34.7 125 23.36

Opposite direction Low to high 108.09 16.68 85.96 11.7

Aggressor@ 0.9 V Low to high High to low 140 38.02 123 23.51

High to low @High Frequency Low to high 114.47 19.4 100.9 17.4

Low to high @High Frequency Low to high 98.41 13.7 85.43 11.5

Low to high Held at high Results in crosstalk induced noise on victim line as shown in Figs. 13 and 14

High to low Held at low

Fig. 14. Snapshot of signal transition due to aggressors transitions for Cu

interconnect.

Fig. 15. Snapshot of signal transition due to aggressors transitions for mixed CNT

interconnect.

S.D. Pable et al. / Microelectronics Journal 44 (2013) 454–461460

mixed CNT bundle is not suitable for global interconnect com-pared to Cu under subthreshold conditions.

6. Conclusion

This paper has successfully carried out comprehensive perfor-mance investigation of mixed CNT bundles and Cu interconnectsby process parameters and aspect ratio optimization underdifferent subthreshold conditions. It also explored the effectivereduction of crosstalk and delay in global interconnects by using

aspect ratio scaling. It has been found that the performance ofinterconnect under subthreshold conditions is primarily deter-mined by the driver resistance and the interconnect capacitanceand not by its resistance contrary to superthreshold conditions.This work concluded that the optimization of interconnect geo-metry parameters results in best performance improvementunder subthreshold conditions. Aspect ratio reduction increasesthe interconnect resistance but reduces its capacitance and there-fore, results in better interconnect speed and lower EDP. Hence,re-designing of interconnect geometry parameters results inimprovement in delay and crosstalk for Cu and mixed CNT bundleinterconnects. This paper also concluded that mixed CNT bundleinterconnects are not suitable in subthreshold operating region. Ithas also been found that Cu interconnects with AR¼1 is moresuitable for global interconnects due to lower interconnectcapacitance compared to a CNT bundle under subthresholdconditions.

Acknowledgment

This work is funded by Grants received from Department ofScience and Technology, Government of India, under their FISTprogram.

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