Slide 1French 207 MAPLD 2005

Integrated Tool Suite for Post Synthesis FPGA Power Consumption

Analysis

Matthew French, Li WangUniversity of Southern California, Information Sciences Institute

Tyler Anderson, Michael WirthlinBrigham Young University

Slide 2French 207 MAPLD 2005

Power Tools: Goals

• Push power analysis, visualization, and optimization to front of the tools chain:– Analyze power consumption at logic simulation

with two levels of accuracy• Pre-place-and-route, using heuristic

estimates based on fanout• Back-annotated with precise post-place-

and-route RC data– Visualize by providing intuitive views to help

the designer rapidly find and correct inefficient circuits, operating modes, data patterns, etc.

– Optimize systems by automatically identifying problem paths and suggesting improvements

• Benefits– Closer to logical level and design entry– Power profiling during functional simulation– Early estimation before place and route– Automatic specific resource utilization power

details – Facilitates high level design alternative

exploration

FPGA Tool Flow

Proposed Power Tool Entry Point

Current Power Tool Entry Point

Slide 3French 207 MAPLD 2005

Tool Backbone: JHDL & EDIF Parser

• Leverage JHDL simulation Environment with EDIF Parser circuit manipulation• JHDL

– Java-based structural design tool for FPGAs– Circuits described by creating Java Classes– Design libraries provided for several FPGA families– http://www.jhdl.org

• JHDL design aides– Logic simulator & waveform viewer– Circuit schematic & hierarchy browser – Module Generators

• Circuit designer does not need to know Java!

JHDLData

StructureEDIFNetlist

EDIFData

Structure

ManipulationTools

EDIFParser

3rd PartyTools

• EDIF Parser– Supports multiple EDIF files

– Virtex2 libraries and memory initialization

– Support for “black boxes”

– No JHDL wrapper required

– http://splish.ee.byu.edu/reliability/edif/

– Verified: Synplicity, Synplcity Pro, Coregen, System Generator, Chipscope

JHDL Environment

EDIF Parser

Slide 4French 207 MAPLD 2005

Power Visualization Tool

• Two views:– Instantaneous vs. cumulative power

consumption over time

– Sorted tree view of “worst offenders”

• Integrated “cross-probing” with existing JHDL tools– Unified Environment

– Allows Experimentation

– Smart Re-use of CPU Memory

• Help rapidly identify inefficient circuits and operating modes

• Per-cell / per-bit granularity

• Simulation trigger on power specification

Cross Probing

Slide 5French 207 MAPLD 2005

Post Synthesis Level Power Modeling

• Power Modeling– Quiescent power based on total circuit size– Dynamic Power

• Toggle Rates (Data Dependant)• Components Used• Routing Interconnect

– Actual quiescent and dynamic power not known until circuit is placed and routed

• Leverage existing JHDL tool environment– Toggling rates derived from simulator

• Will lose glitching information– Components known from EDIF or JHDL primitives

• Component capacitance imported from Xpower

– How to model routing interconnect?• Do not have exact routing information at

synthesis• Routing tools can pick different route each

iteration– Interconnect length and combinations vary

))()((% WireComponentClock CapCapFreqtogglePower Component Cap

(pF)Component Cap

(pF)

FF 1.21 LUT 1.0

SRL 3.0 LD 1.0

INV 1.0 AND 1.0

RAM 1.0 MULT 17.2

DLL 40.0 IBUF 1.0

BUFG 6.0 BRAM 59.0

Xpower Component Capacitance

Interconnect Cap (pF)

Long Line 11.8

Hex Line 0.59

Double Line 0.44

Direct Connect 0.29

Xpower Interconnect Capacitance

Slide 6French 207 MAPLD 2005

Capacitance vs Fanout

• Fanout model well correlated

• Secondary fit line corresponds to Macros

• High variance at low fanout

• Achieving 4.3% average error, 16% variance

• Explored device utilization models as well

Placement Macros

Slide 7French 207 MAPLD 2005

Resulting Power Tool Flow

Source Code

Synthesis

Map Place & Route

Xpower

Bitgen

EDIF Parser

JHDLPower Analysis & Visualization

Virtex II Power Model

Routed Circuit Model

EDIF

VHDL Verilog JHDL

Xilinx Tool Flow

.ncd .ncdTo Target

.pwr

Power Tools

Slide 8French 207 MAPLD 2005

Power Optimization Approach

• Influence Xilinx Place&Route tools for power efficiency– Minimize clock/wire lengths of high power nets

• Use power analysis tools to identify hot-spots and generate constraints– Timing constraints on non-clock signals

– Location constraints on sink flip-flops of clock signals

• Timing Constraints– Over-constrain timing for power

– Achieving up to 12% power reduction

• Location Constraints– Pares clock tree

– Achieving up to 23% power reduction

– Several placement strategies

• Not violating original circuit timing specifications

Timing Constraint

(ns)

Placement Constraint

(X,Y)

Unconstrained Constrained

Slide 9French 207 MAPLD 2005

Conclusions

• Post-synthesis level power modeling is feasible– Some accuracy trade-offs inevitable– Quicker power results enable

• Capability to determine power specifications early in the design flow

• Feedback on design-level circuit power ramifications• Tighter feedback loop to designer for more design

iterations

• Optimization– Preliminary results encouraging– Tools do not alter original circuit functionality & use COTS

inputs– Developing optimization algorithms & routines

• Tools are open source: http://rhino.east.isi.edu• This research made possible by a grant from

the NASA Earth-Sun System Technology Office