Synthesis of Signal Processing on FPGA
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April 15, 2003 1 Synthesis of Signal Processing on FPGA Hongtao Du @AICIP.ECE.UTK
description
Synthesis of Signal Processing on FPGA. Hongtao Du @AICIP.ECE.UTK. Getting started What is VLSI? ASIC family members Carrying on VHDL Synthesis structure Do it yourself Parallel ICA Re-configurable components. Development of VLSI. Integrated Circuit (IC): - PowerPoint PPT Presentation
Transcript of Synthesis of Signal Processing on FPGA
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Getting startedWhat is VLSI?ASIC family members
Carrying onVHDL Synthesis structure
Do it yourselfParallel ICARe-configurable components
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Development of VLSIIntegrated Circuit (IC):
A microelectronic semiconductor device consisting of many interconnected transistors and other components.
ICs are fabricated (constructed) on a die (a small rectangle) cut from a silicon wafer.
Containing logic gates: inverters, AND, OR, NAND, NOR, etc.
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(continue)
Small Scale Integration (SSI) -- tens transistors Medium Scale Integration (MSI) -- hundreds transistorsLarge Scale Integration (LSI) – thousands transistorsVery Large-Scale Integrated Circuit (VLSI) has hundreds of thousands.One megabyte RAM contains more than one million transistors, developed in 1986 Wafer-scale integration
The most extreme technique.Using whole uncut wafers as components.
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ASIC Family
ASIC
PLD
FPGA
MGA
Standard Library Cells
Analog / Digital Mixed Technologies
Full-Custom
Semi-Custom
Programmable
Non-programmable
PLD: programmable logic deviceMGA: mask gate array
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FPGA v.s. PLDFPGA
Best for low quantity applicationsVendor prefabricates rows of gates and programmable connectionsUser specifies connections to implement logic functionsReplaces 2,000 to 2,000,000 gates Implementation time: within hoursDevelopment system cost: $5,000 – 10,000 (PC-based)
PLDBest for simple design
Vendor prefabricates multiple sets of gates with programmable connections
User specifies connections to implement logic functions
Replaces 300 to 8,000 gates
Implementation time: within minutes
Development system cost: $3,000 – 5,000 (PC-based)
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MGA and Standard Library Cells
MGABest for moderate-sized designsVendor prefabricates rows of gates and wafersUser specifies two layers to implement logic functionsReplaces 10,000 to 10,000,000 gatesAfter place & route, masks are made for two layersDevelopment system cost: $ 50K (Workstation-based)Turnaround time for prototypes: 3 -- 5 weeks
Standard Library CellsBest for high quantity applications with multiple functions, such as CPU and RAM.User selects cells and specifies two layers of interconnections.Replaces 100,000 to 10,000,000 gatesAfter place & route, masks are made for all layersDevelopment system cost: $100K (Workstation-based)Turnaround time for prototypes: 8 weeks
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FPGA FeaturesAdvantages
Rapid prototyping
Low risk
Low testing costs
Standard product advantages
Life cycle, reusable
Disadvantages Chip capacity and cost
Speed of circuit
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Getting startedWhat is VLSI?ASIC family members
Carrying onVHDL Synthesis structure
Do it yourselfParallel ICARe-configurable components
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VHDLHardware Description Language (HDL).
VHDL: VHSIC (Very High Speed Integrated Circuit) Hardware Description Language.Developed to standardize documentation for maintenance and possible redesign, by DOD.IEEE VHDL standard approved in 1987.
Verilog:Developed for verification of logic, by Gateway Automation.
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sorting:PROCESS(clock)
BEGIN
if clock'event and clock='1' then
if all_ic_input_ok='1' and all_ic_output_ok='0' then
……if sort_weight(loop_count+1) >=
sort_weight(loop_count) then
temp1 <=
sort_weight(loop_count);
sort_weight(loop_count) <=
sort_weight(loop_count+1);
sort_weight(loop_count+1) <=
temp1;
temp2 <=
sort_band(loop_count);
sort_band(loop_count) <= sort_band(loop_count+1); sort_band(loop_count+1) <= temp2; change <= '1'; change_count <= loop_count+1; end if; loop_count <= loop_count + 1; end if; if loop_count = band-2 then loop_count <= 0; sort_count <= sort_count + 1; end if; if sort_count=band-1 then all_ic_output_ok <= '1'; end if;
……END PROCESS sorting;
Example: Comparing
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Synthesis structure
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Getting startedWhat is VLSI?ASIC family members
Carrying onVHDL Synthesis structure
Do it yourselfParallel ICARe-configurable components
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Parallel ICA Diagram
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Synthesis Structure
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Structure of Component OneUnit
Loop until
Converge
Normalize
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3)( xxg
InitializeWeight Vector
Update
Compute 23)(' xxg
www /
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Structure of Component Decorrelation
p
jjj
Tp www
11
1111 / pTppp wwww Loop until
Converge
Normalize
Independent Component Input
Update
Decorrelate
p
jjj
Tp www
11
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Structure of Component Comparing
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Coverage of Re-configurable Components
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Pre-layout SimulationsComponents:
One-unitDecorrelationComparing
Top level
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Layout Simulation
Xilinx Virtex 1000EHQ240Estimating 4 Independent Components 92% utilization
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Post-layout Simulation
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Design and FPGA Capacity
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Conclusion
FPGA is an efficient solution for signal processing.
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ReferenceDeniel D. Gajdki and Loganath Ramachandran. Introduction to high-level synthesis. IEEE Design and Test of Computers, pages 44–54, 1994.
Don Bouldin. ECE 551: Designing application-specific integrated circuits, Fall 2001.
Don Bouldin. Design of Systems on a Chip, chapter Synthesis of FPGAs and Testable ASICs. Kluwer Academic Press, 2003.
Habib Youssef Sadiq M. Sait. VLSI Physical Design Automation, Theory and Practice. World Scientific Publishing Company, June 1999.
