Specifications for the IceRay Sampler (IRS) ASIC

Gary S. Varner a,∗ Larry L. Ruckman a and Pisin Chen b Chih-Ching Chen b

Chiu-Chuan Yao b

aDepartment of Physics and Astronomy, University of Hawaii, 2505 Correa Road, Honolulu HI 96822, USAbLeung Center for Cosmology and Particle Astrophysics, National Taiwan University, Roosevelt Road, Taipei, 10617

Taiwan (R.O.C.)

Abstract

We present the specifications and design concept for a waveform sampling ASIC tailored to the needs of an extendedin-ice Askaryan-effect radio neutrino array. Compared with the LABRADOR3 ASIC flown twice on the ANITApayload, far deeper sampling (65,536 versus 256) is realized, permitting sub-threshold forced readout, which shouldextend both the reach and flavor-ID of a 10km scale detector.

Key words: Gigasample/s waveform digitization, radio neutrino detectionPACS: TBD though NOT: 29.40.Ka, 29.40.Mc, 87.57.uk

1. Background

A first prototype IceRay detector [1] station wasfabricated in 2007. It has not yet been deployed atSouth Pole. At that time the LAB3 ASIC [2], al-ready having successfully flown on the first ANITAmission and also operated in AURA prototypes [3]in the IceCube array, were used. Inasmuch as eachIceRay station can be treated as a “mini ANITA”,this is a reasonable choice. However the benefits ofbeing able to read out antennas that might be be-low threshold to trigger were highlighted in studiesof an embedded salt array [4].

Since that time further extensions and improve-ments to the LABRADOR waveform sampling

∗ Corresponding author. Tel.: +001 808-956-2987.Email address: varner@phys.hawaii.edu (Gary

S. Varner).

ASIC have been realized in a series of devices thatexplored deeper [5] and faster [6] sampling, on-chip encoding [7], and much higher bandwidth [8].In particular, it has been pointed out that deepsampling can significantly enhance neutrino flavoridentification by observing sub-threshold emissionof the lepton during propagation through the ar-ray [9]. The required sampling depth for a fullIceRay detector is of the order of the transit-timeacross the array, approximately 10km in length,or about 30μs.

Specific ways in we plan to optimize the wave-form sampler performance to match the needs ofIceRay are– 64k deep sampling on each channel– improved input bandwidth– reduced cross-talk– faster readout

Preprint submitted to Elsevier Science 10 April 2009

2. System Overview

An overview of a composite IceCube + IceRayevent is illustrated in illustrated in Fig. 1.

Fig. 1. Overview of one possible IceRay configuration,where a hybrid event with IceCube is illustrated. Each reddot represents a detector station. Improved flavor ID isobtained by reading out each station, even if below self--trigger threshold.

Each station consists of an array of antennasand supporting amplifiers and EMI-shielded read-out housings. The geometry considered for an ini-tial prototype deployment is illustrated in Fig. 2,where it should be noted that future deploymentswould benefit from embedding the antennas fur-ther into the ice (below the firn layer).

Details of the support electronics are sketchedin Fig. 3, where the existing LAB3 digitizer ASICsmay be seen. While the layout for a new ICRR tosupport the IRS ASIC will need to change, electri-cally it is very similar to that shown here.

Fig. 2. Layout of an IceRay prototype testbed station.

4x2

4x2

LAB3

LAB3

LAB38

Virtex−4

FPGA

TRACR2

FPGA

EEPROM

DOM−MB

ATWD

event timing

TriggerInputs

8

8

DigitizerInputs

2GSa/s

2GSa/s

1GSa/s

bandpassfilters

shielded housing

LNA 2nd stage amp38 dB 38 dB

ReceiversFrom

to ICRR

ICRR*

*ICRR=IceCube Radio Readout

Standard IceCubeCommunications

FreqLow

High Freq.

Tunnel Diodes

Receiver Module (4 chan total, 4 modules)

batwing

discone(Vpol, 0.1−1 GHz)

(HPol, 0.1−0.4 GHz)

Fig. 3. Layout of an IceRay prototype testbed station.

3. Specifications

In order to meet the requirements mentionedabove, an Application Specific Integrated Circuit(ASIC) is being designed to the set of specifica-tions listed in Table 1. An acronym indicative of itsfunctionality has been choosen: the IceRay Sam-pler (IRS). Of note in this description table is thestorage depth, which provides for greater than 65μsstorage. Moreover, it is possible to cascade IRSASICs and extend this value to even deeper values.

2

Table 1Key Specifications of the IRS ASIC.

Parameter Value Comment

Number Channels 8 1 chip/antenna type

Storage cells/channel 65,536 216 total

Timing Strobe 1 Array synchronous

Analog bandwidth ≥ 1GHz depends on antenna

Sampling Rate 1 − 2 GSa/s adjustable

Conversion cycle ≤ 1µs for 512 samples

Local hit latency ≈ 10µs for 8*(256) samples

Local event size ≈ 4kBytes per IRS

Full chip readout ≈ 12.5ms for 8*64k (512k) samples

Max event size ≈ 1MByte per IRS

Synchronous sampling is provided at each sta-tion. Currently synchronization between stationsis provided by GPS 1PPS marker, though futuredeployments may use a dedicated fiber link.

4. Concept Implementation

In the following subsections we describe thecircuit subcomponents we have evaluated andchoosen, as well as calculations and/or simula-tions of the expected performance. A conceptualsummary is presented in Fig. 4, with key blocks inwhite board “brainstorm” mode.

Fig. 4. Sketch of the IRS concept details.

4.1. Input Coupling

Achieving improved analog bandwidth requiresa better understanding of both the integrated cir-cuit and board implementation. The latter is cru-cial though beyond the scope of this paper. Fromprevious experience in similar waveform samplingdevices [2,5], we expect that wire bonding will limitperformance.

A simple representation of the coupling from thephotosensor into one of the storage channels of theIRS is represented in Fig. 5. At the left is the physi-cal circuit representation. At right, the impedanceof the input capacitance (CT ) is in parallel withthe termination resistor (RT ), ZT = RT +ZC andRT = 50Ω.

RFamp

Ω50 C in

inside ASIC

VinVsig

ZT

Z S Z S

Fig. 5. Simple model of input coupling. At left the physicalcomponents, at right the simplified schematic representingthe relevant low-pass filter that models the input couplingresponse.

Using the expression for an impedance divider,

Vin =ZT

ZS + ZT· Vsig (1)

we can express the gain of the circuit:

Gain = G =ZT

ZS + ZT=

RT ||ZC

ZS + RT ||ZC(2)

where RT ||ZC can be reduced as

RT ||ZC =RT

jωCin

RT + RT

jωCin

=1

1RT

+ jωCin

(3)

The gain can then be expressed as

G =

11

RT+jωCin

ZS + 11

RT+jωCin

(4)

which can be simplified by multiplying throughby 1

RT+ jωC and taking ZS = 50Ω, yielding

3

G =1

RS

(1

RT+ jωCin

)+ 1

=1

1 + RS

RT+ jωRSCin

(5)

In the limit ω → 0 the gain is simply the expres-sion

G =1

1 + RS

RT

(6)

and for a matched impedance: RS = RT ob-tain G = 1

2 . This this static gain factor is alwayspresent, in terms of the usual expression for a low-pass filter, we factor out the static resistive dividerand define G = 1 as ω → 0. In this case, the ex-pression simplifies to

G =1

1 + jωRSCin. (7)

Taking the magnitude of the Gain:

|G| =1√

1 + (ωRSCin)2(8)

where ω = 2πf . The frequency dependence asa function of f for Cin = 300fF and RS = 50Ω isseen in Fig 6 below.

Input coupling versus frequency

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0.1 1 10 100

Frequency [GHz]

Rel

ativ

e am

plitu

de [d

B]

Cin=300fF, Rs=50Ohm

Fig. 6. Input gain into the ASIC as a function of analogbandwidth.

Taking the usual convention that the analogbandwidth is defined by the point where the am-plitude of the coupled signal has dropped by 3dB.By inspection of Fig. 6, it is seen that this pointis about 10GHz for the assumptions taken. In-specting the expression for gain, this -3dB point

corresponds to the value where the amplitude hasdropped to 1√

2of its value. This occurs under the

condition where

ωRSCin = 1 or 2πf3dB =1

RSCin(9)

which then reduces to the familiar expression

f3dB =1

2πRSCin(10)

For a source impedance of 50Ω, the dependenceon the input capacitance is shown graphically inFig. 7.

Input Coupling versus total input Capacitance

0

5

10

15

20

25

30

35

0 100 200 300 400 500 600

Total input Capacitance [fF]

Ana

log

Ban

dwid

th [-

3dB

freq

uenc

y] R_S = 50Ohm

Fig. 7. Analog bandwidth versus input capacitance (Cin).

Finally, for an input capacitance Cin of 300fF,the analog bandwidth dependence upon sourceimpedance RS is plotted in Fig. 8.

Depending upon the actual source impedancerealized for the photodetector, it may be necessaryto use an RF amplifier upstream of the device, inwhich case the 50Ω point is the relevant point forcomparison.

4.2. Packaging Effects

The attainable maximum input coupling fre-quency of the ASIC will be degraded when actu-ally packaged. In particular the lead inductancecan and will limit analog bandwidth. This realitymodifies the simplified input schematic of Fig. 5 asshown in Fig. 9, with the addition of an inductancerepresenting the package input connection.

4

Input Coupling versus source impedance

0

5

10

15

20

25

0 50 100 150 200

Source resistance [Ohm]

Ana

log

Ban

dwid

th [-

3dB

freq

uenc

y] C_in=300fF

Fig. 8. Analog bandwidth versus source impedance (RS)for a total input capacitance of 300fF.

RFamp

VsigC inΩ50

inside ASIC

VinZT

ZLZ S Z S

Fig. 9. Modified version of the simplified input circuit forevaluating in coupling to ASIC.

Addition of the bump bond or bonding wireadds a frequency-dependent reactance to the in-put. Also, in combination with the available capac-itances, can lead to resonance structures as a func-tion of frequency. The expression for this reactanceis

ZL = jωL (11)

and the magnitude of which is evaluated as

|ZL| = 2πfL (12)

and the equivalent resistance of which is plot-ted for a typical bond-wire (5nH) and bump bond(0.2nH) in Fig. 10. Already at 2GHz, the effectiveimpedance of the bonding wire has become compa-rable to the termination resistance, thus reducingthe signal available on the input, as well as caus-ing an impedance mismatch for a matched sourceresistance.

At the same time the signal amplitude is alreadyrolling off due the reactance of the input capaci-tance. To estimate the effect, we can pick up theline of reasoning that lead to Eqn. 7, where now

Input inductance impedance versus frequency

0

20

40

60

80

100

120

140

160

180

200

0.1 1 10 100

Frequency [GHz]

Impe

danc

e [O

hms]

Bond-wireBump-bond

Fig. 10. Impedance of typical input connections as a func-tion of frequency.

we instead replace RS with Zin = RS + ZL. Doingso leads to the following expressions for the gain

G =1

1 + jωCin (RS + jωLbond)=

11 + jωCinRS − ω2LbondCin

(13)

=1

(1 − ω2LbondCin) + jωCinRS(14)

Again, taking the magnitude

|G| =1√

(1 − ω2LbondCin)2 + (ωCinRS)2(15)

Inspecting this expression, it is interesting tonote that there is a resonance condition in the casewhere the squared term in the left bracket vanishes.That is, when

ω2LbondCin = 1 (16)

Solving for the frequency, we obtain the familiarexpression for an L-C oscillator:

f0 =1

2π√

LbondCin

(17)

For our two bonding interconnect conditions, as-suming Cin = 300fF this becomes

fwire0 = 4.1GHz and fbump

0 = 20.5GHz (18)

Actually, to treat this properly, both the signaland reference pad inductances need to be consid-ered. As the inductance of these depends upon the

5

actual number of reference bonds, a more refinedestimate will be attempted later, when other reali-ties are addressed. To get a feeling for this modifiedgain, we again evaluate Eqn. 15 versus frequencyin Fig. 11.

Input coupling versus frequency

-10

-8

-6

-4

-2

0

2

4

6

8

10

0.1 1 10 100

Frequency [GHz]

Rel

ativ

e am

plitu

de [d

B]

Bond-wireBump-bond

Fig. 11. Input coupling versus frequency for the modifiedgain due to the addition of inductance due to lead inter-connect. Very strong peaking is seen for the bonding-wirecase.

The dramatic peaking seen for the bonding wirecase is likely to be less prominent in the actual cir-cuit realization due to the reference voltage (termi-nation voltage), as well as effects mentioned next.First it is noted that this expression can be rear-ranged and solved for the f3dB expressions as wasdone previously. However, the simplification madeto highlight the possibility of resonance on the in-put coupling was to consider the short-cut thattook us from Eqn. 5 to Eqn. 7 is invalid. With theinclusion of the inductor impedance, this assump-tion breaks down. The term can be inserted, butthe complexity of the algebra begins to obscurethe pedagogical value of this exercise. Thereforefor subsequent full analysis, the SPICE simulationtool will be used to extract results. However it isuseful to sanity-check those results compared withthese simple estimates. Before throwing everythinginto a black box, it is useful to perform one addi-tional analytic estimate – that of the input cou-pling of each storage cell.

4.3. Storage Cell Coupling

Coupling into the storage cell is identical to thesimplified earlier case of a low-pass filter presentedearlier. When the storage switch is closed, it ischaracterized by an “on” resistance (Ron) and con-nected to a storage capacitor (Cstore). The gain isthen

|G| =1√

1 + (2πRonCstore)2

(19)

and the frequency dependence is plotted for 4representative values of the 2 parameters in Fig. 12.It is interesting to note that these correspond toscaling the previous input coupling case by a factorof 20 (100) in source resistance, leading to a similarscaling in the product for the capacitance at anequivalent -3dB frequency.

Input coupling versus frequency

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

0.1 1 10 100

Frequency [GHz]

Rel

ativ

e am

plitu

de [d

B]

C=15fF,Ron=1kC=15fF,Ron=5kC=25fF,Ron=1kC=25fF,Ron=5k

Fig. 12. Input coupling into storage cell for 4 possible switchon resistance and storage cell capacitance configurations.

So obviously we desire to keep the storage ca-pacitance as small as possible. However there is aclear limit to how far this can be taken. That is,counting statistics on the thermal fluctions in thesmall number of electrons representing a voltage onthis small storage capacitor. This so-called “kTC”noise can be expressed as a voltage fluctuation inwhat actually get stored when the storage capaci-tor switch closes:

vrms =

√kBT

C. (20)

6

For a 1V nominal dynamic range, this limitationin effective number of bits of resolution as a func-tion of storage capacitance is seen in Fig. 13.

Fig. 13. Dynamic range limitation versus storage capaci-tance for a nominal 1V storage range.

Below an estimate for the actual storage capac-itance of the proposed circuit is used.

4.4. Overall Signal Coupling

The resultant ability to couple in the analog sig-nal depends upon the effects described in the pre-vious two subsections. It is worth emphasizing thatif each stage independently degrades the signal by3dB, the effects are cumulative. Therefore the netresult is the crucial one.

5. Simulated Performance

We evaluate by SPICE the expected input per-formance, modelling the input as precisely as pos-sible. This lumped-element model is certainly lack-ing in the accuracy one might get from a 3-D EMsimulation of the transmission line characteristicsof the printed circuitboard and coupling into theASIC. However it is as detailed a simulation of timeand financial constraints permit.

5.1. Throughput coupling

Fig. 14 represents the circuit model of the inputcoupling.

Fig. 14. Input coupling circuit model for the IRS ASIC.

5.2. Flash Conversion Encoding

In order to speed the readout and reduce theprogrammable logic resource requiments for imple-mentation of a large number of channels, a flashencoding scheme [7] has been implemented. Thetiming sequence for each of the conversion chan-nels is displayed in Fig. 15.

Fig. 15. Fast storage conversion timing diagram.

6. Initial Evaluation System

The evaluation system will initially consists of asmall circuitboard, containing a wire-bonded IRSASIC. It will be read out over USB2.0 by a lap-top running a custom data acquisition programbased on the wxWidgets tool kit. A photo of similarand previous compact measurement system is dis-played in Fig. 16. This compact configuration canturn any PC (or laptop) into a high-performancedigital signal oscilloscope.

7

Fig. 16. Photograph of the “oscilloscope on a chip” testset-up, where the sampler ASICs are at the left, near theSMA input connectors.

7. Performance Results

This section to be completed when thetest results become available. For now thereare reference plots from BLAB2 as place-holders.

7.1. Sampling Rate

One technique experimented with in this versionwas that of using each stage of the inverter chain asa sample time reference. The power of this poten-tially allows for significant sampling speed increasein the same process used for BLAB1 [5], and mea-surement of the sampling pointer speed is reportedin Fig. 17.

An example of how the rows of 1024 samplesare stitched together for continuous sequencing isfound in Fig. 18.

0

1

2

3

4

5

6

7

1.5 1.75 2 2.25 2.5 2.75 3ROVDD (volts)

Sam

plin

g Sp

eed

(GSa

/s)

BLAB2_SamplingPRO1_Sampling

Fig. 17. Measured effective sampling speed of the two ref-erence timing chains...

Fig. 18. Recorded overlap sampling of the rows of samples...

7.2. Calibration

As have been noted, the sampling speed of thesedevices is intrinsically the temperature depen-dence [5,2]. By monitoring the reference timingchains mentioned above it is possible to make theseeffects essentially unmeasureable for slow drifts.

Fig. 19. Event-by-event sampling speed comparisons of twoBLAB1 ASICs indicating a common temperature depen-dence term. The sampling speed is continually monitoredand used in calibration to achieve the maximum timingperformance.

In order to address bin-by-bin timing widthdifferences, a couple of different calibration tech-niques have been tried. The first utilizes a sinewave zero-crossing technique used for calibratingthe LAB3 ASIC[2]. That technique works best

8

when the frequency of the sine wave is such thatthe measured interval between zero crossings canbe uniquely assigned to a limited number of binsbetween successive crossings.

Fig. 20. Aperture width determination for individual sam-ple cells via the histogram occupancy technique describedin the text.

Due to sine wave curvature, this technique hasan irreducible systematic error that is a functionof sample rate. A more successful technique is tohistogram the zero crossings of a sine wave and usethe bin occupancy to derive the effective aperturewidth, as may be seen in Fig. 20.

When a sampling strobe is inserted into theBLAB1, the strobe propagates across a SwitchedCapacitor Array (SCA) row and exits the ASIC viaa monitor pin. The sampling speed is determinedby measured this propagation delay, a methodimplemented by creating a feedback loop with theinsertion-extraction chain and an inverter locatedinside the companion FPGA. This feedback in-verter is only connected after waveform readout ofa triggered event and then disconnected once thesampling speed has been measured for that par-ticular triggered event. A so-called Ripple CarryOut (RCO) period may then be expressed as

Ttotal = 2 ∗ (Tlatency + Twaveform) (21)

where the factor of 2 comes from the FGPA feed-back inverter toggling the RCO period, Twaveform

is the SCA propagation time, and Tlatency is theadditional time accrued due to internal FPGArouting, circuit board routing, and routing to andfrom the SCA within the ASIC. To measure Ttotal

an FPGA-based Time-to-Digital Converter (TDC)is used [10]. Both phases of a 250 MHz clock areused by the TDC to obtain a least count of 2ns.Improved resolution is obtained by integratingthe RCO period for 2048 cycles, corresponding toan aggragate single-cycle least count of 0.977 ps.Tlatency is obtained by subtracting Twaveform fromTtotal, where Twaveform is determined from a fit toa fixed frequency sinusoidal signal. The samplingspeed is then

fSPD = (Twaveform/Rowlength)−1 (22)

where fSPD is the sampling speed and Rowlength

is the number of SCA cells in a row, which for theBLAB1 ASIC is 512 cells. As reported in Ref. [5],the sampling timebase is temperature dependent.This effect may be seen as the correlated portion ofFig. 19. By measuring the BLAB1 timebase, thesetimebase shifts can be monitored and corrected of-fline.

7.3. Pixel Level Noise

In order to achieve the desired timing perfor-mance, the Signal-to-Noise Ratio (SNR) is crucial.As the signal gain is limited (for aging and BWlimitations), it is important that reasonable noiselevels be obtained. The measured noise for a singlepixel, which is very representative of the ensembleaverage, is displayed in Fig. 21.

BLAB2: pix noiseEntries 10000

Mean −0.009308

RMS 1.387

/ ndf 2χ 262.5 / 12

Constant 24.9± 1945

Mean 0.01409± −0.02317

Sigma 0.011± 1.384

voltage (mV)−4 −2 0 2 4

0

200

400

600

800

1000

1200

1400

1600

1800

2000

2200 BLAB2: pix noiseEntries 10000

Mean −0.009308

RMS 1.387

/ ndf 2χ 262.5 / 12

Constant 24.9± 1945

Mean 0.01409± −0.02317

Sigma 0.011± 1.384

HISTO

Fig. 21. Measured noise for a single pixel.

7.4. Linearity

In addition to having low noise, it is also impor-tant that the linearity of the sample conversion beof high quality. In Fig. 22 is shown the basic re-sponse of the converted values versus input values(amplifier output is offset to about 1300mV).

9

800

1000

1200

1400

1600

1800

2000

2200

2400

2600

500 700 900 1100 1300 1500 1700

Sampled Voltage (mV)

AD

C c

ount

s

Fig. 22. Transfer response of the stored voltage values.

A linear fit to the main (usable) part of the curveis made and the residual is plotted in Fig. 23.

-10

-5

0

5

10

15

20

1000 1200 1400 1600 1800 2000 2200 2400 2600ADC counts

INL(

mV)

Fig. 23. Simple linear residual for the main part of thetransfer curve.

Because it is computationally more efficient, aLook Up Table is applied to the data that correctsthe residual non-linearity at the edges of the com-parator dynamic range.

7.5. Frequency Response

Another critical component of excellent timingprecision is the ability to couple in the high-frequency components of the signal of interest.In BLAB2 a number of configurations were triedto evaluate their relative coupling performance.The variation in frequency response is plotted inFig. 24.

-20

-15

-10

-5

0

5

10

100 250 400 550 700 850 1000frequency (MHz)

gain

(dB

)

N_MOS-ROW0P_MOS-ROW0N_MOS-ROW1P_MOS-ROW1N_MOS-ROW2P_MOS-ROW2N_MOS-ROW3P_MOS-ROW3

Fig. 24. Frequency response of various storage configura-tions in the BLAB2 ASIC. Positive gain is seen at lowerfrequencies due to the input TIA.

7.6. Analog Crosstalk

As a practical matter, the possible interferencefrom nearest neighbor channels, strongly observedin the LAB3 ASIC [2] can be important. A mea-surement of the observed signal level in Channel2 as a function of input frequency in Channel 1 isplotted in Fig. 25.

-25

-20

-15

-10

-5

0

5

10

0 200 400 600 800 1000 1200frequency (MHz)

gain

(dB

)

CH1CH2

Fig. 25. Observed crosstalk signal in channel 2 as a func-tion of RF sine frequency signal amplitude in channel 1.An modest though interesting resonance is seen at about350MHz.

10

7.7. Fast on-chip ADC

In order to speed up the digitization clock, oneoption is to use the PRO [7] technique ...

The ramp speed is increased in this case andthe sampling of the timing edge is produced via adelay chain with effective sampling speed given inFig. 17.

In this case the measured noise increases for aramp of 100ns?? as may be seen in Fig. 26

BLAB2−PRO: pix noise

Entries 1000

Mean −0.2111

RMS 2.442

/ ndf 2χ 46.38 / 2

Constant 28.6± 663.1

Mean 0.0631± 0.8977

Sigma 0.055± 1.912

voltage (mV)−10 −8 −6 −4 −2 0 2 4 6 8 100

100

200

300

400

500

600

BLAB2−PRO: pix noise

Entries 1000

Mean −0.2111

RMS 2.442

/ ndf 2χ 46.38 / 2

Constant 28.6± 663.1

Mean 0.0631± 0.8977

Sigma 0.055± 1.912

HISTO

Fig. 26. Measured pixel noise when the so-called “PRO”readout encoding is used, which increases over the off-chipencoder though runs almost an order of magnitude faster.

The raw linearity of this flash encoder is shownin Fig. 27, and the linear fit residual is presentedin Fig. 28.

Another issue discovered during the use of fastramping mode is that there is a net baseline shiftacross the array when performing multiple, fastsuccessive conversions.This effect is seen in Fig. 29.Operation with a slower ramp ... should help???

8. Expected Limitations

While the analog bandwidth of the BLAB1 isadequate for many RF recording applications, ahigher bandwidth device will be explored, basedupon the lessons learned from this first device. In

1000

1050

1100

1150

1200

1250

1300

1350

1400

1450

300 325 350 375 400 425 450ADC counts

volta

ge (m

V)

Fig. 27. Measured linearity of so-called “PRO” readout

encoding, where it is noted that due to offset issues only asmall portion of the encoding range could be used.

-6

-4

-2

0

2

4

6

300 325 350 375 400 425 450ADC counts

INL(

mV)

Fig. 28. Measured residual after linear fit to the “PRO”readout encoding, where again the dynamic range is limitedby operating parameters of the input sampler offset.

particular, the fanout structure and design of theanalog amplifier tree is being scrutinized and im-proved in simulation. It is hoped that an almostarbitrarily large storage depth can be accommo-dated up to 1GHz of analog bandwidth through acareful layout of the buffer amplifier cascade array.

8.1. Sampling Timebase Jitter

While the pedagogical illustrations above arehelpful in understanding what limits the time res-olution that can be obtained, there is an addi-tional contribution that is an artifact of the use of

11

370

380

390

400

410

420

430

440

450

460

470

0 100 200 300 400 500Pix Position

AD

C P

ED v

alue

(cou

nts)

Fig. 29. Baseline shift observed as a function of samplesdigitized across the array. Such a shift is not observed whenusing the external (FPGA-based) TDC.

the BLAB1 ASIC. Specifically, it contains no ded-icated Delay Lock Loop (DLL) circuitry, and thusthe sampling timebase is sensitive at the level ofabout 0.2%/◦C [5]. Even though an event-by-eventcorrection is performed, as described previously, itis quite probable that a residual correction errorcontributes to the time resolution. A simulation isperformed as shown in Fig. 30, where 1mV of noiseis added in quadrature with 1ps of sample aperturejitter on top of an overall event-by-event samplingtimebase jitter. This jitter is assumed to be uncor-related between the two ASICs.

Fig. 30. Time resolution with 1mV noise, 1ps of sample jit-ter, and as a function of event-by-event uncorrected time-base jitter.

In the limit that the known 1mV noise only con-tributes 2ps to the overall time resolution and thatthe sample aperture jitter is negligible, this effectis seen to be dominant. Quantitatively, this cor-responds to about a 10% error on correcting theevent-by-event sampling timebase. If true, this canbe improved through better timebase stabilizationin a next version of the ASIC [5], or through theuse of other devices as described next.

9. Summary

The IRS ASIC will represent a significant exten-sion of the capabilities of an IceRay detector andthis document provides those specifications.

10. Acknowledgements

The authors gratefully acknowledge the gener-ous support of ...

References

[1] P. Allison et al., “IceRay: An IceCube-centered Radio-Cherenkov GZK Neutrino Detector,” arXiv:0904.1309.

[2] G.S. Varner, L.L. Ruckman, J.W. Nam, R.J. Nichol,J. Cao, P.W. Gorham, M. Wilcox, ”The large analogbandwidth recorder and digitizer with ordered readout(LABRADOR) ASIC,” Nucl. Inst. Meth. A 583 447(2007).

[3] H. Landsman et al., Proceedings of ARENA 2008,arXiv:0811.2520.

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