DESIGN AND DEVELOPMENT OF HIGHLYACCURATE TEMPERATURE MEASUREMENT

INSTRUMENTATION FOR USE IN HOSTILE ENVIRONMENT

Item Type text; Thesis-Reproduction (electronic)

Authors Hanna, Ghassan Faraj, 1957-

Publisher The University of Arizona.

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Hanna, Ghassan Faraj

DESIGN AND DEVELOPMENT OF HIGHLY ACCURATE TEMPERATURE MEASUREMENT INSTRUMENTATION FOR USE IN HOSTILE ENVIRONMENT

The University of Arizona M.S. 1986

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DESIGN AND DEVELOPMENT OP HIGHLY

ACCURATE TEMPERATURE MEASUREMENT INSTRUMENTATION

POR USE IN HOSTILE ENVIRONMENT

by

Ghassan Paraj Hanna

A Thesis submitted to the Faculty of the

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING

In Partial Fulfillment of the Requirements For the Degree of

MASTER OF SCIENCE WITH A MAJOR IN ELECTRICAL ENGINEERING

In the Graduate college

THE UNIVERSITY OF ARIZONA

1 9 8 6

STATEMENT BY AUTHOR

This thesis has been submitted in partial fulfillment of re­quirements for an advanced degree at the University of Arizona and is deposited in the University Library to be made available to borrowers under rules of the Library.

Brief quotations from this thesis are allowable without special permission, provided that accurate acknowledgment of source is made. Requests for permission for extended quotation f;;om or reproduction of this manuscript in whole or in part may be granted by the head of the major department of the Dean of the Graduate College when in his or her judgment the proposed use of the material is in the interests of scholarship. In all other instances, however, permission must be obtained from the author.

SIGNED:

APPROVAL BY THESIS DIRECTOR

This thesis has been approved on the date shown below:

^2— JM*

^ JOHN PRINCE III Professor of Electrical Engineering

Date

To my Parents

with love.

iii

ACKNOWLEDGMENTS

I am very grateful to Dr. John Prince for his support,

guidance, and keen interest during times of trouble throughout

my stimulating years of graduate study.

I am also grateful to Mr. Herbert (Bo) Chesney for his

technical assistance and guidance throughout the work of this

thesis.

Finally, I would like to thank Mr. Craig Conkling for

creating the schematics used in this thesis, and my thanks will

also go to Ms. Kelly Judd for typing the manuscript.

iv

TABLE OP CONTENTS

page

LIST OF ILLUSTRATION viii

LIST OF TABLES X

ABSTRACT xi

1. INTRODUCTION 1

2. GENERAL DESIGN CONSIDERATIONS . 5

2.1.1 Data Acquisition System 5 2.1.2 Basic Data Distribution system 8 2.2 Temperature Data Acquisition System 11 2.2.1 Temperature Instrumentation Subststems 12 2.2.2 Temperature Data Acquisition Microcomputers 18

2.3 Data Acquisition System Architecture 19 2.4 Analog-to-Digital Converters 25 2.4.1 Successive-Approximation A/D Converters 25 2.4.2 Dual-Slope A.D Conversion 28 2.4.3 V/F Conversion: An Alternative A/D Method 31

2.5.1 Transducers 41 2.5.2 Thermocouple Background 41 2.6 Single-Ended vs. Differential Signal Paths 45 2.7 Thermocouple Instrumentation Card (An Alternative

Design 48 2.7.1 Commutating Auto-Zero (CAZ) Instrumentation

Amplifier 51 2.7.2 Over Voltage Protection 54 2.7.3 Types of Analog Switches 56 2.7.4 The IH6108 Multiplexer 57 2.7.5 Reference Channel 60 2.7.6 Voltage Regulators 62

3. THERMOCOUPLE INSTRUMENTATION CARD 64

3.0 Thermocouple Instrumentation Card's Design 68 3.1 IH5208 Analog Multiplexer ,... 68 3.2 Thermistor Channel Design 70 3.3 LM299 Voltage Reference 75 3.4 Oven Voltage protection Circuit 76 3.5 AD624 Instrumentation Amplifier 78 3.6 AD650 Voltage to Frequency Converter 79

.3.7 HFBR-1402 Fiber Optic Transmitter 85

v

TABLE OP CONTENTS—Continued

Page

3.8 HCPL-2730 Optocouplers 87 3.9 Test Cell 89

TESTING OF THE THERMOCOUPLE INSTRUMENTATION CARD 93

4.1 Equipment List 93 4.2 Multiplexer's Channel Selection/Addressing Capability. 96 4.3 Input Protection Clamp 97 4.4 5V Voltage Regulator 97 4.5 Operation of V/F Converter with Input Variations 97 4.5.1 Input-Output Correlation Measurements for the v/F

Converter 98 4.6 Offset Voltage and Channel Variations Testing 99 4.6.1 Channel Offset Measurement 100 4.6.2 Reference voltage Channel Measurement 100 4.6.3 Calculations 101 4.7 Precision Voltage Reference Operation 101 4.7.1 Power Supply Effects of vr?f 102 4.7.2 Temperature and V^n Variations Effects on Vref 103 4.7.2.1 Data for Room Temperature 104 4.7.2.2 Data for 55°C 104 4.7.2.3 Data for 75°C 105

4.8 Results of the Linearity Test for TIB 106 4.8.1 Data and Calculations 107 4.8.1.1 Addressing Channel Ul-Sl (Roan Temp.)..... 107 4.8.1.2 Addressing Channel U4-S1 (Room Temp.) 107 4.8.1.3 Addressing Ul-Sl (55°C) 108 4.8.1.4 Addressing U4-S1 (55°C) 108 4.8.1.5 Addressing Ul-Sl (75°C) 108 4.9.1.6 Addressing U4-S1 (75°C) 109 4.8.2 Calculations of Error and Non-linearity 109 4.8.2.1 Calculations for Ul-Sl tRoom Temp) 109 4.8.2.2 Calculations for U4-S1 (Room Temp) 110 4.8.2.3 Calculations for Ul-Sl (55°C) 110 4.8.2.4 Calculations for U4-S1 (55°C) Ill 4.8.2.5 Calculations for U4-S1 (75°C) Ill 4.8.2.6 Calculations for Ul-Sl (75°C) 112

4.9 Test Results of CMRR, DMR and PSR 114 4.9.1 Common Mode Rejection Testing 114 4.9.2 Data and Calculations of CMRR 114 4.9.2.1 Addressing Channel Ul-Sl 115 4.9.2.2 Addressing Channel U4-S1 115 4.9.3 Differential Mode Rejection Testing 116 4.9.3.1 Data and Calculations 116 4.9.3.2 Addressing Channel Ul-Sl 117 4.9.3.3 Addressing Channel U4-S1 117

vii

TABLE OF CONTENTS—Continued

Page

4.9.4 Power Supply Rejection Testing 118 4.9.4.1 AC Signal Source Connected to (-12V) PS Line... 118 4.9.4.2 AC Signal Source Connected to (+12V) PS Line... 118

4.10 Power Supply Requirement and Variation Testing 121 4.10.1 Addressing Channel Ul-Sl 121 4.10.2 Addressing Channel U4-S1 122 4.10.3 Power Supply Requirement 123

4.11 Fiber Optics Testing 123 4.12 Protection Circuit Testing 123 4.13 Conclusion 125 4.13.1 Reducible and Nonreducible Errors 126

LIST OP ILLUSTRATIONS

Figure Page

1. Data Acquisition System 7

2. Data Distribution system 10

3. Temperature instrumentation Subsystems 13

4. Temperature Instrumentation/Remote Isothermal Junction Module 14

5. Temperature Sense Cards 16

6. Frequency Counter Card 17

7. Typical Data Acquisition System 20

8. DAS System for Simultaneous sampling of All Channels.... 21

9. High Accuracy, Multi-Converter DAS System 23

10. Block Diagram of the TIB 24

11. Successive-Approximation Converter 26

12. A) Dual Slope A/D ConverterConversion 30 B) Its Integrator Output Waveform 30

13. The Basic Charge Balancing V/F Converter 32

14. Nonlinearities of V/F, Dual Slope and Successive Approximation 36

15. Differential Data Paths 46

16. Thermocouple Instrumentatin Card - version B 49

17. Thermocouple Instrumentation Card 65

18. Thermistor Wheatstone Bridge Circuit *«. 71

19. AD650 Components Selection Graphs 80

20. Connections for +5V Bipolar V/F 82

viii

LIST OF ILLUSTRATIONS-1—Continued

Figure Page

21. Test Cell 90

22. Thermocouple instrumentation Card - Version 1 94

LIST OF TABLES

Table Page

1. Typical Converter Applications 29

2. Comparison of A/D Converter Type 35

3. IH6108 Multiplexer Decode Truth Table 58

x

ABSTRACT

A data acquisition system is defined to include all the

components needed to generate the electrical analogs of various

physical variables, transmit these signals to a central location

and digitize the information for entry into a digital computer.

The circuit designed in this thesis uses thermocouples to

measure a temperature of 25°C - 1250°C, with an error of less

than 0.242°C for electronics ambient temperature of 25°C - 55°C,

and 0.180°C for an ambient temperature of 75°C.

The design had the use of overvoltage protection circuit

that can .withstand up to 277 Vac spikes, and was capable to

produce a CMRR and DMR for a 60 Hz noise of 161.90 dB and

-49.03 dB respectively.

xi

CHAPTER 1

INTRODUCTION

The science of measurement has supported technology since its

beginning, and a technology-oriented society has in turn imposed a

large superstructure on the science of measurement. Measurement is an

inexact science requiring the use of reference standards, which are

involved either directly or indirectly in all measurements, more di­

rectly as the requirement for accuracy increases. For example, highly

accurate measurements are generally obtained by the comparison method,

such as the voltage measurement potentiometer employing a-standard cell

that is traceable to the National Bureau of Standards. More typical,

however, is the periodic comparison and correction of a sensor measure­

ment against a transfer standard that embodies some calibration proce­

dure. Even gross measurements, such as the use of sensors to detect

high or low limits in a process, require an initial comparison and

calibration.

The data acquisition and conversion systems interface between the

real world of physical parameters, which are analog, and the artificial

world of digital computation and control. With current emphasis on

digital systems, the interfacing function has become an important one;

digital systems are used widely because complex circuits are low cost,

accurate, and relatively simple to implement. In addition, there is

rapid growth in use of minicomputers and microcomputers to perform

1

2

difficult digital control and measurement functions.

Computerized feedback control systems are used by many different

industries today in order to achieve greater productivity in our modern

industrial society. Industries which presently employ such automatic

systems include steel making, food processing, paper production, oil

refining, chemical manufacturing, textile production, oil refining,

chemical manufacturing, textile production and cement manufacturing.

The devices which perform the interfacing function between analog

and digital worlds are analog-to-digital (A/to) and digital-to-analog

(D/A) converter, which together are known as data converters. Some of

the specific applications in which data converters are used include

data telemetry systems, pulse code modulated communictions, automatic

test systems, computer display systems, video signal processing sys­

tems, data logging systems, and sampled-data control systems. In

addition, every laboratory digital multimeter or digital panel meter

contains an A/D converter.

Besides A/D and D/A converters, data acquisition and distribution

systems employ different kinds of circuits, which are explained in

detail in Chapter 2.

This thesis is basically about data acquisition systems; under­

standing them, choosing them, and applying specifically the voltage-to

frequency converter as part of an analog circuit that measures the

temperature of an oven that operates between 0 - 1250°C. Chapter 2

discusses and gives the bulk of the theoretical background needed to

understand the reasons behind our choices of the particular design

3

architecture, kind of sensor, the type of A/D used, and many other

devices used in the design. Extensive comparison was made between two

popular A/D conversion schemes; namely, the successive approximation

and dual slope methods with the voltage-to-freguency conversion scheme

used in our circuit.

The circuit that was designed (temperature instrumentation card)

is a part of a big computerized system that makes the electronics

needed to process temperature measurements. This system consists of

the counter card, the interface card, and the temperature instrumen­

tation card as its front end.

The temperature electronics, are in turn, part of the requirements

needed to build the 8 meter mirror fabrication system of Steward Obser­

vatory. This fabrication facility will be used to produce 3.5m and 8m

mirrors for the corresponding telescopes. The temperature instrumen­

tation card will be used in both furnaces, with the 3.5m pven requiring

54 cards, and the 8m oven 108 cards.

Chapter 2 of this thesis will also discuss an alternative design

to the one that was finally adopted for the fabrication facility.

The alternative design differs from the final one in architecture

and preliminary devices, but uses the same voltage-to-frequency conver­

sion method to process the analog signal and convert it into digital

pulses. Since V/F converter changes the analog signal into a train of

pulses, it is only necessary to convert the pulse train into a parallel

digital code word for computer processing. This is done by counting the

pulses for a fixed period of time. The counter card (not discussed here)

which contains the counter and all the necessary digital circuitry will

4

be responsible for the aforementioned conversion.

Chapter 3 of this thesis describes the design of the final ver­

sion of the circuit in detail. The reader is strongly advised to refer

to the specifications sheets of the corresponding devices implemented

in the circuit for a complete understanding of the design of each sub-

circuit of the temperature instrumentation card. These specs sheets

are referred to in the References section of this thesis.

In the design of our circuit, special considerations were given to

the power supplies and grounding problems. Each supply voltage to a

particular chip has a low pass filter connected to it, which consists

of a bypass capacitor on the supply-voltage pins and a small valued

resistor in the supply line to provide a measure of decoupling between

the various circuits of the system.

Separate digital and analog grounds were provided on the circuit.

The purpose of the two separate grounds is to allow isolation between

the high precision analog signals and the digital section of the

circuitry. As much as several hunderd millivolts of noise can be

tolerated on the digital ground without affecting the accuracy of the

V/F converter. Such ground noise is inevitable when switching the

large currents associated with the frequency output signal.

A special prototype of the circuit was used for testing purposes. '

This circuit uses two thermocouple channels, instead of the five

required for the final design. Chapter 4 covers the testing results

along with the procedures used in the testing and a final section .

comprising the conclusion.

CHAPTER 2

GENERAL DESIGN CONSIDERATIONS

A good engineering approach is the one that attempts to invesigate

the different methods available for solving a particular design problem,

the advantages available with each method, and finally its conformity

with other system's and budget restrictions. This chapter will discuss

the different methods available for the design of the temperature

instrumentation card.

2.1.1 Data Acquisition System

A general and basic data acquisition system will contain the

following:

1. Transducers

2. Amplifiers

3. Filters

4. Nonlinear Analog Functions

5. Analog Multiplexers

6. Sample-Holds

The interconnection of these components is shown in the diagram of

the data acquisition portion of a computerized feedback control system

in Figure 1.

The input to the system is a physical parameter such as tempera­

ture, pressure, flow, acceleration, and position, which are analog

5

6

quantities. The parameter is first converted into an electrical signal

by means of a transducer; once in electrical form, all further proces­

sing is done by electronic circuits.

Next, an amplifier boosts the amplitude of the transducer output

signal to a useful level for further processing. Transducer outputs

may be microvolt or millivolt level signals which are then amplified to

1 to 10 volt levels. Furthermore, the transducer output may be a high

impedance signal, a differential signal with common mode noise, a

current output, a signal superimposed on a high voltage, or a combina­

tion of these. The amplifier, in order to convert such signals into a

high level voltage, may be one of several specialized types.

The amplifier is frequently followed by a low pass active filter

which reduces high frequency signal components, unwanted electrical

interference noise, or electronic noise from the signal. The amplifier

is sometimes also followed by a special nonlinear analog function

circuit which performs a nonlinear operation on the high level signal.

Such operations include squaring, multiplication, division, RMS conver­

sion, log conversion, or linearization.

The processed analog signal next goes to an analog multiplexer

which sequentially switches between a number of different analog input

channels. Each input is in turn connected to the output of the multi­

plexer for a specified period of time by the multiplexer switch.

During this connection time, a sample-hold circuit acquires*' the signal

voltage and then holds its value while an analog-to-digital converter

converts the value into digital form. The resultant digital word goes

to a computer data line or to the input of a digital circuit. Thus the

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analog multiplexer, together with the sample-hold, time shares the A/t)

converter with a number of analog input channels. The timing and

control of the complete data acquisition system is done by a digital

circuit called a programmer-sequencer, which in turn is under control

of the computer. In some cases the computer itself may control the

entire data acquisition system.

While this is perhaps the most commonly used data acquisition

system configuration, there are alternative ones. Instead of multi­

plexing high-level signals, low-level multiplexing is sometimes used

with the amplifier following the multiplexer (as is the case of our

design). In such cases just one amplifier is required, but its gain

may have to be changed from one channel to the next during multi­

plexing. Another method is to amplify and convert the signal into

digital form at the transducer location and send the digital infor­

mation in serial form to the computer. Here, the digital data must be

converted to parallel form and then multiplexed onto the computer data

bus. These alternatives will be discussed and compared, later on, with

the approach our design took.

2.1.2 Basic Data Distribution System

The data distribution portion of a feedback control system, illus­

trated in Figure 2, is the reverse of the data acquisition system. The

computer, based on the inputs of the data acquisition system, must

close the loop on a process and control it by means of output control

functions. These control outputs are in digital form and must there­

fore be converted into analog form in order to drive the process. The

9

conclusion is accomplished by a series of digital-to-analog converters

as shown. Each D/A converter is coupled to the computer data bus by

means of a register which stores the digital word until the next

update. The registers are activated sequentially by a decoder and

control circuit which is under computer control.

The D/A converter outputs then drive actuators which directly

control the various process parameters such as temperature, pressure

and flow. Thus the loop is closed on the process and the result is a

complete automatic process control system under computer control.

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2.2 Temperature Data Acquisition System

The system that was designed is that of a temperature data acqui­

sition with the following requirements and specifications:

1) The system to be designed needs to be able to measure a tem­

perature that will range from 25°C to 1250°C, with an error

of less than a half a degree centigrade, when the electronics

ambient temperature is between 25°C and 50°C. The error

should also not exceed 1°C for an ambient temperature of

85°C.

2) The potential exists for faults of 277 VAC. The instrumen­

tation shall be capable of withstanding such overvoltages

without sustaining any damage.

3) "Absolute temperature measurement sensors have to be included V * '

to measure the temperature of the elctronic's enclosures, the

power panel enclosures, and the isothermal junction block.

The specifications for the measurement electronics are:

a) The accuracy required shall be + 1°C.

b) The maximum ambient temperature will be no more than

100°C.

4) A noisy environment exists. The circuit to be designed

should have a high common mode rejection ratio.

5) The output of the temperature instrumentation subsystem is to

be -connected to a counter card that has a maximum operating

frequency of 40 MHz.

6) The circuit to be designed has to have a high degree of

reliability and maintainability.

12

7) Cost should be a factor but not a decisive one.

The above requirements and specifications were drawn from the

functional description of all the subsystems that make the temperature

instrumentation of the 8-meter furnace, in which our subsystem, the

thermocouple instrumentation, is but the first in a series that end

with the microcomputer interface card.

2.2.1 Temperature Instrumentation Subsystems

The temperature instrumentation subsystems (Figure 3) collect and

process all of the temperature data for the oven control system. Tem­

perature data includes not only the temperature measurements from

inside of the furnace, but also temperature measurements for the

various enclosures which contain the oven electronics.

Temperature readings from inside the furnace are taken using

grounded and shielded thermocouples. 270 thermocouples will be used to

measure the temperature at each of the 270 heater panels and up to an

additional 270 thermocouples will be used to monitor the temperature of

the mold materials, glass, and other desired locations inside the fur­

nace. The thermocouple.outputs are connected, using shielded thermo­

couple extension wire, to remote temperature sense modules placed at

various locations on the outside surface of the oven.

Each remote temperature sense module (Figure 4) will be capable of

handling up to 10 thermocouples outputs. This results in a total of 54

temperature sense modules. Each module shall also contain two absolute

temperature measurement modules for-measuring the isothermal junction

block temperature. Temperature sense cards (Figure 5), located in the

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remote temperature sense modules, condition and amplify the outputs of

the thermocouples and absolute temperature modules. The amplified sig­

nals are then multiplexed into a voltage to frequency converter. The

output of the voltage to frequency converter is sent over an optical

fiber to a temperature conversion module. The temperature sense cards

have the necessary offset and voltage references for autocalibration.

The temperature conversion module contains frequency counter cards

(Figure 6) which convert the frequency data from the temperature sense

cards into digital counts. Each frequency counter card is capable of

receiving frequency data from four temperature sense cards. The cards

also supply power to the same four temperature sense cards, along with

multiplexer channel address. The temperature data acquisition micro­

computers, accept data .from the temperature conversion module over a

parallel I/O bus. There will be one temperature conversion module for

each temperature data acquisition microcomputer. The temperature con­

version modules also shall each contain two temperature sense cards for

obtaining data from up to 12 absolute temperature modules located in

the electronics enclosures. Each temperature conversion module shall

be capable of accepting data from and supplying it to 18 remote tem­

perature sense modules.

2.2.2 Temperature Data Acquisition Microcomputers

These modules collect and process the temperature data for the

system. Their tasks are:

1) Control and read the temperature conversion modules.

2) Do required processing of raw data, i.e. thermocouple ice

point compensation and linearization.

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3) Perform autocalibration of temperature sense module.

4) Detect any defective temperature sense channels or devices,

5) Detect out of range temperatures in system enclosures and

trigger alarms in the event of such occurences.

6) Perform voting function on controller module communications

and trigger alarms when possible controller module failure

occurs.

7) Provide a logical interface between temperature measurement

subsystems and the controller modules.

19

2.3 Data Acquisition System Architecture

There are several data acquisition system architectures to be

considered by the designer who must choose hardware for a given appli

cation. At present the most widely used DAS configuration is that

shown in Figure 7. It handles a moderate number of analog channels

feeding into a common multiplexer, programmable gain amplifier (if

required), track/hold amplifier and A-D converter.

A more specialized and expensive variation is to place a track/

hold in each channel as shown in Figure 8. Switching all channels to

Hold simultaneously produces a "snapshot" view which preserves the

phase relation of signals in all channels. This information is impor­

tant in seismic studies and vibration analysis.

The DAS system of Figure 9 offers many advantages, but is not yet

practical except for slowly changing channel data. Low frequency sig­

nals allow dedication of a slow but accurate integrating type A-D

converter for each channel. The channel filter often included to

reduce aliasing errors and noise are not necessary, since aliasing is

not a problem with low bandwidth signals. The integrating converter

suppresses wideband noise by averaging it about the instantaneous

signal ievel. Also, the converter's integration period may be chosen

to provide almost complete rejection of a specific interference fre­

quency such as 60 Hz. Digital outputs from the converters are then

digitally multiplexed.

The system shown in Figure 9 has an inherent advantage over the

other two systems, having eliminated both the track/hold and the analog

multiplexer with their many error contributions. The disadvantage, of

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course/ is cost. In addition to cost, this system shares with the

other two the disadvantage of having to use an op amp to boost the

output of the transducer (in this case, a thermocouple with an output

of 30 uV/°C or 50 mV at 1250°C).

The approach that was taken to implement the specifications of the

thermocouple instrumentation card is shown in Figure 10.

This system consist of a transducer (thermocouple) feeding

directly into a differential multiplexer. The low level signal is then

amplified using an instrumentation amplifier that feeds into a voltage-

to-frequency converter which finally outputs a train of digital pulses

in a serial form. Following the V/F is a NAND gate controlled by a

precision timer which gates the pulses through to a counter. The

counter counts the pulses until the timer turns them off at the gate

and then holds the output as a parallel digital word. As with other

A/D converters, a trigger pulse initiates a conversion by triggering

the timer and resetting the counter to zero. This architecture has

several advantages over the other systems described earlier, since it

eliminates the need for op amps, filters and track/hold amplifiers

which combined, produce many errors. The need for a digital section

with the V/F converter does not change considerably the low cost of

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2.4 Analog-to-Digital Converters

Analog-to-digital converters, also called ADC's or encoders,

employ a variety of different circuit techniques to implement the

conversion function. Of the various techniques available, the choice

depends on the resolution and speed required.

For the purpose of this thesis, we will concentrate on two popular

A/D conversion techniques, and will try to compare them to the V/P

conversion method that was adopted in the design of the thermocouple

instrumentation card. These techniques are the successive-approxima-

tion and dual slope conversion methods. Three relatively inexpensive

(under 100 dollars) methods - the successive approximation, dual slope

and V/F conversion schemes - can deliver equal accuracy, but each is

used best.in a different application (Table - 1).

2.4.1 Successive-Approximation A/D Converters

By far, the most popular A/D conversion technique in general use

for moderate to high speed applications is the successive-approximation

type A/D (Figure 11). This method falls into a class of techniques

known as feedback type A/D converters, to which the counter and the

tracking A/D types also belong. In all cases a D/A converter is in the

feedback loop of a digital control circuit which changes its output

until it equals the analog input. In the case of the successive-

approximation converter, the DAC is controlled in an optimum manner to

complete a conversion in just n steps, where n is the resolution of the

converter in bits. In other words, the successive-approximation

compares the output of an internal D/A converter against the input

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signal, one bit at a time. Therefore, n fixed time periods are needed

to deliver an output n bits long, but the total time needed is indepen­

dent of input-voltage value.

The first step after the start pulse in a successive-approximation

conversion cycle is turning on the MSB (Most Significant Bit), which

sets the D/A converter's output at half scale. This analog signal is

then fed back to the comparator. The MSB is left on in the D/A conver­

ter's ouput if smaller than the analog input, and turned off if the

output is larger.

Next, the second bit is turned on, and the quarter-scale value

added to the D/A converter output and the comparator again does its

job. This process continues until the LSB has been tested and the

final comparison made. When the process is complete, the converter

signals this by changing the state of its end-of-conversion (status)

output. The final digital output can then be read from the output of

the successive-approximation register of the converter.

Successive-approximation converters can achieve conversion speeds

of 100 ns/bit in medium-priced (250-300 dollars) 8 and 10-bit units.

Converters with 12-bit outputs are typically available with conversion

times ranging from 2 to 50 us.

28

2.4.2 Dual-Slope A/D Conversion

The dual-slope technique falls under another class of A/D conver­

ters known as integrating type which operates by an indirect conversion

method. The unknown input voltage is converted into a time period

which is then measured by a clock and a counter. A number of varia­

tions exist on the basic principle such as single-slope, dual-slope,

and triple-slope methods. In addition there is another technique -

completely different - which is known as the charge-balancing or quan­

tized feedback method which the V/F converter falls under.

The dual-slope converter uses a simple counter to indirectly mea­

sure the input signal after an operational integrator converts a volt­

age into a time period (Figure 12a). This scheme is the second most

commonly employed method and is used, almost exclusively, in such in­

struments as digital multimeters and panel meters.

The conversion cycle begins when the analog-input signal is

switched to the input of the operational integrater. The voltage is

integrated (Fig. 12b) for a fixed time period determined by the clock

frequency and the counter size. At the end of the period, the integra­

tor input is switched to an internal reference whose polarity is oppo­

site that of the original analog input. The reference is then inte­

grated until the-output reaches zero and triggers the comparator.

During the second integration, the clock is gated into a counter

chain that accumulates the count until the comparator inhibits the

clock. When the clock signal stops, the conversion is complete.

29

Table 1 Typical Converter Applications

A/D Converter type Common Applications

Successive Approximation

High speed data-acquisition systems Pulse-code-modulation systems Waveform sampling and digitizing Automatic test systems Digital process control systems

Dual Slope

Digital multimeters Digital panel meters Laboratory measurements Slow-speed data acquisition systems Monitoring systems Ratiometric measurements Measurements in high-noise environments

Voltage to Frequency

Digital multimeters Digital panel meters Remote data Transmission Totalizing measurements Measurements in high noise environments High voltage isolation measurements Ratiometric measurements

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Dual-slope conversion has several important features. First, con­

version accuracy is independent of the stability of the clock and inte

grating capacitor as long as they are constant during the conversion

period. Accuracy depends only on the reference accuracy and the inte

grator circuit linearity. Second, the noise rejection of the converter

can be infinite if ̂ is set to equal the period of the noise. To

reject 60 Hz power noise, therefore, requires that T]_ be 16.667 msec.

2.4.3 V/F Conversion: An Alternative A/D Method

Seldom used until a few years ago, V/F conversion techniques are

rapidly becoming popular as an alternative to successive-approximation

or dual-slope techniques. There are several ways to build a V/F

conversion circuit, but the charge-balancing method (Figure 13) is the

most popular.

If Vin is positive, the integrator output ramps down until its

output voltage V^ crosses the comparator's threshold (ground, in this

case) and causes the comparator to change state. The transition, in

turn, triggers a precision timing circuit that delivers a constant-width

pulse. The pulse gets fed to two places: a buffer circuit that then

feeds the output; and the integrator, where the pulse causes the inte­

grator output to rapidly ramp up.

The timing circuit is, in effect, a precision one-shot multivi­

brator that is stable with both time and temperature. The reference

current, Iref, must also be stable, and a precision regulator with a

voltage reference source is included for that purpose.

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Since the reference current is pulled from the integrator summing

junction for a fixed amount of time, and at intervals determined by the

input voltage, the positive-input current feeding the integrator bal­

ances the current pulses being pulled out. The integrator can be made

extremely linear and, when combined with the charge-balancing feedback

loop, can achieve nonlinearities as low as 0.005%.

To form an A/D converter with the V/F technique, the output of the

V/F circuit must feed a counter that is gated for the desired maximum

count (for a converter with a 100-KHz output, a 14-stage binary counter

can be used, as is the case in our design).

It is useful to discuss the characteristics of V/F converters in

terms" of well known A/D converter specifications (Table 2). For an A/D

converter,' resolution is expressed in bits and is determined by the

number of parts into which the full-scale range is divided. In the V/F

form of an A/D converter, the resolution is determined by the full-

scale frequency, the time base and the capacity of the counter used.

If a 10-KHz V/F converter is used with a time base of 1 second and four

decade counters,, its resolution is one part in 10,000, or four

binary-coded decimal (BCD) digits. A 100 KHz converter with a one

second time base gives greater than 16-bit resolution (1 part in 65,536).

Successive approximation or dual-slope converters with straight binary

coding would have to deliver a digital output of at least 13 bits to

come close (13 bits = 1 part in 8192). A V/F based A/D converter can

also deliver straight binary. To make a 12-bit unit, a three 4-bit

binary counter can be used with a time base equal to 0.4096 seconds.

In dual-slope converters, resolution is also a function of inte­

gration time, clock frequency and counter capacity. Successive-approx­

imation units use weighted current sources, and the number of sources

determines the resolution. The higher the number of bits, the harder

it becomes to maintain the linearity of the weighted sources.

Linearity is the acid test of any A/D converter specifications

since resolution can be unusable if linearity error doesn't hold to

less than +0.5 LSB (1 LSB at the worst). At a fixed temperature,

linearity is the only error that remains after offset and gain errors

have been adjusted out.

The linearity error of a converter is the maximum deviation of the

output values from a straight line drawn from zero to the maximum out­

put. For -a 12-bit a/d converters a "good-quality" successive approxi­

mation unit has a nonlinearity of about +0.012%, a dual-slope

unitabout +0.05 to 4j0.01% and a V/f converter about +0.01 to ̂ 0.005%.

The nonlinearity characteristic of successive approximation con­

verters differ fundamentally from that of the dual-slope or V/f. Typi­

cal nonlinearity curves are shown (slightly exaggerated) in Figure 14.

Both the V/f and dual-slope converter linearity characteristics

tend to have a bow that is caused by the operational integrators used

in the converters. By contrast, the successive-approximation conver­

ter's linearity is determined by the major-carry transitions of the

weighted current sources. These points are located chiefly, where 1/2

and 1/4 scale current values are switched in or out during the conver­

sion process. As shown in the graph of Figure 14, a jump in the curve

35

Table 2. Comparison of A/D Converter Type

Specifications Successive-Approximation Dual-Slope

Voltage to Frequency

Resolution 12 bits 12 bits 12 bits

Missing Codes None by careful design

none, inherent none, inherent

Nonlinearity j+0.012% max jjd.05 to 0.01% +0.005% max

Differential Nonlinearity

+1/2 LSB approx. 0 approx. 0

Temperature Coefficient

10 to 50 ppm/°C 10 to 50 ppm/°C 10 to 50 ppm/°C

Conversion Time 2 to 50 us 5 to 77 ms 0.041 to 0.41s

Noise Rejection, 60Hz

None 40 to 60 dB 33.8dB *

* For 0.41S conversion time

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signifies when a major-carry current value is slightly off its correct

value. A very linear converter restricts these jumps to very small

amounts (+0.012% for a 12-bit converter).

The V/f converter takes the longest to do a complete conversion.

The time base used in Figure 13 is 1 second for a single conversion -

rather slow for most applications. Dual slope converters are faster,

with conversion times ranging from 5ms to 100ms.

Successive approximation converters are the fastest of the three,

with conversion times as short as 2 us for 12 bits. Most successive

approximation converters have conversion time between 3.5 and 50 us.

Since the time for conversion can be made equal to the inverse of

the line-voltage frequency, the dual slope converter can be designed to

reject much of the noise caused by the power line. The integrating

technique used by dual slope and V/f converters gives them the ability

to reject high levels of input noise. For these two integrating conver­

ters, the longer the signal is integrated, the better the noise atten­

uation. When the integration period equals a multiple of the inverse of

the line frequency (for dual slope units), the noise rejection becomes

infinite at integral values TFn, where T is the integration period and

Fn is the noise frequency. V/F converters don't, in general, use a

period that is a multiple of any periodic noise, and so the asymptote of

the noise-rejection curve is used to determine the rejection at a given

TFn.

38

The V/P- converter's noise rejection asymptote rises by 20 dB per

decade, and , for a 60 Hz power line and a 0.41 s conversion time, the

rejection can be computed at 33.8 dB. Dual slope converters have rejec­

tion ratios as high as 60dB when conversion is synchronized with the

noise frequency.

Successive approximation converters have no noise-rejection capa­

bility whatsoever. Input noise at any time during the conversion pro­

cess can cause significant conversion errors. (Noise feeds directly to

the comparator and can change the decision point). The only way to

minimize noise is to add an input noise filter to the converter.

Operation at different temperatures can tremendously alter conver­

ter performance, no matter which converter type is selected. These

changes affect offset and gain, two important converter parameters.

Even though offset and gain are adjusted during calibration, they can

change significantly with temperature.

Offset is a function of current-source leakage, comparator bias

current and comparator input voltage offset. Gain (sometimes called

scale factor) is a function of the voltage reference, resistor tracking

and semiconductor -junction matching - and is usually the most difficult

parameter to control. Absolute accuracy is affected by offset and gain

changes, so if these change during operation, output errors will occur.

And, if the linearity degrades, a converter can actually skip output

codes (become nonmonotonic). (An a/d converter is said to have no

missing codes when, as the analog input of the converter increases from

zero to full scale or vice-versa, the digital output passes through all

of its possible states). Both the dual slope and V/f converters are

39

inherently monotonic because of their integration techniques and the use

of counting circuits to deliver the digital output.

The successive-approximation a/d converter, on the other hand, is

more prone to missing codes. The code jumps occur when the analog

transitions between adjacent output codes become greater than 1 LSB.

Because the jumps can be greater than 1 LSB, another spec, differential

nonlinearity, becomes very important. Differential nonlinearity is

defined as the maximum deviation of the size of any adjacent code tran­

sitions from their ideal value of 1 LSB.

A specified differential nonlinearity of 4H3.5 LSB tells that the

magnitude of every code transition is 1 LSB LSB, maximum. The

differential nonlinearity can reach a maximum of +_ 1 LSB before conver­

ter performance is in doubt.

Choosing the right converter for specific application is no easy

matter. For example, digital multimeters typically use a dual-slope

converter since high speed isn't necessary, but high noise rejection is.

However, in other applications, such as in fast-throughput data acqui­

sition, the successive-approximation converter must be used.

Dual slope converters are widely used in applications requiring

human interface in measurement and control.

A common application for the V/f converter is to transmit tempera­

ture or pressure data from an industrial process. The only restriction

on the analog data to be transmitted is that it does not change too

rapidly for the V/f converter to follow.

40

While the V/f module is a relatively slow way to convert a/d, the

cost is low and accuracy can be high. Other advantages of V/f converter

that added to the reasons behind our choice of the V/f technique as the

a/d converter that should be used to measure temperature are:

1) Excellent noise rejection at the input by virtue of its 0.41

second signal averaging time.

2) Capability to interface directly between analog and digital

circuits.

3) High common mode voltage isolation.

4) Good linearity.

5) Excellent temperature stability.

41

2.5.1 Transducers

The first item in the signal path of a DAS is the transducer. This

device usually transforms energy from one form to another, producing an

electrical analog of the physical variables to be monitored or measured.

Transducers are based on a variety of physical principles but most

produce a voltage as an output. Some yield an intermediate variable

such as resistance or capacitance, which is transformed to voltage by an

applied electrical excitation (carrier frequency, dc voltage, current

source).

Often, several types of transducers are available to sense a given

quantity. In the case of our design, thermocouple (type N) was chosen

to measure the physical variable: temperature.

2.5.2 Thermocouple Background

Stated simply, when two wires of dissimiliar metals are brought

into contact at equal temperatures, a voltage potential exists. The

problem becomes that of measuring this voltage potential and relating it

to temperature which is the parameter of interest in the first place.

Two factors exist which make this difficult. The first is that the

thermocouple voltage cannot be measured directly because the voltmeter

leads themselves create new thermocouple junctions. The second is that

the variation in thermocouple temperature with respect to thermocouple

voltage is not linear. These two factors and their solutions are

discussed below.

To solve the first problem, an isothermal junction was used to act

as an electrical isolator but a good heat conductor. This junction

42

serves to hold the junctions created by the thermocouple leads and the

measuring device (here, a computer with the instrumentation card as its

front end) at the same temperature. What is left to be done is to

measure the temperature of the isothermal junction directly and use

that information to compute the unknown temperature from:

v = X (Tji - Tref)

where,

v = computer voltage reading X = Seebeck coefficient for an N-type thermocouple

Tji = the unknown temperature to be measured Tref = the isothermal (also called reference) junction's temp.

A thermistor, whose resistance ̂ is a function of temperature,

provides us with a way to measure the absolute temperature of the iso­

thermal junction. This will be accomplished via software compensation

which relies upon the software of a computer to compensate for the

effect of the isothermal junction. The isothermal terminal block

temperature sensor can be any device which has a characteristic propor­

tional to absolute temperature: an RTD, a thermistor, or an integrated

circuit sensor.

It seems logical to ask: If we already have a device that will

measure absolute temperature, (like an RTD or thermistor) why do we even

bother with a thermocouple that requires isothermal junction compensa­

tion? The single most important answer to this question is that the

thermistor, the RTD, and the integrated circuit transducer are only

useful over a certain temperature range. Thermocouples, on the other

hand, can be used over a range of temperatures, and optimized for var­

ious atmospheres. In our case, only thermocouples can read temperature

43

ranges from 0 to 1250°C. They are much more rugged than thermistors, as

evidenced by the fact that thermocouples are often welded to a metal

part or clamped under a screw. They can be manufactured on the spot,

either by soldering or welding. In £hort, thermocouples are the most

versatile temperature transducer available and since the measurement

system performs the entire task of isothermal compensation and software

voltage-to-temperature conversion, using a thermocouple becomes as easy

as connecting a pair of wires.

Thermocouple measurement becomes especially convenient when we are

required to monitor a large number of data points. This is accomplished

by using the isothermal reference junction for more than one thermo­

couple element tin our case for 10 thermocouples).

To compensate for the nonlinearity of the thermocouple temperature

with respect to thermocouple voltage, a computer software compensation

can be used. By consulting the National Bureau of Standards Thermo­

couple Tables, and approximating the table values using a power series

polynomial, the thermocouple voltages produced can be converted into

temperature easily via the system software, A better method that was

used in our design, which is faster and consumes less amount of memory,

is the usage of two reference channels, the zero (or. offset) reference

channel for 0°C temperature reading, and the voltage reference (50 mv)

channel. The output voltage of the Nicrosil versus Nisil (type N)

thermocouple that was used in our design is around 50 mV at 1250°C. The

computer will read the temperature by referring to the curve drawn

between these two reference points.

Any deviation (nonlinearity) of the temperature reading from the

line drawn between these two points, will be considered an error and

accounted for by the computer software.

45

2.6 Single-Ended vs. Differential Signal Paths

After the transducer has been chosen, the question that will arise

will be: Should the signal path be single-ended or differential? The

answer to this question is as follows: consider the thermocouple output.

A high level signal (100 mV to 10 V) is easier to handle than low level.

Is a common mode signal present? If not, is it likely to be acquired as

"pickup" during transmission? This is likely if cable is routed near

florescent lights, motor or other electrical machinery. If common mode

voltage is not expected, then an economical single-ended connection is

possible, with a single wire per channel and a common return.

Low level signals (less than 100 mV, as is our case) require

special treatment. The presence of common mode voltage, whether high or

low, requires a differential signal path. The problem with the single-

ended signal approach of lA*s (Instrumentation Amplifier) connection

(i.e. no differential input) is that ground currents between the signal

source and amplifier will cause a small voltage drop that is in series

with the signal source. This ground loop is then amplified by the

gain of the amplifier. If an IA is connected as a differential signal

input, this ground loop will appear as only a common-mode signal and,

therefore, be rejected.

Now, for the case in which the transducer output is a low level

voltage, the choice is whether to transmit it as is, or to boost the

level by adding an amplifier. The amplifier will provide .low source

impedance as well as gain; two valuable forms of signal conditioning.

However, providing power to a remote amplifier can be difficult. Even

if a supply is available at the remote site, the voltage between two

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widely separated commons presents a problem. If the sum of the signal

plus common mode voltage does not exceed the input range of either the

multiplexer or buffer amplifier, the thermocouple output can be con­

nected directly to the multiplexer (Figure 15).

A shielded differential signal path was chosen for our design,

since the oven's environment is a very hostile one, where noise that is

produced by high voltage generators (270 Vac and 540 Vac) and other

electrical machinery, is a strong factor that can influence easily the

output voltage of the thermocouple (0-45 mv) for 0-1250°C, and conse­

quently, increase the error. Instrumentation amplifiers with their high

differential input impedance and high common-mode rejection ratio, were

also used to further minimize the error caused by the presence of noise.

The instrumentation amplifiers also provide a conversion from a

differential to single path, a gain amplification between the multi­

plexer and A-D converter, and finally prevents a loading effect due to

the multiplexer's ON resistance.

48

2.7 Thermocouple Instrumentation Card (An Alternative Design)

In consideration of the design of the thermocouple instrumentation

card (or the analog section of the voltage-to-frequency A/D converter),

two methods were used as an approach. The first one was to amplify the

output voltage of the thermocouple, then multiplex all the channels

before sending any particular signal to the V/F converter to start the

conversion (Fig. 16). The second method, which was later adopted and

used for the final design, took the approach of: multiplexing directly

the signal (i.e. the output v.oltage of the thermcouple), amplifying it,

and then connecting it to the input of the V/F converter. This latter

method proved to be successful under testing, and since it used one

amplifier per multiplexer, the total cost of this method is less than

the first -one which needed an amplifier per each differential channel of

the multiplexer.

Boosting the signal level before multiplexing will minimize the

errors due to r[)g(0n) and leakage currents of the multiplexer, which

could prove fatal if the multiplexer chosen has a high rDS(onj (say

10 K) and a high leakage currents (>100 nA). This will give 1000uV

drop across cDgjonj. This 1000uV figure might be considered accep­

table if the sensor output was 10V FS. However, thermocouple output of

16 mv FS over a 160°C temperature range correspondes to 100uV/°C.

Thus, the 1000 uV voltage drop across the switch is equivalent to 10°C

error - a deplorable level of accuracy.

The signal levels are boosted so that the MUX error becomes a much

smaller proportion of the multiplexer input signal. But as was

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explained, this technique is expensive and new sources of error are

introduced: op-amp offsets and temperature drifts.

As an alternative, spending a few dollars more to obtain a MUX

specified at 100 pA leakage current with rDgjonj of 900 ohms

proved to be successful in meeting our design's accuracy.

2.7.1 Commutating Auto-Zero (CAZ) instrumentation Amplifier

As was explained before, .the alternative design took the approach

of amplifying the thermocouple output voltage before multiplexing. To

achieve this, an Intersil ICL7605 CAZ instrumentation amplifier was

chosen. The main features of the ICL7605 are:

1. Exceptionally low input offset voltage - 2 uV *

2. Low long term input offset voltage drift - 0.2 uv/year

3. Low input offset voltage temperature drift - 0.05 uV/°C

4. High common mode rejection ratio - 100 dB

5. Wide common mode input voltage range - 0.3 V above supply rail

6. Operates at supply voltages as low as +2 V

An important advantage of the ICL7605 instrumentation amplifier

(IA) over other types-of lAs, is the provision of self-compensation for

internal error voltages. Furthermore, the ICL 7605 have approximately

constant input equivalent noise voltage, CMRR, PSRR, input offset volt­

age and drift values independent of the gain configuration. By compar­

ison hybrid-type IAs which use the traditional three op amp configura­

tion have relatively poor performance at low gain (1 to 100) with

improved performance above a gain of 100.

52

The only major limitation of the ICL 7605 is its low frequency

operation (10 to 20 Hz maximum). However, since we are dealing with

thermocouples with their operating frquency of DC to 10 Hz, the CAZ

speed is quite adequate.

Compared to the standard bipolar or PET input op amps, the CAZ amp

scheme demonstrates a number of important advantages:

1. Effective input offset voltages can be reduced from 1000 to

10,000 times without trimming.

2. Long-term offset voltage drift phenomena can be compensated

and dramatically reduced.

3. Thermal effects can be compensated for over a wide operating

temperature range. Reductions can be as much as 100 times or

better.

4. Supply voltage sensitivity is reduced.

Ul in Pig. 16a shows the complete design of the ICL 7605, which is

the same as for 02 or in any other channel needed. [It was only decided

to design two channels, since the other three left should have the same

configuration, anyway.]

To have a maximum output frequency of 100KHZ from the V/P converter

for a thermocouple output voltage of 50mV, an input voltage to the V/F

converter of 4V is required. Consequently, the CAZ instrumentation

amplifier was designed to have a voltage gain of 80 in a noninverting

mode.

R15 + R17 gain = 1 +

R13

= 81.72

53

R17 was chosen as a pot resistor to trim the gain to its desired

gain of 80.

Because of the charge injection effects which appear at both the

switches and the output of the voltage converter, the values of capac­

itors C2 and C4 must be about 1 uF to preserve signal translation

accuracies to 0.01%. The luP capacitors, coupled with the 30 Kohm

equivalent impedance of the switches, produce a low-pass filter response

from the voltage converter which is down approximately 3dB at 10Hz.

Input commutation transients in the ICL 7605 arise when each of the

on-chip op amps experiences a shift in voltage which is equal to the

input offset voltages (about 5-10 mV), usually occuring during the

transition between the signal processing mode and the auto-zero mode.

Since the'input capacitors of the on-chip op amps are typically in the

10 pF range, and since it is desirable to reduce the effective input

offset voltage about 10,000 times, the offset voltage auto zero capaci­

tors Ci and C3 must have values of at least 10,000 x 10 Pf, or 0.1 uF

each. The manufacturer suggested a 1 uF as a good choice.

Pin 8 (the Bias terminal) was grounded to lower the power dissipa­

tion of the on chip op amps. Pin 12 (the division ratio terminal) was

connected to V* to give the full division ratio. That is dividing the

oscillator frequency of 5.2 KHz by 32, which will result in a nominal

commutation frequency of approximately 160 Hz. The commutation frequen­

cy is that frequency at which'the on-chip op amps are switched between

the signal processing and the auto-zero modes. A 160 Hz commutation

frequency represents the best compromise between input offset voltage

and low frequency noise.

54

A supply voltage of +5 V was chosen/ because first it is within the

max supply voltage rating of ICL 7605 (+9V), and secondly a +5V is the

standard TTL voltage that many other devices in our design will use.

An 0.1 uF decoupling capacitor (Cg and C10) was connected to each

supply rail.

For a supply current of 5mA and assuming 0.5V'drop, then

R21 = 0.5V = 100 ohms. 5mA

2.7.2 Over Voltage Protection

The maximum supply voltage rating of the ICL 7605 CAZ instrumen­

tation amplifier is +9V, and the manufacturer recommends no more than

(V--0.3) to (V++0.3)V differential input voltage be applied to -DIFF IN

(Pin 18) to +DIFF IN (Pin 17). This maximum rating will cause no

problem when dealing with input voltages of 0 - 45 mV. The problem that

arises is the possibility of the occurance of a +270 Vac spike from the

voltage generator that is used to melt the glass inside the furnace.

To avoid destroying the device by such a signal, an overvoltage

protection circuit was designed. The resistor/diode circuits will

protect the device if the supplies go to.ground or if the input exceeds

the supply. If either of these situations occur, the diodes will be

forward biased and current path to ground will exist. This will protect

the ICL 7605 from excessive current levels.

The primary purpose of the resistor (R9 or R10) is to limit the

current through the diode. Another advantage of using diode protection

is that, it prevents the input signal from passing to the output. This

55

is a result of the input being clamped to the breakdown voltage of the

zener diode (3.3V).

There are some disadvantages to the user of this type of protec­

tion. One would be the economics involved with using external protec­

tion for each analog input. This could present a certain problem if a

large number of channels were involved. Another possible source of

error is current leakage in the diodes.

Since cost is not a very important factor in our design, spending

extra dollars to protect our devices presented no problem. For the

case of current leakage in the diodes, the 1N3595 diode was chosen

specifically for its low leakage feature.

To limit the current in the 1N3595 to less than its maximum rating

of 200 mA*forward current, the R9 (for'the positive input) was calcu­

lated as follows (again referring to Fig. 16a):

R9 = 277V = 2.77 K 100 mA

The standard resistance is 2.74 K.

For an Xz - 0.25 mA for the 1N4620 zener diode

Rl • 5-3.3 = 6.8 K 0.25 mA

The 1N4620 zener diode is specified at a breakdown voltage of 3.3V

which is less than the (+5 +0.3) maximum rating of the differential

input voltage allowed without any damage to the ICL 7605 amplifier (i.e.

the signal will be clamped at 4V).

The same calculations and reasoning is done with the negative

signal path.

56

As can be seen, each signal path has a protection circuit to take

care of a negative or a positive overvoltage spike.

To summarize, overvoltage protection is necessary because the

signal lines are commonly subject to a number of destructive situations:

1. Analog signals may be present while the amplifier power

supplies are off.

2. The signal lines may receive induced voltage spikes from

nearbysources.

3. Static electricity may be introduced on the signal lines by

personnel or equipment.

4. Grounding problems are frequent: A.C. power line voltage at

high impedance can appear on the signal lines. Signal lines

•can be accidentally shorted to other voltage sources.

2.7.3 Types of Analog Switches

The most commonly used types of analog switches found in today's

data conversion systems are: reed relay, JFET, and CMOS. Reed relays

offer low ON and high OFF resistance and are capable of handling very

high voltages, but have slow speeds. JFET switches have lower OFF

leakage current and are capable of very high speeds. CMOS switches,

which are the most popular and widely used in multiplexer applications,

have low OFF leakage currents, good speed, and stable ON resistance

under varying input signal conditions.

Significant dynamic errors inherent to CMOS analog switches are OFF

channel leakage current and settling time value dictated by the device's

ON resistance and its inherent capacitance.

57

Other system restrictions may further narrow the field of candi­

dates suitable to performing the switching task. These restrictions

could include, low power budget, hostile environment, cost, alternate

sourcing, and package density.

2.7.4 The IH6108 Multiplexer

The Intersil IH 6108 (U3 in Pig. 16a) is an 8-channel CMOS analog

multiplexer with a leakage current of less than 100 pA, and rDSon of

less than 400 ohms, and a settling time of 0.3 us.

When selecting the proper CMOS analog switch, we looked for low

OPP leakage current, good settling time, latch free operation, and

stable ON resistance under varying analog signal input conditions.

Pig. 16a shows the connections of the IH 6108 multiplexer. As was

explained before, the design under consideration was made to show only

two channels out of the required five thermocouple channels. The other

three thermocouple channels will have the same connections as channel 1

and channel 2.

The other three inputs to the multiplexer are ; the thermistor

channel to measure the ambient temperature of the isothermal junction

block, the offset reference channel, and finally the reference voltage

channel.

Of the eight inputs to the multiplexer, Pig. 16a shows only four

channels: the two thermocouple channels (Pins 5 and 7) offset refer­

ence channel (Pin 4), and finally the Vreg reference channel (Pin 6).

Details of the thermistor channel will not be discussed here since the

actual design is the same as in the final version of the thermocouple

instrumentation card.

58

The address lines for the select channel are connected to the

computer via optocouplers (Fig. 16b).

Three line binary decoding is used so that the 8 channels can be

controlled by the 3 address inputs; additionally a fourth input is

provided to act as a system ENable. when the ENable input is high (+5V)

the channels are sequenced by the 3 line address inputs/ and when low'

(0V) all channels are off.

The decode truth table for the multiplexer, as provided by the

manufacturer, is shown below:

Table- 3 IH6108 Multiplexer Decode Truth Table

|1 Selected

1 2 3 4 5 6 7 8

Logic "1" - V0H > 2.4V VEN = +5

Logic "0" = V0L < 0.8

A computer software was written to deal with all the addressing

problems and temperature measurements processing. This program will

not be addressed in this thesis, nor will the interface card with

the computer.

S2 SI S0 EN

0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1

Channe

59

Now, for a supply voltage of +12V and a supply current of 5mA, the

multiplexer will need a current limiting resistor of:

R19 = 0.5V = 100 Ohms 5mA

It was assumed that, 0.5V drop across the resistor should be

sufficient to limit the required supply current to 5 mA.

A decoupling capacitor (C13) of 0.1 uF was connected to the resis­

tor to act as a power supply stabilizer, and a low pass filter when

taken as a network with the resistor.

Decoupling the Vcc line is the most common method used to counter

noise problems. High frequency noise (100MHz and above) and low frequen­

cy noise (less than 25 MHz) are common problems associated with all the

devices. Switching devices have their high frequency noise coming

from:

1. High frequency noise results from the device rapidly switching

logic levels. The bulk of the switching current from a low to

high transition shows up in Icc current surges, while the bulk

of the switching current from a high to low transition shows

up in ground current surges.

2. Noise is transmitted through the changing magnetic fields that

result from the changing electric fields in a switching line

and are picked up on adjacent signal paths. This problem is

also known as transmission lines "cross talk."

The low frequency noise results from the change in the Icc current

demand as devices change state.

60

2.7.5 Reference Channels

As was discussed before, for the autocalibration to be performed

by the computer software, two reference points are needed. The first

reference point (designated as the offset channel) was designed by

grounding Pin 4 of the multiplexer. The second reference point

(designated as the reference channel) was designed using the National

Semiconductor LM299A precision reference voltage zener, chosen to

provide stable, low temperature coefficient reference voltage. It

has the following advantages over ordinary zeners:

1. There is virtually no hysteresis in LM299A reference voltage

with temperature cycling.

2. It is free of voltage shifts due to stress on the leads.

3. Since the unit is temperature stabilized, warm up time is

fast.

U4 and U5 with their external circuitry represents the complete

design for the reference channel.

The zener inside the LM299A provides a 6.95V reference across R36

and R37.

Prom the graphs supplied by the manufacturer, the maximum surge

limiting resistor for a supply voltage of 24V and a 25°c operating

temperature, was found to be equal to 330 ohms. This resistor is

designated R35. A 2 uF capacitor (C24) was suggested by the

manufacturer to bypass the heater.

The maximum forward current for the LM299A is 1mA, and if another

0.5 mA is allowed to pass through R36 and R37, then

61

12 - 6.95 R34 » 3.36 K

1.5 mA

For a reference point of, say, 4V

R36 + R37 = 6.95 - 13.9 K 0.5mA

4 Now , R37 8 K

0.5mA

and R36 = 5.9 K

Now, to balance the input resistance to every channel of the multi­

plexer, the intersil ICL7600 auto zero instrumentation amplifier in a

unity gain mode was added to the LM299A to act as a buffer.

The error-storage capacitors C21 and C22 are each 1 uP value (as

suggested by the manufacturer), since this value provides a good compro­

mise between the minimum equivalent input offset voltage and the lowest

value of low-frequency noise.

The DR (division ratio) terminal ( Pin 14) is connected to the

power supply (V+) to provide a commutation frequency of 160 Hz.

Pin 9 (Bias terminal) is connected to ground. The Bias terminal

provides three programmable bias levels. These levels are set by

connecting the Bias terminal to V+, GND or V". The reason for this

current programmability is to provide the user with a choice of device

power dissipation levels, slew rate values (the higher the slew rate

the better the recovery from commutation spikes), and offset errors

due to chip "voltage drop" and thermoelectric effects (the'higher the.

power dissipation the higher the input offset error). The manufac­

turer suggests that the medium (GND) BIAS setting provides the best

choice.

62

Decoupling capacitors C20 and C23 of 0.01 uF each were connected

to each power supply terminal to act as a low pass filter with the

supply current limiting resistors R40 and R41.

For R40 = R41 and for a maximum supply current of 5mA and

assuming 0.5V drop across the resistor

R40 = 0,5V = 100 Ohms 5mA

2.7.6 Voltage Regulators

The +12V and -12V power supplies are readily provided by the

computer. Now, since +5V and -5V power supplies were used by many

devices in the circuit, a need arose to design voltage regulators that

can supply these voltages.

U10 is the +5V positive voltage regulator. C26 of 0.1 uF is

connected across the output to improve transient response, while C25

of also 0.1 uF is required, since the regulator is located an appre­

ciable distance from +12V power supply filter. Both values of the

capacitances are suggested by the manufacturer.

The only thing that was needed to be designed is R38 which was

calculated to provide a maximum quiescent current of 6mA.

Assuming 0.6V across the resistor, then

R38 = 0.6V = 100 Ohms 6mA

The input voltage for the uA 7805 voltage regulator has to range

8V £ Vin £ 20V. Consequently an 11.4V should be sufficient to drive

the circuit. The Fairchild uA 7800 series can provide up to 1A in

output current.

63

Ull is a negative (-5V) voltage regulator with an output current

in excess of 1A. As in the case of the positive voltage regulator,

the only component to be designed was R39.

For a maximum quiescent current of 2mA and assuming a 0.5V drop

across the resistor, then

R39 = 0.5V = 250 Ohms 2mA

This will complete our description of the alternative design,

since U6 through U9 have the same design components as in the final

version of the thermocouple instrumentation card, which will be des­

cribed in detail in the following chapter.

The alternative design {version B) was not tested, for the simple

reason of not implementing it as part of the final analog section of

the temperature measurement subsystem. Nevertheless, this design

should prove successful in its implementation if desired to be used.

CHAPTER 3

THERMOCOUPLE INSTRUMENTATION CARD

This chapter will discuss and describe the final design of the

thermocouple instrumentation card that was implemented and used as an

integral part of the temperature data acquisition system.

This chapter will also try to avoid rediscussing the architec­

ture, strengths, specifications and the problems associated with the

design. Consequently, the reader is advised to consult the correspon­

ding sections in Chapter 2 that dealt with the aforementioned points.

The reader is also advised to re-read section 2-2 which dealt with the

specifications of the design for a better understanding of the following

pages. To summarize these specifications, the circuit that was designed

had the following boundary conditions:

1. The input voltage to the circuit is between 0 - 50 mV for

0 - 1250°C range of the temperature to be measured.

2. The binary counter that is used in the Counter Card has a

maximum operating frequency of 40 MHz with guaranteed limits'

of 20 MHz at 25°C. Consequently, the output frequency of

the v-to-F converter (hereby considered the output of the

circuit) should well be within this range.

The implemented version of the thermocouple instrumentation card is

shown in Figure 17.

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67

As was discussed before/ the final version had the use of inter­

connecting the thermocouple channels directly to the multiplexer.

The desired output voltage of the particular channel will be

addressed via the computer, then amplified using an instrumentation (

amplifier, which in turn will send the amplified signal to the voltage

to frequency converter to start conversion. The resulting train of

pulses will then be transmitted to the counter card via fiber optic

transmitter. The counter card (not shown) will finally send the data

(via the Interface Card) to the computer to be processed.

The output frequency of the V-to-P converter changes linearly

with the output voltage of the thermocouple as the operating tempera­

ture of the furnace is changed. The computer will be able to trans­

late voltage into degrees centigrade by referring to the NBS (National

Bureau of Standards) tables supplied for the Nicrosil versus Nisil

(type N) thermocouple that was chosen for our design.

68

3.0 Thermocouple Instrumentation Card's Design

3.1 IH5208 Analog Multiplexer

The IH5208 is a 4-Channel differential and fault protected CMOS

analog multiplexer with an ultra low leakage current -lD(off) —

and an ros(on) of 0,7 K at 25°c*

The need for a differential input multiplexer was dictated by

the differential signal path that was decided upon as the design

approach for the thermocouple channels, while the low leakage current

with a small multiplexer will result in a small error

in temperature reading (in this case, an error of 7 x 10"^ ^C).

Because each card was designed originally to process 5 thermo­

couple channels, two multiplexers were needed as can be seen in Figure

17(a). The output voltage pins of the multiplexers are connected

together differentially and fed into a differential input single-ended

output instrumentation amplifier. The addressing lines Ag, Ap and EN

are also connected together. The EN lines were utilized to avoid the

need for a third multiplexer. By connecting EN1 to an inverter, it was

assured that one multiplexer will be off whenever a particular channel

in the other one is addressed.

The U2 multiplexer has three thermocouple channels and the ther­

mistor channel as inputs, while U3 has two thermocouple channels, the

reference channel and the offset channel as its inputs.

Power supply requirements for the IH" 5208 multiplexer.-are the same

as for the IH6108 multiplexer used in the alternative design, i.e.

+12V power supplies were used with a 5mA maximum supply current.

69

Calculating for both the positive and negative supply voltages, we find:

R26 = R27 = 0.5V = 100 ohms 5mA

As can be seen a voltage drop of 0.5V was allowed across the

current limiting resistors. A capacitor of 0.1 uF was added to act as

a low pass filter with the resistor.

The reference and offset channels show a 2.74 K resistors con­

nected to them. The reason behind that is the need to have equal

input resistance to each channel of the multiplexer. Since the

thermocouple channels needed a 2.74 K resistance to limit the current

through the diodes of their over voltage protection circuit, hence,

was the need to add an equal value resistances to each channel of the

multiplexer.

The same argument can be applied for the thermistor channel,

i.e. R17 + R18 • 2735 ohms = R20 + R18.

70

3.2. Thermistor Channel Design

A thermistor is a thermally sensitive resistor - i.e. a body that

exhibits change in electrical resistance with change in body tempera­

ture. Unlike resistance temperature detectors (RTDs), which consist

of wire-wound elements or metal films that exhibit small change in

resistance with temperature, thermistors are ceramic semiconductors

which exhibit large changes in resistance with changes in temperature.

To measure the ambient temperature of the isothermal junction, a

thermistor was chosen to act as the measuring device. Since the

thermistors are temperature sensitive resistors, a Wheatstone bridge

circuit was designed to measure the resistance of the thermistor at a

particular temperature. That information will then be sent to the

computer to be processed.

Figure 17a shows the circuit that was designed. The resistance

of the YSI 44033 thermistor at 25°C is 2252 ohms. A choice was to be

made between having resistors R16, R17 and R18 manufactured to the

exact value of the thermistor resistor or having the nearest 0.1%

standard value resistors (2260 ohms) as their value. Cost considera­

tions favored the second option and hence, a need to calculate the

error due to the resulting mismatch in the resistances value and the

thermistor resistor.

Figure 18 shows the Wheatstone bridge circuit or the thermistor

channel redrawn.

To find the temperature's reading error due to the mismatch, the

transfer function of the circuit was needed to be calculated.

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72

For Rj = thermistor resistor

Vin = Ul-zener reference voltage = 6.95V

now, Vout = V2 - VX

R17 Vi = VS -

R16 + R17

and R18 V2 = VS

R18 + Rrji

VS = vin

Req

Req + R15

where Req = (Rip + R18)//(R16 + Rl7)//R25

R25 Rt R16 + R25 Rt R17 + R25 R18 R16 +R,j, R18 R17

Rt R16 + Rq, R17 + R18 R16 + R18 R17 + R25 R18 + R25 R16 + R25 R17

then, R18 R16 - R17 Rm Vout = Vs ....(1)

(R16 + R17) (R18 + Rp) where,

Vin R25 (R^i + R18) (R16 + R17) Vs

R25 (Rt4R18) (Rl6+R17)-tR15 [ (RT4R18) (R164R17H-R25 (R1vlRl8flll&4Rl7) ]

Eq. (1) is for the worst case condition i.e. when the change due

to temperature in resistances R16, R17 and R18 is not equal.

Now, using eq. (1) we can find the inverse transfer function,

that is,

R18[VSR16 - Vout (R16 +R17) ] Rj ————• 1 ~~ ~~ ———— .... (2)

vout (R16 + R17) + Vs R17

73

And in terms of V^, Eqs. (1) and (2) can be written as,

Vin R25 (R18R16 - Rt,R17) Vout =

R25 (Rt-«18 ) (R16-W17 HR15 [ (R^vHUS) (R16-«17 )*R25 (Rr«164R174R18) ] • •»• (3)

and

R25 R16 R18 - VQUt. [R18 (R16+R17) (Rl5+R25)+Rl5R25 (R16+R17+R18) ]

^ Voutt<Rl6 + R17MR25 + R15) + R15 R25] + Vin R25 R17

The worst case condition is defined as:

1) Vout (max) = V2(max) - V^tmin)

2) For V2 = V^Onax), we need R18 = R18 + (D) R18 + (D) R18CT.C.)

Where,

(D) = Resistance Tolerance

T.C. = Tolerance due to temperature coefficient

while for V-j_ = v^min), we need R16 = R16(max) and

R17 = R17 (min) i.e.

R16(max) = R16 + D R16 + D R16 (T.C.)

and R17(min) = R17 - D R17 - D R17(T.C.)

Here, Rt is assumed constant at the particular temperature. Now,

we will calculate Rip error that results from the worst aase condition of

the resistors while keeping vout = Const, i.e. calculating how much Rrp

has to compensate for the worst case condition of the other resistors to

keep same Vout unchanged.

Now, if we assume that the isothermal junction temperature is at

50°c (hence RT = 811.3 ohms) and the board's temperature at 35°C, and

using 0.1% and 25 ppm/°C resistances, we can calculate:

74

R16 = 2260 + 2.26 + 0.565 = 2262.825 ohms = R18

Similarly, taking into account variations in resistances due to

tolerance and temperature coefficient, we can find for worst case

condition:

R17 = 2257.175 ohms

R15 = 5752.801 ohms

R25 = 100.125 ohms

and finally Vj^n = 6.9500695V

Using Eqs. 3 and 4, we can find;

Rj, = 811.30628 ohms i.e. an error of 0.00628 ohms

normalizing at 50°C, R/°C = 811.3 = 16.226 ohms/°C 50

or ' Error = 3.87033 x 10~4Pc

In other words, the computer will read the temperature of the

isothermal junction less by the calculated error, which is very small

indeed.

The above example, and many other calculations that were done and

which resulted also in very small errors, justified our choice of

using standard 0.1% and 25 ppm/°C resistance.

Now, going back to our Wheatstone bridge circuit and trying to give

a better design insight, we see that R16, R17 and R18 were chosen as

close as possible to the thermistor resistor (2252 ohms at 25°C) that is

needed to be measured as temperature varies. R15 on the other hand, was

calculated to be 5.76 K so that a voltage drop of 5,76V can be seen

across it, this will limit the output voltage of the thermistor channel

to less than 50 mV.

75

R25 and C4 act as a low pass filter, with C4 also acting as a

stabilizer for Vs.

3.3 LM299 Voltage Reference

The design of the LM299 voltage, reference, is basically the same as

the one for the alternative design discussed in section 2-7-5, with the

following differences: A resistance network of 14K and 100 ohms was con­

nected across the voltage reference's zener diode to supply a reference

voltage of 50 mV across the 100 ohms resistance. This 50 mV voltage

acts as our reference channel's voltage for the autocalibration. A

resistance {R21) of 2.64 K was connected to the reference channel to

give a total of 2.74 K input resistance to the multiplexer when added

with the 100 ohms resistance. All the input resistances to all the

multiplexer's channels are 0.1% precision resistors of 2.74 K value.

76

3.4 Over voltage protection Circuit

Conventional CMOS multiplexers can be protected against overvoltage

destruction by external resistor-diode networks to limit input current

to a safe level, but it is difficult to prevent another phenomenon with

overvoltage, normally - off switching elements will tend to switch on,

due to parasitic bipolar transistors in the CMOS structure, so the

overvoltage spike will appear at the multiplexer output. The IH5208

internal protection circuits eliminate the problem by automatically

shutting off the parasitic transistor during overvoltage conditions.

The resistor-diode network was described in detail in section 2-7-

2. To increase the efficiency of our over voltage protection circuit,

a 10 mA fuse was added to cut off the circuit completely in case an

excessive'over voltage spike was passed through the thermocouple channel.

Under input overload conditions, the user of AD-624 instrumentation

amplifier will see two diode drops C1.2V) between the plus and minus

inputs, in either direction. The AD-624 can withstand momentary over­

loads of with no harm to the device. Consequently, +8«2V zener

diodes were chosen to clamp the signal without destroying the AD-624 in

case of overvoltage spike. A 0.67 voltage leeway was left to account

for any extraneous variables.

A transzorb (5KP13) was added to the output of our switching power

supply to act as a high power transient voltage suppressor. The 5KP13

is designed to withstand a high level of peak current (max* 210A) while

allowing the fuse to blow before shorting. This will enable the user to

replace the fuse and continue operation. A 13V reverse stand-off volt­

age transzorb was chosen, since our power supply output voltage is +12V,

77

i.e. a +1V tolerance was allowed for our power supply.

For the overvoltage protection circuit to function properly, all

the devices should be ON i.e. a supply current should be established.

That was accomplished by designing the current limiting resistors (R1

and R2). These were calculated for a supply current of approximately

1mA to be:

12 - 8.2 - 0.7 Rl 150 Ohms = R2

1.027 x 10~3

As is the case in other circuits, bypass capacitors (C^ and C2) of

0.1 uF were connected between the supply voltage pins and analog signal

ground to provide with Rl and R2 a measure of decoupling between the

various circuits in the system.

78

3.5 AD-624 instrumentation Amplifier

The AD-624 is a high precision low noise instrumentation amplifier

designed primarily for use with low level transducers. An outstanding

combination of low noise, high gain accuracy, low gain temperature

coefficient and high linearity make the AD-624 ideal for use in high

resolution data acquisition systems.

The AD-624 has an input offset voltage drift of less than 0.25

uV/°c, output offset voltage drift of less than 10 uV/°C, CMER above 80

dB at unity gain, and maximum nonlinearity of 0.001% at G = 1.

The AD-624 does not need any external components for pre trimmed

gains of 1, 100, 200, 500 and 1000. Consequently, for a gain of 100 all

that was needed is connecting pins 13 and 3 to each other. Pin 6

(reference terminal) was grounded to provide a return path for the bias

currents of the input transistors of the dc amplifier.

The power supply requirements are the same for any other device in

our circuit.

79

3.6 AD-650 Voltage-to-Frequency Converter

The V/F converter is an electronic circuit that converts an input

voltage into a train of digital output pulses at a rate that is directly

proportional to the input. The relationship of input voltage to output

pulse rate is very nearly a straight line function. Another important

characteristic is that the output pulses are at levels that directly

interface with standard digital logic circuits such as DTL, TTL and

CMOS.

The only restriction on the analog data to be transmitted is that

it does not change too rapidly for the V/F converter to follow.

The AD-650 V/F converter provides a combination of high frequency

operation and low nonlinearity. The linearity error of the AD650 is

typically .0.005% of full scale at 100 KHz. It also has an open collec­

tor output with separate ground which allows simple interfacing to

either standard logic families or optocouplers.

The manufacturer states that only four component values must be

selected by the user. These are input resistance (R36), timing capaci­

tor (C14), logic resistor (R42), and integration capacitor (C13). The

first two determine the input voltage and full scale frequency, while

the last two are determined by other circuit considerations.

Of the four components to be selected R42 is the easiest to define.

As a pull up resistor, it was chosen to limit the current through the

output transistor (inside the AD-650) to 0.5 mA for a TTL maximum V0L of

0.4V.

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81

R36 and C14 are the only two parameters available to set the full

scale frequency to accommodate the given signal range. The variable

that is affected by the choice of R36 and C14, is nonlinearity.

The selection guide of Figure 19 (supplied by the manufacturer) shows

this quite graphically. In general, larger values of C14 (or Cos) and

lower full scale input currents (higher values of R^n (or R36)) provide

better linearity. In Figure 19 the manufacturer shows the implications

of four different choices of Rin, For a full scale frequency of 100 KHz

(corresponding to +5V input), Rin was selected to be equal to 42.4K and

CQS = 330 pF. This will give a nonlinear ity of 40 ppm or 0.0040%.

Using the following formula supplied by the manufacturer, we can

calculate our maximum output frequency:

VIN/RIN Fout = 0.15

CQS + 4.4 x 10™11F

Substituting,

10/42.4K = 0.15 = 94.572 KHz

330 x 10"12 + 4.4 x 10"11

This will give a time period of 10.5 u s, which should be easily

handled by the counter that can function with a frequency of up to 40MHz

or a pulse width of 25 ns.

The last component to be selected is the integration capacitor C13.

In almost all cases, the manufacturer suggests that the best value for

C13 can be calculated using the equation:

10~4 p/sec C13 (1000 pF minimum)

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When the proper value for C13 (or CINT) is used, the charge balance

architecture of the AD650 provides continuous integration of the input

signal, hence large amounts of noise and interference can be rejected.

If the output frequency is measured by counting pulses during a constant

gate period, the integration provides infinite normal mode rejection for

frequencies corresponding to the gate period and its harmonics. How­

ever, if the integrator stage becomes saturated by an excessively large

noise pulse, the continuous integration of the signal will be inter­

rupted, allowing the noise to appear at the output. Because of that,

the manufacturer suggests that increasing CINT to 2000 pF will provide

much more noise margin, thereby eliminating this potential trouble spot.

R40 is set to 1.24 K by the manufacturer to activate the bipolar

offset current of 0.5 mA when connected between pins 4 and 5 of the AD

650.

The internal bipolar current sink is used to provide a half-scale

offset for a +5V signal range, while providing a 100 KHz maximum output

frequency.

Terminals 2 and 4 of the AD 650 are connected together internally,

(Figure 20), and so the offset current of 0.5 mA with the grounded 10K

(R41) resistance will provide a -5V offset voltage at pin 2. Since pin

3 must also be at -5V (pins 2 and 3 make the differential input to an

internal op amp), the current through Rin is 10V/42.4K = 0.23 mA at

V^n = +5V, and 0mA when V^n = -5V.

Now, according to our design only a 0 - 5V input is expected to be

processed by the V/F converter. This will set the output frequency to

50 - 100 KHz full scale. The reason behind using a bipolar configuration

for the AD 650 was to account for any short in the thermocouple

terminals that could lead to a negative voltage output, i.e. an output

frequency of less than 50 KHz will indicate a negative input voltage

and hence, an error to be corrected.

85

3.7 HFBR - 1402 Fiber Optic Transmitter

To send the output frequency of the AD-650 to the counter in the

Counter Card, a need for a secure data transmission had arisen. Fiber

optics have become an ideal data link for applications requiring noise

immunity, extended distance, high bandwidth/ voltage isolation, intrin­

sic safety (no sparks), and secure data. These general characteristics

of fiber optics with the features of the HFBR-1402, were ideal for our

application.

The HFBR-1402 (U9 in Figure 17b) has high optical power output (-

17dB measured out of 1 meter of cable) and a wide operating temperature

range (-40°C to +Q5°C). Also, it can interface directly with an SMA

connector i.e. no receptacle is required.

Since the HFBR-1402 transmitter requires a 6-60mA drive current

range to be activated, and since the output current of the AD650 was

limited to 0.5mA by R42 (to supply TTL maximum V0L of 0.4V), a drive

circuit was designed. The circuit consists of a simple current booster

transistor. When the input (digital output of V/F) to transistorQ2

is low, Q2 will be cutoff and the output voltage V0H = 1.7 (voltage drop

across the input diode of HFBR-1402, connected between terminals

2 and 3). This will result in a current of I - (12 - 1.7)/560 = 18 mA

which should be enough to drive the fiber optic and hence, start

transmitting. On the other hand, if the input is high, transistor Qz

will be saturated and Vout = vot) = 0.3V. This will give a base current

of (5 - 0.7)/10K = 0.43 mA, and a collector current of 4.3 mA for

86

hpE(sat) whiGh will not be enough .to drive the fiber optic and

consequently the output voltage of the instrumentation card will be low.

The above operation will repeat itself for the whole period the V/F

converter is operating normally.

87

3.8 HCPL-2730 Optocouplers

The HCPL-2730 dual channel coupler contains a separated pair of

GaAs light emitting diodes optically coupled to a pair of integrated

high gain photon detectors. They provide extremely high current

transfer ratio (typ. 1000), low input current (0.5 mA), and an excellent

input-output common mode transient immunity. A separate pin for the

photo-diodes and first gain stages (Vcc) permits lower ouput saturation

voltage and higher speed operations than possible with conventional

photo-darlington type isolators.

The HCPL-2730 is used to provide both a digital logic ground isola­

tion and a- current loop receiver. The computer will address the multi­

plexers and receive data from them through two optocouplers designated

U6 and 07'in Figure 17b.

To enable one multiplexer and disable the other at the same time,

the output of U7 was connected directly to 03 Mux, and through an

inverter (Qj_) to U2 multiplexer.

The I0R Spec for the HCPL-2730 is 220 uA, while IIH = -30 uA for

the IH5208 multiplexer. To insure a minimum high of 3.5V, the pull-up

resistors (R33, R32 or R31) were calculated to be:

R31 = R32 = R33 = 5-3.5 = 6.8K 220 uA

This will insure enough current to enable 03, while for an input

high for Qx of 3.5v, hpE of 45, and V^g^) of 0.3V, a resistor R35 was

calculated to be 390K for an assumed base current of 7.4 uA.

88

Using the same parameters, R34 was calculated to be:

R = 5-0.3 = 14.24K 0.33 mA

R34 was actually chosen to be 15K.

This will ensure that one multiplexer is off, while any particular

channel in the other one is addressed.

With this, our description of the final design of the instrumen­

tation card is completed.

89

3.9 Test Cell

Figure 21 shows the test cell that was used in the testing of the

thermocouple instrumentation card to provide a variable input voltage

((-60) - (+60) mV) that acts as an equivalent to the output voltage of

the thermocouple under the operating temperature range (0-1250°C).

The test cell consists of two batteries of +18V and -18V respec­

tively to act as a power supply for the +12V voltage regulators. The

batteries were substituted for a real power supply, because of the

convenience of their size to be included in a box that accommodates the

test cell.

To check for the degradation of the batteries, a simple test

circuit was designed. The test circuit consisted of a switch, a

current was limiting resistor in series with a 12V zener diode and an

2 mA (1.8V) LED diode that has a small value resistor (R3) across it.

R3 acts as a current path to ground in case the LED diode is off.

Now, as long as the voltage of the batteries is above 15V, the LED

light will be on, but if the batteries fall below 15V, say 14V, then

14- 12-1.8 I « 0.333 mA

600

This value is below the 2mA operating current of the LED, and

consequently, this will indicate the need to recharge the batteries.

The resistor R3 was chosen small compared with the off resistance

of the LED, while R1 was calculated as follows:

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The LM7812 and LM7912 were designed following the same design

approach for the voltage regulators explained previously.

To provide a positive and a negative variable output voltage, two

precision voltage references were designed. Following the graphs sup­

plied by the manufacturer of the LM399, the maximum surge limiting

resistor was found to be 500 ohms (R5 or R6).

For a maximum current supply of 1.5 mA, R7 was calculated to be:

12 - 6.95 R7 = R8 3.36 K

1.5 ma

where the 6.95V is the zener's diode voltage rating of the LM399.

The outputs of the two precision voltage references were connected

together through a resistance network which consists of resistances R9,

R10, Rll and R12. The exact values of R9 and R10 were determined

experimentally.

For an output voltage of 60 mV, the current through R9 is

(6.95 - 0.06J/13.3K = 0.518 mA. Assuming the same current through the

combined network of R10, Rll and R12, this will give a required resis­

tance value of 7.01/0.518 mA = 13.53K, i.e. increasing the resistance

of the 100K pot will provide us with positive output voltage while

decreasing it will supply a negative voltage. The break point for a

zero output voltage is R12 = 11K.

To account for loading effects, the output voltage was connected

to an op amp in a unity gain connection. The op amp with its high

input impedance, will have very little effect, if any, on the output

voltage of the circuit. In any case, as long as the output voltage of

the circuit is close enough to the output voltage of the thermocouple

(50mV), the test cell should be sufficient for our testing purposes.

CHAPTER 4

TESTING OF THE THERMOCOUPLE INSTRUMENTATION CARD

The following pages will discuss the procedures and the results

of the testing done on the thermocouple instrumentation card (TIC).

The testing was done on a special prototype of the TIC (Fig. 22)

that had two thermocouple channels, which are designated Ul-Sl and

U4-S1 in Fig. 22a /Where the U is standing for the unit number of the

multiplexer on the circuit's schematic along with the S which is

standing for the channel number of the 4-channel multiplexers that were

chosen for our circuit. The final design will include a total of 5

thermocouple channels to both MUX'S.

4.1 Equipment List

1) Special prototype of the TIC.

2) A 3-switch current loop box for channel selection.

3) DC - voltage power supply source.

4) Specially designed test cell.

5) High resolution (6 - digits ) DVM.

6) Frequency counter.

7) Oscilloscope.

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4.2 Multiplexer'3 Channel Selection/Addressing Capability

Procedure

a) A 3-switch box with TTL output capability was constructed to

act as 3-addressing lines to the inputs of the two multiplexers.

b) The three TTL output addressing lines were connected to a

current loop socket acting as an input line for the TIC

multiplexers.

c) Different combinations of the addressing lines were used to

verify the addressing requirements for each channel of the two

multiplexers.

The results of the testing were as follows:

INPUT Ul-MUX U4-MUX CHANNEL SELECTED S2 SI S0 A0 A1 EN A0 A1 EN

QTBB 0~7&0' 0.00 4753 475*8 07¥8 475*8 478*8 4751 U4-S4 NO CONNECTION 0.00 0.00 1.52 0.02 4.88 0.08 0.02 4.88 4.81 U4-S3 OFFSET 0.00 1.52 0.00 4.88 0.02 0.08 4.88 0.02 4.81 U4-S2 REFERENCE 0.00 1.52 1.52 0.02 0.02 0.08 0.02 0.02 4.81 U4-S1 THERMOCOUPLE 1.52 0.00 0.00 4.88 4.88 4.88 4.88 4.88 0.02 U1-S4 COMPENSATION 1.52 0.00 1.52 0.02 4.88 4.88 0.02 4.88 0.02 U1-S3 OFFSET 1.52 1.52 0.00 4.88 0.02 4.88 4.88 0.02 0.02 U1-S2 REFERENCE 1.52 1.52 1.52 0.02 0.02 4.88 0.02 0.02 0.02 Ul-Sl THERMOCOUPLE

The above combinations of the addressing lines were used to select

any of the channels that were used in any of the subsequent testings

that were done in this chapter. The S0, SI, and S2 notations stand

for the-input voltage to the optocouplers, while the A0, A1 and EN

are the TTL addressing lines to the multiplexers i.e. theoutput

voltages of the optocouplers.

97

4.3 Input Protection Clamp

Using a DVM the voltages across the zener clamp diodes were

measured and the results were as following:

Z1 - 8.5186 Vdc

22 - - 8.5365 Vdc [Refer to FIG. 22 for the notations]

The zener diodes were designed originally to clamp at + 8.2 Vdc,

nevertheless the above results are within our accepted design

specifications (8.2 + 0.5 Vdc).

4.4 5-V Voltage Regulator

The output voltage of the voltage regulator was measured using

a DVM and it was reading a value of: Vout = 4.89 Vdc. This result

was read for our specified +12 Vdc power supply, and the DVM kept

reading a constant output voltage value even after the power supply

was varied substantially (> 6.3 V) to account for the effects of

any power supply variations on the performance of the 5-V voltage

regulator.

4.5 Operation of Voltage to Frequency Converter With Input Variations:

A special test cell was designed to provide a variable mV

level input voltage (Vin) to our TIC. [Refer to Fig. 21].

Procedure

1) Set up equipment. Apply power supply of ̂ 12 V. Allow to

stabilize.

2) Zero DVM as follows:

A) Disconnect leads at test circuit. Connect jumper between leads.

B) If ZERO light is on, then press button to turn it off.

3) Connect DVM to test cell output monitor jack.

4) Select the thermocouple channel by setting switches on channel

selector.

5) Adjust test cell for desired output (i.e. input voltage to the

instrumentation card) which is displayed on the DVM. Allow to

stabilize. Note and record (Vin).

6) Note and record the instrumentation card output frequency as

displayed on frequency counter (Pout).

The above procedure was applied for both multiplexers, and

the readings took into account the drift and accuracy of the

measuring instruments i.e. the instruments were readjusted

frequently. Still, doubts exist about how accurate were our

measuring instruments' readings, since our desired accuracy is

within the uV range.

4.5.1 Input-Output Correlation Measurements For The V/F Converter:

CHANNEL 01-S1 CHANNEL U4-S1

Vin (V) FOUt (KHZ) Vin (V) FOUt (KHZ)

0.000056 47.663 0.000024 47.573 0.005044 52.162 0.005061 52.142 0.010020 56.645 0.010030 56.620 0.015007 61.142 0.015018 61.114 0.020016 65.657 0.020038 65.639 0.025018 70.165 0.025013 70.124 0.030053 74.702 0.030059 74.671 0.035016 79.174 0.035035 79.155 0.040045 83.704 0.040035 83.662 0.045005 88.171 0.045015 88.147.. 0.050011 92.682 0.050015 92.648

As can be seen from the measurements above, our V/F converter is

working properly within our specified limits of error. The V/F

99

converter was desinged originally to function with an output frequency

of 50 KHz for a zero input voltage and a 100 KHz for an input voltage

of 50 mV. The error we are talking about ( a pulse period of 10 us for

a 100 KHz and a 10.78 us for a 92.680 KHz ) will have no significant

effect on our pulse period ( 40 ns ) needed for the counters. Expected

effect on the resolution is around 1-2 uV, which translates into 1-2

counts error.

4.6 Offset Voltage And Channel Variations Testing

Procedure

1) Set up equipment. Apply power supply of +_12 V. Allow to stabilize.

2) Zero DVM as following :

A) Disconnect leads at test circuit. Connect jumper between leads.

B) If zero light is on, then press button to turn it off.

3) Connect DVM to voltage reference monitor jack.

4) Select desired measurement channel by setting switches on

channel selector. [For channel selection table, refer to p.95]

5) Note and record reference voltage value as measured at the

monitor jack, displayed on DVM.

6) Note and record instrumentation board frequency as displayed

on frequency counter.

Data And Calculations

4.6.1 Offset Channel Measurement

The following measurements were taken with the input voltage

grounded:

CHANNEL

01-SI CJ1-S3 U1-S4 U4-S1 U4-S3

Pout (KHZ)

47.550 47.559 47.554 47.552 47.556

CHANNEL

CJ1-S1 U1-S3 U4-S1 U4-S3

POUt (KHZ)

47.533 47.537 47.533 47.536

4.6.2 Reference Voltage Channel Measurements

The reference voltage was used as an input to the channels with

a value of Vref = 0.047743 V, and the following readings were taken:

CHANNEL

Cl-Sl U1-S2 U4-S1 U4-S2

Fout

90.571 90.560 90.570 90.557

Now, define the followings:

F'l = Mean value frequency with Vin grounded.

F'2 = Mean value frequency with Vin = 0.047743 V.

Now,

F'l = 47.535 KHz F'2 » 90.564 KHz

F = F'2 - F'l = 43.029

Scaling factor » S.P. = Vin / F = 0.047743 / 43.029

= 1.10953 uV/Hz

101

4.6.3 Calculations

1) With Vin grounded:

CHANNEL

Ul-Sl U1-S3 U4-S1 U4-S3

FOUt (KHZ) (FOUt -F'l) (HZ)

47.533 47.537 47.533 47.536

-1 3 -1

2

Voffset (uV)

-1.10953 3.32859

-1.10953 2.21906

2) With Vin = 0.047743 V:

Define: Voffset = Vmeas - Vin

where,

CHANNEL

Ul-Sl U1-S2 U4-S1 U4-S2

Vmeas = (Fmeas - F'l) * S.F.

(KHZ) (KHZ) Fmeas Fmeas - F'l

90.571 90.560 90.570 90.557

43.037 43.026 43.036 43.023

(V) (Fmeas - F'l)

"^Ts.FT]

0.0477508 0.0477386 0.0477497 0.0477353

(UV) Voffset

7.84 -4.40 6.70

-7.70

Offset testing results indicate proper functioning of the channels

within the accepted limits of error. An offset value of 7.84 uV

translates into an error of around 0.234 of a degree centigrade.

4.7 Precision Voltage Reference Operation

The LM299 voltage reference output voltage was reading a value of

Vout = 7.0541 Vdc on its zener diode terminal for a power supply

of _+ 12 V. Data was collected to see the effects of power "supply .

variations on the value of our voltage reference as measured across

R18. This is our Vref, the input voltage to the channels.

4.7.1 Power Supply Effects On Vref

Procedure

1) Set up equipment and follow procedure 1 through 5 on p.98.

2) Vary the power supply as needed.

-HPS (V) -PS (V) Vref (V)

12 12 0.047744 13 12 0.047745 14 12 0.047745 15 12 0.047746 11 12 0.047744 10 12 0.047742 09 12 0.046816

12 12 0.047744 12 13 0.047745 12 14 0.047746 12 15 0.047745 12 11 0.047743 12 10 0.047743 12 09 0.047742 12 08 0.047743 12 06 0.047743

12 12 0-. 047744 13 13 0.047746 14 14 0.047749 15 15 0.047752 11 11 0.047742 10 10 0.047740 09 09 0.046820

12 12 0.047745 11 13 0.047743 10 14 0.047742 09 15 0.046837

12 12 0.047744 13 11 0.047745 14 10 0.047745 15 09 0.047746

As shown from the above data, the variations of Vref with power

supply variations is insignificant, and we can expect our circuit

to function properly within a good range of +/- 2 V.

103

4.7.2 Temperature And Vin Variations Effects On Vref:

Procedure:

1) Set up equipment. Apply power supply of +/- 12 V. Allow to stabilize.

2) Zero DVM as following :

A) Disconnect leads at test circuit, and connect jumper between leads.

B) If ZERO light is on, press button on DVM to turn it off.

3) Connect DVM to test cell output monitor jack.

4) Select measurement channel desired by setting switches on

channel selector.

5) Adjust test cell for desired output (i.e. input to instrumentation

card) as displayed on DVM, and allow to stabilize.

6) Note and record input voltage (Vin) as measured at test cell output

monitor jack, displayed on DVM.

7) Zero DVM as in step 2 above.

8) Connect DVM to voltage reference monitor jack.

9) Note and record reference voltage value as measured at monitor

jack, as displayed on DVM.

10) Disconnect the board and place it inside the oven chamber.

11) Adjust the temperature of the oven chamber for 55 °C and then for

75 °C. For each temperature, repeat the above procedure.

The data taken below will investigate the changes of Vref with

regard to Vin variations under different ambient temperatures for the

channels Ul-Sl and U4-S1.

2.1 Data For Rocnt Temperature:

ADDRESSING U4-S1 ADDRESSING Ul-Sl

Vin (V) Vref (V) Vin (V) Vref (V)

0.000047 0.047743 0.000030 0.047742 0.005066 0.047742 0.005019 0.047741 0.010007 0.047742 0.010035 0.047740 0.015016 0.047742 0.015010 0.047741 0.020034 0.047742 0.020014 0.047741 0.025005 0.047741 0.025019 0.047741 0.030038 0.047741 0.030014 0.047739 0.035028 0.047740 0.035026 0.047740 0.040038 0.047740 0.040027 0.047740 0.045037 0.047740 0.045034 0.047741 0.050030 0.047740 0.050028 0.047740

2.2 Data For 55 °C:

ADDRESSIHG Ul-Sl ADDRESSING U4-S1

Vin (V) Vref (V) Vin (V) Vref (V)

0.000027 0.047733 0.000019 0.047733 0.005049 0.047733 0.005033 0.047734 0.010040 0.047733 0.010075 0.047734 0.015040 0.047732 0.015013 0.047734 0.020047 0.047732 0.020048 0.047734 0.025044 0.047732 0.025022 0.047734 0.030015 0.047733 0.030027 0.047734 0.035021 0.047734 0.035018 0.047733 0.040020 0.047733 0.040023 0.047734 0.045012 0.047732 0.045062 0.047734 0.050019 0.047733 0.050035 0.047733

105

4.7.2.3 Data For 75 °C:

ADDRESSING Ul-Sl ADDRESSING U4-S1

Vin (V) Vref (V) Vin (V) Vref (V)

0.000006 0.047732 0.000030 0.047734 0.005013 0.047733 0.005014 0.047734 0.010020 0.047734 0.010012 0.047733 0.015019 0.047734 0.015009 0.047734 0.020016 0.047734 0.020048 0.047734 0.025033 0.047733 0.025021 0.047733 0.030006 0.047734 0.030030 0.047733 0.035015 0.047734 0.035032 0.047734 0.040024 0.047734 0.040032 0.047734 0.045047 0.047733 0.045028 0.047733 0.050031 0.047733 0.050012 0.047734

As can be seen from the data above our Vref varied around 2 uV

at room temperature and 1 uV at 55 °C and 75 °C from its respective

nominal values at the corresponding temperatures. Also, it decreased

around 10 uV at 55 °C and 75 °C from its nominal value at room

temperature. As it will be seen from later testings, this change had no

effect at all on our specified limits of error. In all cases, our design

can tolerate an error of +/- 2 mV in the nominal value of Vref, since

its final effect will be on the output frequency of the V/F converter

with its large output pulse width, as was explained before. The Vref

showed a consistent value at higher temperatures, which indicates that

increasing the temperature will have no further effect on the

performance of the voltage reference.

106

4.8 Results of The Linearity Test For The TIB

Procedure

1) Set up equipment. Apply power supply of +/- 12 V. Allow to stabilize.

2) Zero DVM as following:

A) Disconnect leads at test circuit. Connect jumper between

the leads.

B) If ZERO light is on, then press DVM button to turn it off.

3) Connect DVM to test cell output monitor jack.

4) Select measurement channel desired by setting switches on channel

selector.

5) Adjust test cell for desired output voltage (i.e. input to the

instrumentation card) as displayed on DVMr and allow to stabilize.

6) Note and record the input voltage (Vin) as measured at test cell

output monitor jack* displayed on DVM.

7) Note and record the instrumentation card output frequency (Fin) as

displayed on frequency counter.

8) Select the offset channel using channel selector.

9) Note and record the instrumentation card output frequency (Fo) as

displayed on frequency counter.

10) Select reference channel using channel selector.

11) Note and record the instrumentation card output frequency (Fr) as

displayed on frequency counter.

12) Zero DVM as in step 2 above.

13) Connect DVM to voltage reference monitor jack.

107

14) Note and record the reference voltage value as measured at monitor

jack, displayed on DVM.

15) Repeat steps 2-14 for 55 and 75 degrees centigrade.

4.8.1 Data And Calculations

4.8.1.1 Addressing Channel Ol-Sl (Room'temp.)

Vin (V) Fm (KHz) Fo (KHz) Fr (KHz) Vref (V)

0.000000 47.675 47.674 90.685 0.047747 0.005020 52.198 47.674 90.683 0.047746 0.010025 56.705 47.672 90.681 0.047746 0.015018 61.203 47.672 90.679 0.047747 0.020018 65.707 47.670 90.677 0.047746 0.025011 70.203 47.668 90.673 0.047747 0.030018 74.712 47.667 90.673 0.047747 0.035020 79.218 47.666 90.670 0.047746 0.040020 83.720 47.665 90.669 0.047746 0.045014 88.219 47.663 90.668 0.047746 0.050024 92.730 47.663 90.666 0.047746

4.8.1.2 Addressing Channel U4-S1 (Room temp.)

Vin (V) Fm (KHz) Fo (KHz) Fr (KHz) Vref (V)

0.000000 47.658 47.658 90.663 0.047746 0.005021 52.184 47.660 90.663 0.047747 0.010025 56.692 47.658 90.662 0.047747 0.015057 61.224 47.658 90.662 0.047747 0.020007 . 65.684 47.658 90.662 0.047747 0.025020 70.202 47.659 90.663 0.047747 0.030035 74.720 47.659 90.663 0.047747 0.035026 79.214 47.658 90.662 0.047747 0.040032 87.725 47.658 90.663 0.047747 0.045022 88.220 47.658 90.662 0.047747 0.050018 92.722 47.659 90.662 0.047747

4.8.1.3 Addressing Ul-Sl (55 °C)

Vin (V) Fm (KHz) Fo (KHz) Fr (KHz) Vref (V)

0.000027 46.919 46.899 89.737 0.047733 0.005049 51.427 46.898 89.737 0.047733 0.010040 55.911 46.899 89.736 0.047733 0.015040 60.398 46.898 89.736 0.047732 0.020047 64.891 46.898 89.736 0.047732 0.025044 69.377 46.898 89.735 0.047732 0.030015 73.840 46.896 89.734 0.047733 0.035021 78.332 46.897 89.735 0.047734 0.040020 82.819 46.898 89.734 0.047733 0.045012 87.299 46.896 89.733 0.047732 0.050019 91.793 46.896 89.733 0.047733

,1.4 Addressing U4-S1 (55 °C)

Vin (V) Fm (KHZ) Fo (KHz) Fr (KHz) Vref (V)

0.000019 46.909 46.894 89.734 0.047733 0.005033 51.410 46.894 89.735 0.047734 0.010075 55.935 46.894 89.736 0.047734 0.015013 60.371 46.897 89.737 0.047734 0.020048 64.888 46.897 89.737 0.047734 0.025022 69.357 46.898 89.739 0.047734 0.030027 73.851 46.899 89.739 0.047734 0.035018 78.330 46.898 89.738 0.047733 0.040023 82.824 46.898 89.740 0.047734 0.045062 87.348 46.899 89.739 0.047734 0.050035 91.811 46.899 89.738 0.047733

1.5 Addressing Ul-Sl (75 °C)

Vin (V) Fm (KHz) FO (KHZ) Fr (KHz) Vref (V)

0.000000 46.530 46.529 89.273 0.047734 0.005026 51.034 46.530 89.274 0.047734 0.010016 55.501 46.530 89.273 0.047734 0.015003 59.966 46.529 89.271 0.047734 0.020042 64.480 46.529 89.271 0.047734 0.025015 68.933 46.530 89.271 0.047734 0.030035 73.428 46.528 89.272 0.047734 0.035010 77.885 46.529 89.272 0.047734 0.040012 82.365 46.529 89.271 0.047734 0.045041 86.869 46.529 89.270 0.047733 0.050042 91.346 46.529 89.270 0.047733

4.8.1.6 Addressing 04-Sl <75 °C)

Vin (V) Fm (KHz) Fo (KHZ) Fr (KHz) Vref (V)

0.000000 46.525 46.525 89.270 0.047735 0.005024 51.026 46.527 89.270 0.047734 0.010020 55.501 46.528 89.270 0.047734 0.015044 60.001 46.527 89.270 0.047734 0.020022 64.460 46.528 89.270 0.047734 0.025024 68.940 46.528 89.271 0.047734 0.030034 73.427 46.528 89.272 0.047734 0.035054 78.102 46.528 89.270 0.047734 0.040059 82.405 46.528 89.272 0.047734 0.045022 * 86.851 46.529 89.272 0.047734

4.8.2 Calculations of Error And Non-Linearity

Define: Scale Factor = S.F. = Vref / {Fr - Fo)

Vmeas = (Fm - Fo) x S.F.

Error (meas) = Era = Vmeas - Vin

Non-Linearity = Max. Em x 100 / Vref

Error (rms) = sq. root of the mean sq. value of Em

4.8.2.1 Calculations For Ul-Sl (Room temp.)

(KHz) (V / KHz) (KHz) (V) (UV) Fr - Fo S.F. X0.001

°l l 1

ni

Vmeas Em

43.011 1.11011 0.001 0.000001 1 43.009 1.11013 4.524 0.005022 2 43.009 1.11013 9.033 0.010027 2 43.007 1.11021 13.531 0.015022 4 43.007 1.11019 18.037 0.020024 6 43.005 1.11026 22.535 0.025019 8 43.006 1.11024 27.045 0.030026 8 43.004 1.11026 31.552 0.035031 11 43.004 1.11026 36.055 0.040030 10 43.005 1.11024 40.556 0.045026 12 43.003 1.11029 45.067 0.050037 13

(Em)

1 4 4 16 36 64 64

.121 100 144 169

Error (rms) = 8.107 uV

Non-Linearity = 0.0272 %

110

4.8.2.2 Calculations For U4-S1 (Room temp.)

(KHz) (V/KHz) (KHZ) (V) (UV) A Fr - Fo S.F. X0.001 Fm - Fo Vmeas Em (Em)±.

43.005 1.11024 0.000 0.000000 0 0 43.003 1.11031 4.524 0.005023 2 4 43.004 1.11029 9.034 0.010030 5 25 43.004 1.11029 13.566 0.015062 5 25 43.004 1.11029 18.026 0.020014 7 49 43.004 1.11029 22.543 0.025029 9 81 43.004 1.11029 27.061 0.030045 10 100 43.004 1.11029 31.556 0.035036 10 100 43.005 1.11026 40.067 0.040032 11 121 43.004 1.11029 40.562 0.045035 13 169 43.003 1.11031 45.063 0.050033 15 225

Error (rms) = 8.82 uv

Non-Linearity = 0.0314 %

4.8.2.3 Calculations For Ul-Sl (55 °C)

(KHz) (V/KHz) (KHZ) (V) (UV) A Fr - Fo S.F. X0.001 Fm - Fo Vmeas Em (Em)_

42.838 1.11426 0.020 0.000022 - 5 25 42.839 1.11424 4.529 0.005046 - 3 9 42.837 1.11429 9.012 0.010042 2 4 42.838 1.11424 13.500 0.015042 2 4 42.838 1.11424 17.993 0.020048 1 1 42.837 1.11427 22.479 0.025047 3 9 42.838 1.11426 26.944 0.030022 7 49 42.838 1.11429 31.435 0.035027 6 36 42.836 1.11431 35.921 0.040027 7 49 42.837 1.11427 40.403 0.045012 0 0 42.837 1.11429 44.897 0.050028 9 81

Error (rms) = 4.9267 uV

Non-Linearity = 0.01885 %

4.8.2.4 Calculations For U4-S1 (55 °C)

111

(KHZ) (V/KHz) (KHz) (V) (UV) #1 Fr - Fo S.F. X0.001 Fm - Fo Vmeas Em (Em)—

42.840 1.11421 0.015 0.000007 - 2 4 42.841 1.11421 4.516 0.005032 - 1 1 42.842 1.11418 9.041 0.010073 - 2 4 42.840 1.11423 13.474 0.015013 0 0 42.840 1.11423 17.991 0.020046 - 2 4 42.841 1.11421 22.459 0.025024 2 4 42.840 1.11423 26.952 0.030030 3 9 42.840 1.11421 31.432 0.035022 4 16 42.842 1.11418 35.926 0.040028 5 25 42.840 1.11423 40.449 0.045069 7 49 42.839 1.11424 44.912 0.050043 8 64

Error (rms) = 4.045 uV

Non-Linearity = 0.01675 %

,2.5 Calculation For 04--SI (75 °C)

(KHZ) (V/KHz) (KHz) (V) (UV) •I £| 1 1

£l

S.F. X0.001 Fm - Fo Vmeas Em (Em)±

42.745 1.11673 0.000 0.000000 0 0 42.743 1.11676 4.499 0.005024 0 0 42.742 1.11679 8.973 0.010021 1 1 42.743 1.11676 13.474 0.015047 3 9 42.742 1.11679 17.932 0.020026 4 16 42.743 1.11676 22.412 0.025028 4 16 42.744 1.11674 26.899 0.030039 5 25 42.742 1.11679 31.574 0.035261 7 49 42.744 1.11674 35.877 0.040065 6 36 42.743 1.11676 40.322 0.045030 8 64

Error (rms) = 4.647 uV

Non-Linearity = 0.01676 %

112

4.8.2.6 Calculations For Ul-Sl (75 °C)

(KHz) (V/KHz) (KHz) (V) (UV) A

Fr - Fo S.F. X0.001 Fm - Fo Vmeas Em (Em)—

42.744 1.11674 0.001 0.000001 1 1 42.744 1.11674 . 4.504 0.005029 3 9 42.743 1.11676 8.971 0.010018 2 4 42.742 1.11679 13.437 0.015006 3 9 42.742 1.11679 17.951 0.020047 5 25 42.741 1.11681 22.403 0.025019 4 16 42.744 1.11674 26.900 0.030040 5 25 42.743 1.11676 31.356 0.035017 7 49 42.742 1.11679 35.836 0.040021 9 81 42.741 1.11679 40.340 0.045051 10 100 . 42.741 1.11679 44.817 0.050051 9 81

Error (rms) = 6.03 uv

Non-Linearity = 0.02094 %

As seen from the above calculations, our instrumentation card

showed a better tolerance of error as the ambient temperature was

increased. The reason behind this phenomenone was attributed to the

increase in the negative offset voltage generated inside the V/F Converter

as the ambient temperature was increased and which oppposed our positive

offset voltage that was calculated under room temperature conditions

and consequently contributed to the total decrease in our offset voltage.

A new set of multiplexers were used to see whether that will make

any difference in our calculated results. The data collected and

calculated showed no significant difference in our offset voltage.

A table is made to translate the total error into its equivalent

of degrees centigrade (i.e. degrees centigrade error).

Prom the NBS tables of AWG 14 Nicrosil versus Nisil thermocouples

temperature °c as a function of thermoelectric voltage, reference

junction at 0 °C.

Using 500 ̂ as a reference temperature;

For 500.15 °C the thermocouple has an output voltage - 16.75 mV

Vout /°C - 16.75 mV/500.15 °C

=33.5 UV/°C

TEMP. Voffset (UV) DEGREES ERROR

Ul-Sl Room temp. 8.107 0.242 55 °C 4.926 0.147 75 °C 6.030 0.180

U4-S1 Room temp. 8.820 0.263 55°C 4.045 0.120 75°C 4.647 0.138

The method used to calculate the degree error was:

Thermocouple voltage of 33.5 uV translates into 1 °C

So,

DEGREES ERROR = Voffset (uV)/33.5 (uV/°C)

114

4.9 Test Results Of CMRR, DMR And PSR:

4.9.1 Common Mode Rejection Testing

Procedure

1) Connect AC signal source to both differential inputs of the channel

under test.

2) Set AC source to zero output amplitude. Adjust to desired

frequency (Fin).

3) Monitor input to the TIB with scope, and the TIC output with

frequency counter.

4) Select the offset frequency channel using the channel selector. Note

and record the output frequency (Po).

5) Select the channel under test using channel selector.

6) Slowly increase the output amplitude of the AC source until the

output frequency of the measurement channel (Fm) deviates by about

5 Hz from (Fo). This is the Vout.

7) Note and record the peak amplitude {A) of the AC signal displayed

on scope.

4.9.2 Data And Calculations of CMRR:

Note, Vout - 5 uV and

Adm = 100

Also define: Acm = Vout/(0.707 A) where (0.707 A) is the rms value

CMRR = |Adm/Acm| = 20 log |Adnt/Acm| dB

4.9. 2.1 Addressing Channel Ul-Sl:

Fin (Hz) Fo (KHz) A (Vpk) Acm |Adm/Acm| dB

2 47.614 8.8 8.0365xl0"7 1.24x10s 161.90 10 47.613 8.8 8.0365X10*7 1.24x10s 161.90 20 47.611 8.8 = Above = Above =

30 47.609 8.8 = = -

60 47.608 8.8 = 3 =

120 47.607 8.8 = a =

180 47.605 8.8 = = =s

240 47.605 8.8 =s

300 47.603 8.8 — =

600 47.602 8.8 8.0365X10"7 1.24x10s 161.90 1 K 47.601 1.6 4.4200X10-6 22624434 147.09 2 K 47.598 1.5 4.7147x10"® 21210257 146.53 3 K 47.598 1.5 4.7147X10"6 21210257 146.53 4 K 47.600 1.5 = Above = Above =

6 K 47.599 1.5 = = =

8 K 47.596 1.5 S3 = =

10 K 47.594 1.5 4.7147xl0"6 21210257 146.53 20 K 47.593 1.4 5.0515X10-6 19796100 145.93

4.9. 2.2 Addressing Channel U4-S1:

Fin (HZ) Fo (KHz) A (Vpk) Acm |Adm / Acm| dB

2 47.590 8.8 8.0365 xl0-7 1.244 xl08 161.90 10 47.590 8.8 8.0365X10"7 1.244x10s 161.90 20 47.589 8.8 =Above =Above =

30 47.589 8.8 3 = =

60 47.589 8.8 = = . =

120 47.588 8.8 =2 = s

180 47.589 8.8 = =

240 47.588 8.8 = =

300 47.587 8.8 = = =

600 47.586 8.8 8.0365xl0"7 1.244x10s 161.90 1 K 47.585 1.6 4.42xl0-f 22624434 147.09 2 K 47.584 1.6 4.42x10"*° , 22624434 147:09 3 K 47.584 1.5 4.7147X10"6 21210257 146.53 4 K , 47.583 1.5 4.7147X10-6 21210257 146.53 6 K 47.582 1.5 = — =

8 K 47.581 1.5 =

10 K 47.580 1.5 4.7147X10-6 21210257 146.53 20 K 47.580 1.4 5.0515x10-6 19796100 145.93

116

As can be seen from the above results, our circuit has a very high

common mode rejection ratio (161.90 dB for a 60 Hz 8.8 V noise signal),

and showed a consistently high CMER even with the presence of a very

high noise signal. ( See above, for even with the presence of a

noise signal of 20 KHz 1.4 V our CMRR is around 146 dB).

4.9.3 Differential Mode Rejection Testing:

Procedure

1) Ground one differential input of the channel under test, and

connect AC signal source to the other input.

2) Monitor the output frequency of TIC with frequency counter, and

*

monitor the input signal with scope.

3) Set AC signal source to zero output amplitude. Adjust to desired

frequency (Fin).

4) Select the offset reference channel. Note and record the output

frequency (Fo).

5) Select the channel under test.

6) Slowly increase the amplitude of the AC signal source until the

output frequency of the measurement channel (Fm) deviates by about

5 Hz from the (Fo).

7) Note and record the peak-peak amplitude (A) of the AC signal

displayed on scope.

4.9.3.1 Data And Calculations:

Note Vout = 5 uV , Adm = Vout/(0.707 Apk)

Where 0.707 Apk = The rms value of the AC signal

4.9.3.2 Addressing Channel Ul-Sl:

Fin (Hz) FO (KHZ) Apk-pk (mV) Adm dB

10 47.574 1 0.01414 -36.98 20 47.574 3 4.714x10"! -46.53 30 47.573 3 4.714X10"3 -46.53 40 47.572 3' 4.714x10"! -46.53 50 47.572 3 4.714x10"! -46.53 60 47.571 4 3.536x10"! -49.03 80 47.570 6 2.357x10"! -52.55 100 47.570 8 1.768x10"! -55.05 200 47.570 15 9.429x10"} -60.51 400 47.570 60 2.357x10"} -72.55 600 47.570 135 1.047x10 -79.59

4.9.3.3 Addressing Channel U4-S1:

(mV) Fin (Hz) Fo (KHZ) Apk-pk • Adm dB

10 47.570 1 0.01414 -36.98 20 47.569 3 4.714X10"3 -46.53 30 47.570 3 4.714x10"! -46.53 40 47.570 3 4.714x10"! -46.53 50 47.570 3 4.714x10"! -46.53 60 47.569 4 3.536x10"! -49.03 80 47.569 6 2.357x10"! -52.55 100 47.569 10 1.414X10"3 -56.99 200 47.569 20 7.072x10*} -63.01 400 47.568 80 1.768x10"} -75.05 600 47.568 140 1.010X10"4 -79.91

The results shown above indicates a good differential mode

rejection of noise by our circuit.

118

4.9.4 Power Supply Rejection Testing:

Note:

1) AC signal source coupled to power supply line with capacitor and

resistor summing junction. AC riding power supply monitored with scope.

2) Readings taken from board parameters at varying noise amplitude

levels { 60 Hz ), measured pk-pk.

3) The data below was collected after the protection circuit testing

was done.

Data And Calculations

Note: Vin = 0.0 : for all the data collected

4.9.4.1 AC Signal Source Connected to (-12 V) PS Line:

A (mV) Pm (KHz) Fo (KHz) Fr (KHz) Vmeas (V) CHANNEL

10 47.664 47.666 90.665 0.047749 Ul-Sl 100 47.664 47.666 90.666 0.047749 Ul-Sl 500 47.664 47.665 90.665 0.047749 Ul-Sl 10 47.663 47.661 90.663 0.047749 -U4-S1 100 47.663 47.663 90.664 0.047749 U4-S1 500 47.663 47.662 90.664 0.047749 U4-S1

4.9.4.2 AC Signal Source Connected to (+12 V) PS Line:

A (rriV) Fm (KHz) Fo (KHz) Fr (KHz) Vmeas (V) CHANNEL

10 47.664 47.663 90.665 0.047749 U4-S1 100 47.664 47.665 90.665 0.047749 U4-S1 500 47.663 47.664 90.664 0.047749 U4-S1 10 47.664 47.664 90.664 0.047749 Ul-Sl 100 47.663 47.664 90.664 0.047749 Ul-Sl 500 47.664 47.663 90.664 0.047749 Ul-Sl

119

Now, following the same method for calculating the error on p.108

we proceed into calculating the error incured on our results by

the presence of noise.

Calculations For (4.9.4.1)

(KHZ) (V/KHz) (KHz) (V) <uV) Fr - Fo S.F. X0.001 Fm - Fo Vmeas Error CHANNEL

42.999 1.11046 -0.002 —0.000002 -2 Ul-Sl 43.000 1.11044 -0.002 -0.000002 -2 Ul-Sl 43.000 1.11044 -0.001 -0.000001 -1 Ul-Sl 43.002 1.11039 0.002 0.000002 2 U4-S1 43.001 1.11041 0. 000 0.000000 0 U4-S1 43.002 1.11039 0.001 0.000001 1 U4-S1

Error (rms) = 1.00 uv

Note that error due to noise is pretty small. Also note that

there is a negative offset voltage on Ul-Sl, and a positive one

on U4-S1. This can be attributed to device mismatch, or more likely

to the accuracy of the measuring instruments.

Calculations For (4.9.4.2)

(KHZ) (V/KHz) (KHZ) (V) (UV) Fr - Fo S.F. X0.001 Fm - Fo Vmeas Error CHANNEL

43.002 1.11039 0.001 0.000001 1 U4-S1 43.000 1.11044 -0.001 —0.000001 -1 U4-S1 ' 43.000 1.11044 • -0.001 —0.000001 -1 U4-S1 43.000 1.11044 0.000 0.000000 0 Ul-Sl 43.000 1.11044 -0.001 -0.000001 -1 Ul-Sl 43.001 1.11041 0.001 0.000001 1 Ul-Sl

Error (rms) = 0.666 uV

Note that error due to noise is less by an average of 1 uv with

the (+12 V) power supply lead than it is with the (-12 V) power supply

lead, which can be attributed to the design response of the different

120

devices making up the instumentation card.

It can also be seen that no effects were introduced on our

measurements , even with the presence of 500 mV ripple voltage on

either lead of the power supply. In other words, our circuit rejects

completely 0.5 V ripple voltage without any effects on the performance

of our refernce voltage. [See the consistency of the Fm, Fo, Fr, and

Vref measurements].

4.10 Power Supply Requirement And Variation Testing

Procedure -/ •

1) Follow the same procedure for the non - linearity testing.

2) Vary the power supply as needed.

Data And Calculations

4.10.1 Addressing Channel U1 - SI;

+PS (V) -PS (V) Fm (KHz) Fo (KHz) Fr (KHz) Vref (V)

12 12 47.623 47.618 90.643 0.047744 13 12 47.620 47.613 90.650 0.047745 14 12 47.621 47.613 90.665 0.047745 15 12 47.622 47.612 90.678 0.047746 11 12 47.607 47.603 90.612 0.047744 10 12 47.606 47.603 90.594 0.047742 09 12 47.607 47.604 89.750 0.046816

12 - 12 47.623 47.615 90.641 0.047744 12 13 47.625 47.618 90.661 0.047745 12 14 47.623 47.618 90.675 0.047746 12 15 47.628 47.620 90.696 0.047745 12 11 47.607 47.600 90.601 0.047743 12 10 47.600 47.593 90.571 0.047743 12 09 47.585 47.578 90.528 0.047742 12 08 48.670 48.663 92.718 0.047743 12 06 49.233 49.229 93.754 0.047743

12 12 47.623 47.617 90.642 0.047744 13 13 47.623 47.614 90.670 0.047746 14 14 47.612 47.603 90.686 0.047749 15 15 47.599 47.584 . 90.689 0.047752 11 . 11 47.603 47.598 90.580 0.047742 10 10 47.605 47.601 90.546 0.047740 09 09 47.570 47.568 89.631 0.046820

12 12 47.632 47.631 90.660 0.047745 11 13 47.637 47.632 90.664 0.047743 10 14 47.644 47.639 90.675 0.047742 09 15 47.650 47.643 89.874 0.046837 13 11 47.649 47.642 90.671 0.047745 14 10 47.627 47.620 90.638 0.047745 15 09 47.605 47.597 90.602 0.047746

122

4.10.2 Addressing Channel U4-S1:

+PS JV)_ -PS (V) Fm (KHz) Fo (KHz) Fr (KHz) Vmeas (V)

12 12 47.627 47.614 90.639 0.047744 13 12 47.624 47.613 90.651 0.047745 14 12 47.623 47.610 90.661 0.047745 15 12 47.621 .47.609 90.673 0.047746 11 12 47.613 47.602 90.608 0.047744 10 12 47.612 47.603 90.593 0.047742 09 12 47.613 47.604 89.747 0.046816

12 12 47.626 47.616 90.640 0.047744 12 13 47.629 47.616 90.655 0.047745 12 14 47.627 47.613 90.672 0.047746 12 15 47.632 47.616 90.692 0.047745 12 11 47.612 47.599 90.598 0.047743 12 10 47.602 47.591 90.569 0.047743 12 09 47.589 47.576 90.528 0.047742 12 08 48.676 48.662 92.714 0.047743 12 06 49.234 49.221 93.752 0.047743

12 12 47.628 47.614 90.638 0.047744 13 ' 13 47.626 47.611 90.666 0.047746 14 14 47.616 47.599 90.681 0.047749 15 15 47.598 47.581 90.683 0.047752 11 11 47.606 47.596 90.578 0.047742 10 10 47.609 47.600 90.544 0.047740 09 09 47.574 47.567 89.630 0.046820

12 12 47.636 47.625 90.651 0.047745 11 13 47.641 47.630 90.660 0.047743 10 14 47.647 47.636 90.674 0.047742 09 15 47.652 47.647 89.875 0.046837

• 13 11 47.652 47.639 90.667 0.047745 14 10 47.628 47.615 90.631 0.047745 15 09 47.609 47.596 90.599 0.047746

As can be seen from the above data, our reference voltage did

not change in any significant way within about +/- 2 V variation

of the power supply, which will give us that range of circuit stability.

123

4.10.3 Power Supply Requirements:

The circuit was designed to have a power supply of +/- 12 V.

Calculating the biasing current requirements for the positive

lead of the power supply we found that we need 19.3 mA, so

P = VI - 231.619 mW

On the negative lead, the biasing current requirements was calculated

to be 12.5 mA, and

p = vi • 150 mw

4.11 Fiber Optics Testing

The fiber optics reciever was connected to the counter card

inside the PC computer. An oscilloscope was used to verify the operation

of the fiber optics reciever which proved to be functioning properly.

4.12 Protection Circuit Testing

Procedure And Results

1) Remove 01 and U4 from the board, and then turn the power supply on.

2) Connect a variable AC voltage source to the input PI. Monitor the

AC voltage at the input and at CRl. [For the notations refer to the

circuit schematic].

3) Set AC source to zero,, then gradually increase to 100 Vac (rms).

The AC voltage at CRl cathode was observed to increase to 9.8 Vac as

the input was increased, and stayed at that value even when the

input was increased beyond 100 V. The input resistor R3'- was noted to

get hot indicating a high power dissipation.

124

4) The AC was then disconnected, adjusted to 277 Vrms and turned off,

and again reconnected to the input as before.

5) The AC source was turned on, the input voltage measured 277 Vrms

and the CR1 cathode clamped at 10.5 Vac. The resistor R3 emitted

visible smoke. Fuse opened after several seconds. AC source was then

turned off.

6) The board power supply was turned off.

7) AC source adjusted to zero. New fuse installed. AC.source turned on

and gradually increased to 100 Vrms. The CR1 cathode voltage did not

exceed 8.9 Vrms. R3 became hot.

8) AC source disconnected from input, adjusted to 277 Vrms, turned off

and reconnected to the input.

9) AC source turned on. Fuse opened immediately. CRl cathode never

reached clamping voltage (Highest meter reading was less than 5 Vrms).

The AC source was then disconnected and testing proved the

effectivness of our protection circuit.

125

4.13 Conclusion:

As could be seen from the data and the calculations done on many

parameters of the TIB, the following conclusions are reached:

The 5-V voltage regulator was supplying a voltage of 4.89 Vdcr

which lead to considering our TTL output level 1 to be 4.88 Vdc

instead of the nominal 5 V.

The V/P converter will supply a frequency of 92.730 KHz for an

input voltage of 50 mV. This means that a pulse width of 10.8 us

will be sent to the counter card, which can tolerate this easily,

since it is designed to function with a pulse width of upto 40 nS

or 25 MHz.

The precision voltage reference was supplying a Vref of 0.047744 V

at room temperature, and showed a stability of +/- 2 uV for a

change of 0 - 50 mV in the output voltage of the thermocouples.

The stability was seen to improve with the increasing temperature

and was calculated to be +/- 1 uV. Increasing the ambient

temperature to 55 °C or 75 °C will decrease the Vref by around 10 uV

This was seen to have no effect on the final calculations of error.

Actually the opposit was observed i.e. it decreased the total error

by around 4 uV.

The nonlinearity of the circuit was calculated to be 0.0272 %

at room temperature and improved with the increasing ambient

temperature to 0.0188 % and 0.0209 % for 55 °C and 75 °C

respectivly.[Figures are for 01 calculations].

126

The total error of the TIC was calculated to be:

Offset Voltage + Nonlinearity (uV)

25 °C 55 °C 75 °C

Ul-Sl 8.107 4.926 6.030 U4-S1 8.820 4.045 4.647

As can be seen from above, the total error depends on the

circuitry associated with each thermocouple channel. The difference

of accuracy of each channel is considered as part of the non reducible

errors associated with the TIC.

4.13.1 Reducible and nonreducible errors:

The reducible errors are those associated with the tolerances

and specifications of the devices used in the design. The better

they are met, the less errors we should expect. The reducible errors

will be eliminated through autocalibration. The devices that have been

selected to meet our specs are:

Resistances with a low temp, coefficient of +/- 25 ppm/C and

0.1 % tolerance. These are 2.74 K, 2.64 K, 3.36 K, 42.4 K and 1.24 K.

Resistances of*+/- 100 ppm/C and 5 % tolerance. These are 100,150,

360 ohms and 15, 390 and 6.8 Kohms.

Military standard Ceramic capacitors of 0.1, 1, and 2.2 uF.

8.2 V, 5-W Zener diodes with temp, coeff. of 2 mV/C.

5-v Voltage regulator with a temp, coeff. of - 1.3 mV/C and a long term

stability of 20 mV and output noise voltage of 40 uV for frequency of

upto 100 KHz.

Multiplexers with TTL compatibility and low leakage current of

less than 100 pA.

AD 624 instrumentation amplifier with TC of 5 ppm/C, nonlinearity of

0.001 % max, and an input offset voltage of 25 uV max with a drift of

0.25 uV/°C max.

LM 299 precision voltage reference with TC 0.0005 %/°C max,

RMS noise of 20 uV, and 20 ppm stability for 1000 Hrs.

AD 650 V/P Converter with nonlinearity of 0.005 % at 100 KHz,

calibration error drift +/- 150 ppm/C, and an offset voltage drift

of +/- 30 uV/°C.

The nonreducible errors are those resulting from:

1) Conversion error;

The resolution of the TIC is:

at Vinl = 0 V Foutl = 47.-550 KHz

at Vin2 =*0.047743 V Fout2 = 90.571 KHz

Resolution - (Vin2 - Vinl)/(F2 - Fl)

= 1.10976 uV/Hz

or the conversion error is +/- 1 count.

2) Offset error due to offset variation between zero reference

channel and measured channel. The calculations showed that this

error is variable and depends on the internal and external -

circuitary associated with each multiplexer. As an average, the

offset voltage was calculated to be:

Refering to page 98;

Fout - 47.554 KHz = Mean value frequency

Voff (uV) (Voff)2

Ul-Sl -4 16 U1-S3 5 25 U1-S4 0 00 U4-S1 -2 04 U4-S3 2 04

Voff (cms) = 3.13 uV

3) Nonlinearity of gain in AD 624 and AD 650:

AD 624 max 0.001% X 50 mV - 0.5 uV

AD 650 typ 0.005% X 50 mV = 2.5 uV

max 0.02% X 50 mV = 10 uV

4) Gain Calibration Scale Factor

at 25 °C, change of Vref = 2 uV

at 55 °C and 75 °C, change of Vref = V'ref = 1 uV

LM 299 TC; typ = 0.00002% /°C

max = 0.00005% /°C

LM 299 long term stability; 0.002% /1000 hrs

V'ref = 2 uV /1000 hrs

Assuming 3 months calibration interval, V'ref = 3 uV

Measured temperature induced drift at 55 °C, V'ref = 10 uV

25 °C 55

V'ref (uV) 3 10 Voffst (uV) 1 -5

Conversion (uV) 1 1

TOTAL 5 uV 6 uV

25 °C Scale factor error - 5 uV/50 mV = 0.01 % of reading

55 °C Scale fatcor error = 6 uV/50 mV = 0.012 % of reading

129

5) Noise, both component and power supply generated

The error due to the presence of 60 Hz noise in the power supply

leads was calculated to be 1.527 uV for the negative lead and

0.913 uV for the positive lead. With a conversion error of 1 uV/Hz

this could be even smaller. The CMRR and DMR for a 60 Hz noise

were calculated to be 161.90 dB and - 49.03 dB respectivly.

The total measured error of the TIC was calculated to be 8.107,

4.923 and 6.030 uV for 25 °C, 55 °C and 75 °C respectivly. This

error was better than our error budget estimates, which was 11.9 uV

and 23.0 uV. The reason behind this difference is attributed to the

fact that estimates were done for the maximum error expected, and that

the reason behind small errors with the increasing temperature was

that the V/P converter generated negative offset error that opposed

the positive error that was calculated under normal room temperature

conditions.

From page 113; the total error in degrees centigrade was

calculated to be;

TEMPERATURE Voffset (uV) DEGREE ERROR

Ul - SI Room temp. 8.107 0.242 55 °C 4.926 0.147 75 °C 6.030 0.180

U4 - SI Room temp. 8.820 0.263 55 °C 4.045 0.120 75 °C 4.647 0.138

As can be seen from the above data, the maximum variation

between the two thermocouple channels in degrees centigrade

occured at 75 °C and was calculated to be 0.042 °C.

The temperature instrumentation board can function within the

above specified limits of error with +/- 2 V variation of the power

supply, which was specified to be +/- 12 V.

The power supply requirements are 231.62 nW for the positive

lead and 150 mw for the negative lead.

For the protection circuit a fuse of 10 mA will be used, and

this will open for a Vac greater than 47.4 V and the zener

diode will clamp at 8.5 V.

LIST OF REFERENCES

13X

The Engineering Staff of Analog Devices, Inc. (1986) Analog-Digital Conversion Handbook (3rd edition), pp. 3-64, pp. 169-211, pp. 371-387, pp. 473-668.

Harris Corp. (1986). Analog Product Data Book. Appl. Notes Nos: 520, 521, 522, 524, 531, 532, 535.

Patrick H. Garrett (1981). Analog I/O Design Acquisition: Conversion: Recovery, pp. 1-15, 53-72, 113-119, 135-139.

Intersil Inc. (1980), Data Acquisition Handbook, pp. 1-56, 211-225, 297-318, 328-359.

Intersil Inc. (1985), Application Handbook, Appl. Notes Nos: A020, A032, A05.1.

Fairchild (1978) Diode Data Book: IN3595 High Conductance Low Leakage Diodes, pp. 3-66.

National Semiconductor (1973), Linear Applications Handbook 1: Appl. Notes Nos. AN-21, AN-74. ""

Motorola (1980), Zener Diod Manual, pp. 1.1 - 1.9, 4.1 - 4.10, 6.1-6.19. IN5344 Zener Diode, p. 10.3.

Intersil (1986), Component Data Catalog, ICL7605 pp. 4.23-4.33, IH5208 pp. 3.127-3.134, IH6108, pp. 3.149-3.154.

Fairchild (1978), Voltage Regulator Handbook, pp. 1.3-1.22, pp. 3.3-3.27. UA7805C, p. 7.35. UA7905C p. 7.8.

National Semiconductor (1982), Voltage Regulator Handbook, pp. 7.1-7.21, LM 399/299, pp. 10.127-10.132.

Texas Instruments (1977), The Voltage Regulator Handbook, pp. 1-22.

General Semiconductor Industries, Inc. (1985), Product Data Book, 5KP13, p. 1.28.

National Semiconductor (1980), Data Conversion/Acquisition Databook, Appl. Notes Nos. AN-156, AN-161, AN-173, AN-363.

NBS Monograph 161 (1978), The Nicrosil versus Nisil Thermocouple: properties and thermoelectric reference data.

Meyer Sapoff, Thermistors for Resistance Thermometry, Thermometries, Inc. (reprint from Measurements and Control), April 1980.

132

Burr Brown, Application Notes, Nos. AN-75, AN-103, AN-89, AN-101, AN-79.

Hewlett Packard Co., Appl. Note 290. "Practical Temperature Measurements."

Analog Devices (1984), Data-Acquisition Databook, Appl. Notes pp. 20.3-20.30, AD650, pp. 11.15-11.26.

Hewlett Pakard Co. (1986), Optoelectronics Designer's Catalog, HCPL-2730, pp. 3.61-3.64, HFBR 1420, pp. 4.27-4.30.