In-Depth Study of Simultaneous Switching Noise

Patterns for Different Signaling Topologies

Kundan Chand, Hui Liu, Dan Oh

Altera Corporation

101 Innovation Dr, San Jose, 95134, CA, US

doh@altera.com

Abstract - Simultaneous switching noise (SSN) is one of the key

performance bottlenecks in design of single-ended signaling

systems such as DDRx, LPDDRx, and LVTTL interfaces. Good

power distribution network (PDN) is a must for high-end system

designs. Due to design limitation in die and package, providing

sufficient on-die capacitor (ODC) or on-package capacitor (OPD)

is a very challenging task. In this paper, we propose a novel on-

die decoupling scheme which places decoupling caps in core area

and connects to I/O area by package interconnects. Single-ended

signaling is also a common choice for SiP interface designs

including WideIO interface where SSN impact can dominate the

timing error compared to on-board interface designs where

crosstalk is still the most critical factor for timing error. One of

the crucial tasks in SSN analysis is determining the excitation

data pattern. We also propose a reasonable worst case SSN data

patterns for both terminated and un-terminated channel types

and compare the performance using simulations.

I. INTRODUCTION

Power distribution network design is a major challenge for

DDR designs. The quality of the power supply, seen by the

circuits on the die, is important for proper circuit performance

and the ability to meet timing and jitter specifications. The

power distribution network (PDN) for the package die

combination is an important consideration in determining

power supply quality. Through the use of on-package

decoupling (OPD) capacitance and on-die capacitance (ODC),

the PDN performance can be improved but it costs die or

package area.

With continuous progress of semiconductor technology,

hundreds of high speed fabric I/Os, sixty or more multi-

gigabit data-rate transceivers, and a million logic elements

(LEs) are incorporated on the same die. In order to reduce

SSN noise, the supply pins continue to increase as shown in

Figure 1 and Figure 2.

Figure 1. Power distribution design challenges

Figure 2. Power supply inductance vs. number of pins

Analyzing SSN with a complex passive channel including

both signal and power return paths is a quite challenging task.

Accurate SSN analysis requires a detailed full-circuit driver

model to capture the nonlinearity of circuit with large supply

noise and complex passive channel model with accurate signal

and power return paths to capture signal to power coupling.

Besides a long simulation time to capture both intersymbol

interference (ISI) and low frequency power noise, even

making a SPICE to converge is quite challenging for such

complex systems. Thus, much of research has been done to

improve the efficiency of SSN analysis over last decade [1].

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One of the crucial tasks in SSN analysis is determining the

excitation data pattern. Although one can use a generalized

peak distortion analysis (GPDA) to find the worst case data

pattern [1], [2], it often is too cumbersome as the data pattern

has to be regenerated for different channel settings. Hence, it

would be useful to define a reasonable worst case data pattern

depending on the signaling types instead of fine detail channel

settings.

In this paper, we propose the different SSN data pattern for

both terminated and un-terminated channel types. The

terminated channel consumes both AC and DC currents

whereas un-terminated channel consumes mostly AC current.

In contrast to common thinking, un-terminated channel also

consumes DC current for long channel to charge transmission

lines, special care is required for such cases. In this paper,

we cover all the cases including pseudo open drain (POD)

signaling case where only a pull-up termination is used.

Consideration of data rate to SSN analysis is also discussed in

this paper.

The second section of the paper gives an overview of the PDN

challenges for embedded vs. edge IO configurations used in

FPGA applications. Section III describes the SSN issues in

DDR3 designs and compares the performance between the

two IO configurations. In Section IV, the novel ODC island

scheme is explained and SSN improvement is quantified using

relevant simulations. Finally, in Section V the worst case SSN

patterns are proposed with simulation results followed by

conclusions in Section VI.

II. POWER DISTRIBUTION NETWORK CHALLENGES IN FPGA

APPLICATIONS

The integration of transceivers and DDR I/Os into FPGAs has

greatly facilitated system designs in many applications.

However, integrating them together has caused significant

challenges in FPGA package designs. Figure 3 and Figure 4

display the die floorplan for FPGA test chip using embedded

IO and edge IO columns. The embedded IO columns are

located close to the center of the die whereas the edge IOs are

located close to one edge. The embedded columns allow the

FPGA designer to fit in more number of transceivers in the

same die. While it is convenient to route out the PDN for the

edge IOs, package routing becomes more challenging for embedded IO PDNs. The use of on-package decoupling

capacitance (OPD) is also ineffective for embedded IOs due to

large hook-up inductance.

Figure 3. Die floorplan showing embedded IO column

Figure 4. Die floorplan showing edge IO column

Figure 5 displays the VCCIO PDN impedance profile for

embedded vs. edge IO for Altera FPGA test chip. The

impedance peak is much higher for embedded IOs due to large

VCCIO inductance caused by routing complexity. Since

VCCIO is routed below the package core layer, OPD is

ineffective due to large hook-up inductance. Therefore, the

SSN performance for embedded IOs is much worse compared

with edge IOs.

Figure 5. VCCIO impedance profile

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III. SSN ISSUES IN DDR3 DESIGNS

In contrast to most chip-to-chip I/O interfaces that use

differential signaling, the mainstream memory interface

designs are based on single-ended signaling such as SSTL or

PODL. Extending the data rate for single-ended signaling

beyond current data rate of a few Gb/s is becoming very

difficult due to SSO noise. Interestingly, DDR4 has mitigated

SSO noise compared with DDR3. This is due to two main

reasons.

Firstly, the data bus inversion (DBI) coding technique

introduced in GDDR4 reduces SSO noise significantly. DBI

reduces the “weight”, or total number of 1 or 0 states, of the

bus by inverting the polarity of the bus values. Proper

implementation of the encoding method will limit the “weight”

of an N-bit bus to N/2. The choice of reducing the number of 1

or 0 states depends on the details of the bus termination. In

GDDR4, which uses VCCIO referenced PODL signaling,

power is saved by reducing the total number of 0 states, since

they consume static current [4].

Secondly, DDR4 uses Pseudo-Open-Drain Logic (PODL)

signaling which has only pull-up termination [1]. The

presence of only a pull-up termination makes PODL signaling

to behave similar to open-drain signaling which significantly

reduces power consumption since there is no current flowing

during the high state. Evidently, DDR3 has worse SSN

performance compared to DDR4 due to above mentioned

reasons.

IV. NOVEL DECOUPLING SCHEME

On-die decoupling cap (ODC) or on-package decoupling cap

(OPD) can be used to improve VCCIO PDN for embedded

IOs. ODC must be located near the current source in order to

be effective. Increasing ODC generally leads to increase in die

area. Alternatively, connecting OPD closer to the die can be

challenging due to routing difficulties in the package. As

shown in Figure 6, OPD becomes less effective for embedded

IOs due to large hook-up inductance.

HDMIM is a high density on-die metal cap where cap plates

are located in between two of the upper die metal layers. It

allows the re-use of die space for capacitance purposes, which

is also being used for regular circuitry. HDMiM can be built

with low resistance connection to the PDN making it effective

for high frequency. Figure 6 below shows a typical HDMiM

cap implementation.

Figure 6. Package layout showing OPD hook-up connection

These HDMiM caps can be placed in different locations of the

die (ODC islands) and then connected together in the package

as shown in Figure 7. Actual usage of these ODC islands can

be configured or altered using the package routing layer,

instead of changing the die.

Figure 7. Novel on-die decoupling scheme using package layer

The above implementation is more effective than OPD due to

less hook-up inductance and also easier to connect. It reduces

the die cost and area by reducing ODC requirement. The same

die can be configured to meet different application needs e.g.

ODC can be assigned to different power rails just by

modifying package design.

Figure 8 shows the VCCIO impedance profile showing

improvement using ODC islands. There is significant PDN

improvement in the mid frequency range of 50 - 300MHz by

implementing this scheme. The multiple peaks in the red

curve are due to the hook-up inductance resonating with ODC

islands. The hook-up inductance value can be optimized

further by changing the package design.

Figure 8. VCCIO impedance profile showing improvement using

ODC island scheme

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Figure 9. Victim eye improvement using ODC island

Figure 9 shows the victim eye improvement using the

proposed scheme for embedded IOs. For this particular case

significant reduction in SSO noise is observed by

implementing this scheme.

V. SSN SIMULATION STUDY

Figure 10 displays the setup for DDR3 SSN simulation. The

eye diagram is simulated at the input of the DRAM receiver

when 48 fabric IOs are toggled simultaneously. The

simulation methodology used is explained in Error!

Reference source not found..

Figure 10. DDR3 simulation setup

A difficult challenge in SSN analysis is exciting and

simulating the proper data pattern. ISI and crosstalk are

dominated by high frequency switching activity whereas

power supply noise peaks at mid-range frequencies. Therefore,

the worst case channel analysis requires both medium and

high frequencies at the same time. First, one of the signal lines

is chosen to be the victim line. Then, immediate neighboring

signals are modeled as separate independent aggressors, in

order to generate the worst case crosstalk. The remaining

signals are modeled as SSN generating aggressors, and

excited using the same data pattern, which has strong PDN

resonant frequency content.

For the above setup, the victim is toggled using PRBS15

whereas the crosstalk aggressors are using PRBS10 to capture

high frequency noise. Since VCCIO PDN resonates at

medium frequency range, the SSN aggressors are toggled at

PDN resonant frequency. Figure 11 shows the different

aggressor patterns used while Figure 12 displays the on-chip

VCCIO noise corresponding to different SSN patterns.

“Toggling burst” pattern is 1010…0000…1010…burst which

toggles with DDR data rate as well as excites the PDN

resonant frequency. “Random burst” pattern is a

xxxx…0000…xxxx pattern which toggles with a mix of PDN

and DDR frequency harmonics.

Figure 11. Plot showing different aggressor patterns

Figure 12. Plot showing VCCIO noise at the chip sense line

It is evident from the above figure that the worst case SSN

noise happens when aggressors toggle at VCCIO resonance

frequency. 0 displays the victim eye diagram with aggressors

toggling with various patterns.

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Figure 13. Victim Eye-diagram at far-end of PCB with aggressors

toggling with different patterns

The worst case DDR3 noise happens when IO toggle with

toggling and random burst patterns.

VI. CONCLUSION

A novel on-die decoupling scheme is proposed which leads to

significant reduction in SSO noise without utilizing extra die

area. This scheme can also be implemented for multi-chip or

multi-die applications where ODC in one chip can be used by

other chips. Connection can be achieved by TSV, package

layer, interposer trace, or RDL as shown in Figure 14.

Figure 14. Other general applications for the decoupling scheme

This decoupling scheme implementation has various

advantages. For certain designs, this technique can be more

effective than OPD due to less hook-up inductance and is also

easier to connect than OPD. Also, by utilizing HDMIM

capacitors the overall system cost can be reduced due to less

die area being used for ODC. Moreover, the same die can be

configured to meet different package decoupling needs for

multiple applications. However, this scheme will take up extra

routing area on the package and hook-up inductance needs to

be minimized for maximum benefits.

The different SSN data pattern for both terminated and un-

terminated channel types have been proposed. It has been

shown that a mix of high and medium frequency data patterns

need to be chosen in order to generate worst case SSN. From

simulation results, it is proven that worst case SSN noise

happens when IOs toggle with random and toggling burst

patterns.

REFERENCES

[1] D. Oh and C. Yuan, High-Speed Signaling: Jitter Modeling, Analysis

and Budgeting, Prentice Hall, 2011.

[2] C.-C. Chou, H.-H. Chuang, T.-L. Wu, S.-H. Weng, and C.-K. Cheng,

“Eye prediction of digital driver with power distribution network noise,”

IEEE Electrical Performance of Electronic Packaging and Systems

Conference, pp. 131-135, 2012.

[3] L. D. Smith, R. E. Anderson, D. W. Forehand, T. J. Pelc, and T. Roy,

“Power distribution system design methodology and capacitor

selection for modern CMOS technology,” IEEE Transactions on

Advanced Packaging, pp. 284-291, Aug. 1999.

[4] D. Oh, W. Kim, et.al “Study of signal and power integrity challenges

in high speed memory I/O designs using single-ended signaling

schemes,” IEC DesignCon, Santa Clara, CA, 2008.

[5] T. Granberg, Handbook of Digital Techniques for High-Speed Design,

Upper Saddle River, NJ: Prentice Hall, NJ, 2004.

[6] M. R. Stan and W. P. Burleson, ”Bus-invert coding for low-power I/O”,

IEEE Transactions on VLSI Systems, vol. 3, No. 1, pp. 49-58, March

1995.

PRBS Clock

Toggling

burst

Random

burst

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