Improving Analog and RF Fill Generation Using Calibre PERC, YieldEnhancer and Pattern...
Transcript of Improving Analog and RF Fill Generation Using Calibre PERC, YieldEnhancer and Pattern...
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Improving Analog and RF Fill Generation Using Calibre PERC, YieldEnhancer and Pattern MatchingDonovan Kim, GLOBALFOUNDRIES Mohamed Essam Ibrahim, MentorErnesto (Gene) de la Garza, GLOBALFOUNDRIES Sherif Hany Mousa, Mentor
Matthew Hogan, Mentor
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Agenda
• Introduction
• Fill Evolution
• Net-aware Fill Flow
• Orientation-aware Fill Flow
• PDK availability
• Potential Future Work
• Conclusion
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Introduction – GLOBALFOUNDRIES at a Glance
• Created in 2009
• Acquired Chartered Semiconductor in 2010
• Acquired IBM Microelectronics in 2015
• Largest privately held semiconductor company
• World’s second largest semiconductor foundry
• ~10X capacity increase since 2009
• More than 250 customers
• 23,000+ patents and applications
• ~18,000 employees worldwide
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Introduction – Manufacturing Capacity
28, 22,12nm90–22nm
Up to 20k
(300mm)
14, 7nm
Up to 60k
(300mm)
Up to 80k
(300mm)
180–40nm
68k (300mm)
93k (200mm)
Burlington, Vermont Singapore East Fishkill, New York Dresden, Germany Malta, New York
350–90nm
40k
(200mm)
Cheng Du, China
TECHNOLOGY NODES
CAPACITY (WAFERS / MONTH)
Up to 7.7M Wafers / Year200mm equivalents
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Introduction - GLOBALFOUNDRIES CMOS Roadmap
Wireless,
Battery-powered Computing
High-performance
Computing
Markets
Servers, high performance
computing and graphics,
high-end smartphone,
core networking
Premium Tier
Features
High-performance,
balanced-cost
7nm
FinFET
14nm
FinFET
28nm
22FDX®
40/55nm
12FDXTM
Markets
Low & mid-end
smartphones, wireless,
IoT, autonomous vehicles,
mobile camera
Volume Tier
Features
Low-power, cost-effective
performance, RF,
embedded memory
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FILL EVOLUTION
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Fill Evolution & Main Drivers
• Support density constraints
– Local, gradient, magnitude and to max constraints
• Support analog requirements
• Match fill around cells, nets and devices
• Reduce variability created by adding fill
• Automate critical nets annotation
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65nm
SmartFill Context-aware Fill FlowsDummy Fill
≥90 nm All Nodes≤45nm
SmartFill
FEOL Fill
Filling MP layers
Symmetric Fill
Orientation-aware fill
Net-aware fill
Cell-based Fill
Density-aware Fill
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Power of GLOBALFOUNDRIES Fill Solutions
Performance
Runtime &
TAT
Accuracy & Consistency
Fill
Decks
Manual Identification & Annotation Fill
Calibre® PERCTM
AnnotationFill
Net-Aware Fill Flow
Orientation-Aware Fill Flow
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Best-in-Class Fill decks
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Net-Aware Fill Flow
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Impact of Fill on RF/Analog Device Targeting & Process Control
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Akira Tsuchiya and Hidetoshi Onodera, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 56, NO. 12, DECEMBER 2008
Parasitic capacitive coupling between the signal wire and fill is an important consideration in fill placement, shape, and size in RF/analog designs.
In addition, as design frequencies increase, the effects of eddy current become increasingly significant:• As frequencies increase, the effect of eddy
currents increase• Effective resistance increases due to eddy
current loss
Resistance and capacitance targeting, control, and modeling are challenged by competing needs to meet process-enabling metal density and maximum open-space requirements, and to minimize parasitic coupling interactions between the fill shapes and critical device features.
Need flexible Fill flow to meet challengesof high frequency RF/Analog devices
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Net-Aware Fill Flow Challenges
Need to remove fill
shapes around
critical nets
Traditional Fill Flow Net-aware Fill FlowManual Nets Annotation
1 2
3
Challenges
– Slow manual process1-2 min per net per ECOe.g.: 100 nets 2 hours
– Error prone
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Annotation
o ADD Marker Manually o GDS/OASIS property o Attach layout text
Identification Fill Flow (Calibre YE)
Net-Aware Fill Flow (Manual Annotation)
• Slow
• Iterative
• Error prone
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User Defined Critical Nets
Critical net Annotation
Critical nets Exclude layer
Manually add Exclude layer
Create Exclude layer
Pre Fill flow (prevent shape
placement)
Post Fill flow (remove placed
shapes)
Manual/Slow
ASCII list from:
- PEX & STA
- Name & Class
(“all clk”)
- Analog Sims
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Annotation
Critical net Annotation
Identification Fill Flow (Calibre YE)
Net-Aware Fill Flow (Automated Annotation)
• Fast
• Single shot
• Consistent
• Integration requires no change in Fill decks
• Increased flexibility
ASCII list from:
- PEX & STA
- Name & Class
(“all clk”)
- Analog Sims
User Defined Critical Nets
Create Exclude layer
Post Fill flow (remove placed
shapes)
Calibre PERC Flow
Cross Ref. Database
Designers
Critical
nets
Automatic Net
Annotation
Pre Fill flow (prevent shape
placement)
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Benefits of Net-Aware Fill
Today’s analog Flow NEW Net-aware Flow
AutomationManual nets selection,
human error prone
Fully Automated,
reliable
SpeedSlow
(interactive mode)
Fast
(batch mode)
Use Model
Layout name focus
Source schematic names require
cross-referencing step
Works seamlessly for both schematic
and layout net names
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Next InnovationOrientation-Aware Fill
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Orientation-Aware Fill Flow Challenges
• Traditional fill flows scan whole area without considering the orientation
• Major/Minor shifts realized
– Critical instances of some blocks
– Cell level (e.g. inductors)
• Shifts impact
– Matching (electrical requirements)
– Consistency (process requirements)
Minor Shifts
Systematic Shift
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Fill interaction w/ spiral inductor
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Tsuchiya, Akira, and Hidetoshi Onodera. "Effect of Dummy fills on characteristics
of passive devices in CMOS millimeter-wave circuits." ASIC, 2009. ASICON'09.
IEEE 8th International Conference on. IEEE, 2009.
Quality factor, Q =𝑚𝑎𝑔𝑛𝑒𝑡𝑖𝑐 𝑒𝑛𝑒𝑟𝑔𝑦 𝑠𝑡𝑜𝑟𝑒𝑑 𝑖𝑛 𝒊𝒏𝒅𝒖𝒄𝒕𝒂𝒏𝒄𝒆)−(𝑒𝑙𝑒𝑐𝑡𝑟𝑖𝑐 𝑒𝑛𝑒𝑟𝑔𝑦 𝑠𝑡𝑜𝑟𝑒𝑑 𝑖𝑛 𝒄𝒂𝒑𝒂𝒄𝒊𝒕𝒂𝒏𝒄𝒆
(𝑒𝑛𝑒𝑟𝑔𝑦 𝑙𝑜𝑠𝑡 𝑖𝑛 𝒓𝒆𝒔𝒊𝒔𝒕𝒂𝒏𝒄𝒆)
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Orientation-Aware Fill Flow
Physical Verification:
Analysis rule file
Rule_101 {
@ rule check
}
known
Patterns/blocks
Full Chip
Classify
Unique
Patterns
Capture
Pattern Processing
Fill unique patterns &
re-capture (custom markers)
Fill
Consistent Fill
Calibre®
PERC™
Calibre®
Pattern
Matching
Calibre®
Yield
Enhancer
Calibre®
Pattern
Matching
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Orientation-Aware Fill Flow (14nm Design)
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Traditional Fill Flow Orientation Aware Fill FlowXOR
Orientation-aware Flow fills inductor instances
with different orientations with high consistency
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Benefits of Orientation-Aware
Today’s analog Flow NEW Orientation-aware Flow
Fill Consistency Systematic and Minor shifts Fully consistent
Speed No Impact on Runtime
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Availability at GLOBALFOUNDRIES
• NET-Aware Fill flow is availablelfor 22FDX and 12LP as fill Supplement Pkg*
• Orientation-Aware Fill flow is available for 22FDX as Fill Supplement Pkg*
*for more details Fill release notes in PDK. Please contact Mentor field team for support
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Future Work
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Integrated high-resolution CMPMODEL topography analysis of fill size, shape and spacing for critical RF/analog designs to meet topography-based DFM rules.
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Future Work
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Integrated high-resolution CMPMODEL topography analysis of fill size, shape and spacing for critical RF/analog designs to meet topography-based DFM rules.
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Conclusion
• GLOBALFOUNDRIES provides leading edge Fill solutions for advanced nodes
• GLOBALFOUNDRIES leverages the Calibre platform
– Integration of Calibre PERC, YieldEnhancer and Pattern Matchingto develop a fully automated solution
Net-Aware Fill Flow Orientation-aware Fill Flow
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Manual Identification & Annotation Fill
Calibre® PERCTM
AnnotationFill
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