IMPLEMENTATION OF A PEAK WINDOWING …summit.sfu.ca/system/files/iritems1/4085/etd2498.pdfto Simon...

IMPLEMENTATION OF A PEAK WINDOWING ALGORITHM FOR CREST FACTOR REDUCTION IN

WCDMA

Hiten N. Mistry B.A.Sc. (Honours), Simon Fraser University, 2003

A PROJECT SUBMITTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF

MASTER OF ENGINEERING

In the School of

Engineering Science

O Hiten N. Mistry 2006

SIMON FRASER UNIVERSITY

Summer 2006

All rights reserved. This work may not be reproduced in whole or in part, by photocopy

or other means, without permission of the author.

APPROVAL

Name: Hiten N. Mistry

Degree: Master of Engineering

Title of Project: Implementation of a Peak Windowing Algorithm for Crest Factor Reduction in WCDMA

Examining Committee:

Chair: Dr. Daniel Lee Associate Professor of the School of Engineering Science

Dr. Shawn Stapleton Senior Supervisor Professor of the School of Engineering Science

Mr. Jeffrey Lai Supervisor Test Manager, Nokia Mobile Phones

Date DefendedIApproved: A p p ; 1 I 2006

tat SIMON FRASER @ UN~VERS~TY~ i brary f&&

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Simon Fraser University Library Burnaby, BC, Canada

ABSTRACT

Wideband Code Division Multiple Access (WCDMA) composite downlink

signals from the base station have high Peak-to-Average Ratio (PAR) as the number of

users increase. The PAR is also known as Crest Factor (CF), the ratio of the peak power

to the mean power of the signal, or how high the signal peaks are. A base station power

amplifier is performance limited by high CF.

This project involves implementing and improving a published Crest Factor

Reduction (CFR) technique to limit PAR and avoid amplifier saturation. Matlab

simulations are performed before implementing the algorithm in an Altera Field-

Programmable Gate Array (FPGA). Each algorithm is simulated and then compared

using signal quality parameters Error Vector Magnitude (EVM) and Adjacent Channel

Leakage power Ratio (ACLR). The improvement to the algorithm is shown to decrease

EVM and CF while maintaining similar ACLR values as the windowing length is varied.

ACKNOWLEDGEMENTS

I would like to thank my senior supervisor, Professor Shawn Stapleton for his

guidance during this project, and making this project workable with the travel schedule

assigned by my employer. I would also like to thank PhD student Wan-Jong Kim for his

continued assistance during the project, which was essential when using and debugging

the FPGA Development Board. Wan-Jong had initially investigated this project and

pointed me to most of the key literature he had already found. Also, I'd like Jeffrey Lai,

who has encouraged my post-graduate studies from the start. Finally, there are many

friends, co-workers, and family members who have provided the support needed to

pursuit a Master of Engineering degree while maintaining the responsibilities of working

in industry.

TABLE OF CONTENTS

.. Approval ......................................................................................................................... 11

... Abstract ............................................................................................................................ 111

Acknowledgements ..................................................................................................... iv

Table of Contents ............................................................................................................... v ..

List of Figures ............................................................................................................. v11 ...

List of Tables .................................................................................................................. vlll

............................................................................. List of Acronyms and Abbreviations ix

1 Introduction ................................................................................................................ 1

2 WCDMA System ........................................................................................................ 3 2.1 Overview of WCDMA system .............................................................................. 3

..................................................................................................... 2.2 Spreading Code 3 2.3 Direct Sequence Spread Spectrum System ............................................................ 4 2.4 Quality Parameters ................................................................................................ 8

.................................................................................................... 2.4.1 Crest Factor 8 2.4.2 Adjacent Power Leakage Ratio ...................................................................... 8 2.4.3 Error Vector Magnitude ................................................................................. 9

..................................... 2.4.4 Complementary Cumulative Distribution Function 10 ................................................................................................. 2.5 Power Amplifier -10

3 Crest Factor Reduction ............................................................................................ 12 ............................................................................. 3.1 Overview of CFR Techniques 12

................................................................................................... 3.1.1 Clipping 1 3 .......................................................................................................... 3.1.2 Coding 13

.......................................................................................... 3.1.3 Peak Windowing 14 ........................................................................................ 3.1.4 Adaptive Clipping 14

3.1.5 CFREngine .................................................................................................. 15 ......................................................................................... 3.2 Windowing Algorithm 15 ......................................................................................... 3.2.1 System Overview 15 ........................................................................................ 3.2.2 Algorithm Details 1 9

4 Simulations ................................................................................................................ 24 ................................................................................................ 4.1 Simulation Model 24

............................................................................................ 4.2 Results and Analysis 26

5 FPGA Implementation ............................................................................................. 29 5.1 Design .................................................................................................................. 29

5.1.1 Overview ...................................................................................................... 29 5.1.2 DSP Builder .................................................................................................. 30 5.1.3 Peak detection .............................................................................................. 31 5.1.4 FIRFilter ...................................................................................................... 32

................................................................................................................. 5.2 Testing 34 5.2.1 Development Board Testing ......................................................................... 34 5.2.2 Test Results .................................................................................................. 35

....................................................................................................... 5.3 Further Work 38

........................................................................................... 6 Algorithm Modification 40 ................................................................................................ 6.1 Combining Filters 40

........................................................................................................ 6.2 Soft clipping 42 .......................................................................................... 6.3 Multi-peak correction 42

7 Conclusion ................................................................................................................. 50

Bibliography ..................................................................................................................... 52

LIST OF FIGURES

Figure 1: The spreading effect on baseband data ................................................................. 4 Figure 2: Effects of spreading on transmitted bandwidth .................................................... 6 Figure 3: System overview of downlink signal creation ..................................................... 7 Figure 4: Illustration of Amplifier Output Back-Off in relation to Crest Factor ............... 11 Figure 5: System overview of downlink signal creation with Peak Windowing

.............................................................................................. block added in 12 Figure 6: Simple signal clipping in time domain ............................................................... 13

Figure 7: Clipped and Windowed signals in time domain ................................................. 16 Figure 8: High Level System Block Diagram of Windowing Algorithm .......................... 18 Figure 9: Functions c(n) and b(n) when windows are overlapping ................................... 20 Figure 10: Windowing filter with feedback structure for M-tap filter ............................... 23 Figure 11: CCDF Plot for WCDMA Single carrier test signal .......................................... 25

Figure 12: Spectrum of WCDMA Test Signal Used ......................................................... 25 Figure 13: Simulation results of WCDMA carrier after clipping for 2 filter

lengths . x(n) is filter input, y(n) is filter output ........................................... 28 Figure 14: Block diagram of algorithm implementation ................................................... 30 Figure 15: Block diagram of peak detection sub system for FPGA design ....................... 32

............................... Figure 16: Block diagram of FIR filter sub system for FPGA design 33 Figure 17: CCDF plot for captured data sets from FPGA compared against limited

input data set ................................................................................................. 37

Figure 18: Time domain plot for captured data sets from FPGA compared against input data ...................................................................................................... 38

........................................................ Figure 19: Filtering of multiple clipping coefficients 43

Figure 20: Block diagram of multi-peak correction system .............................................. 44 Figure 21: Multiple Peak Correction Structure for M-tap filter ........................................ 46

vii

LIST OF TABLES

Table 1 : WCDMA Test Signal Parameters ........................................................................ 24

Table 2: Simulation results for Peak Windowing Algorithm, clipping level for 7 dB PAR ........................................................................................................ 27

Table 3: Simulation results for Peak Windowing Algorithm, clipping level for 6.5 dB PAR ........................................................................................................ 27

Table 4: Simulation results for Peak Windowing Algorithm, clipping level for 5.9 dB PAR ....................................................................................................... -27

Table 5: Simulation results for Peak Windowing Algorithm, clipping level for 5.4 dB PAR ........................................................................................................ 28

Table 6: Analysis of measured FPGA output data compared to simulated data, 16,000 samples, filter length of 75 taps ....................................................... 37

Table 7: Windowing results for Combined Window Filters, clipping level for 7 dB PAR, 100,000 samples.. ......................................................................... .4 1

Table 8: Windowing results for Multi-peak correction, clipping level for 7 dB PAR ............................................................................................................. .47

Table 9: Windowing results for Multi-peak correction, clipping level for 6.5 dB PAR ............................................................................................................. -47



... V l l l

LIST OF ACRONYMS AND ABBREVIATIONS

AID

ACLR

CCDF

CF

CFR

D/A

dB

DS-WCDMA

DSP

E[ 1 EVM

FIR

FPGA

HIL

I

LUT

MHz

OBO

PAR

Q ROM

SF

SNR

VHDL

WCDMA

Analog-to-Digital

Adjacent Channel Leakage power Ratio

Complementary Cumulative Distribution Function

Crest Factor

Crest Factor Reduction

Digital-to-Analog

Decibels

Direct Sequence Wideband Code Division Multiple Access

Digital Signal Processing

Expected Value of

Error Vector Magnitude

Finite Input Response

Field Programmable Gate Array

Hardware-In-Loop

In-phase

Look-Up Table

Megahertz

Output back-off

Peak-to-Average Ratio

Quadrature

Read Only Memory

Spreading Factor

Signal-to-Noise Ratio

VHSIC (Very-High-speed Integrated Circuit) Hardware

Description Language

Wideband Code Division Multiple Access

1 INTRODUCTION

Wideband Code Division Multiple Access (WCDMA) is a direct-sequence spread

spectrum system, allowing multiple users to share the same radio channel. Each user's

signal is identified by a code which can encode and decode their signal from a shared

composite signal. Signals of multiple users are encoded with different codes before

summing together at the base station to create the downlink signal. Summing together

many signals will occasionally cause a wide range of amplitudes in the composite

downlink signal. As more signals are included in the composite signal, the amplitudes

vary to a higher degree. This wide range of amplitudes becomes Gaussian distributed,

leading to high Peak-to-Average Ratio (PAR) in the downlink signal.

A power amplifier is used in the final stage of transmitting the downlink signal,

and is performance limited by high PAR. Amplifiers work best in the linear range where

input signals stay within a bounded range. Large peaks in the input signal result in using

the non-linear region of the amplifier, which can cause adjacent channel leakage and low

power efficiency. Spectral distortions result from amplifier saturation, and the memory

effects in the amplifier slow down the decay of these distortions, worsening the affects.

Other undesirable side-effects from amplifier saturation include higher power

consumption and increased heat generation.

This project involves investigating published Crest Factor Reduction (CFR)

techniques to limit PAR and avoid amplifier saturation. Background information on the

WCDMA System is first provided to understand how a high Crest Factor occurs. Crest

Factor is one of the quality parameters used in describing WCDMA signals, and

additional parameters are also defined. CFR techniques are then introduced, with a

detailed look at the peak windowing algorithm to form the foundation for understanding

its benefits, and the areas in which it could be improved.

Simulations are performed on the selected windowing algorithm before

implementing it on a Field Programmable Gate Array (FPGA). To understand the project

for FPGA implementation, the tools and high level designs are explained. Final FGPA

results are compared with the Simulation results, and areas of design improvement are

noted. Finally, additional algorithm improvements are explored through simulation.

2 WCDMA SYSTEM

2.1 Overview of WCDMA system

Wideband Code Division Multiple Access (WCDMA) is a direct-sequence spread

spectrum system. Each user's signal is encoded and decoded with a unique code. Once

encoded, multiple users' signals can share the same radio channel. Each user's handset

can then recover, or decode, their own signal from that specific radio channel using the

same allocated code which originally encoded the user signal.

2.2 Spreading Code

The code used for encoding and decoding a user signal in WCDMA systems is

referred to as the spreading code. A spreading code is a binary sequence used to spread

the baseband data before transmission. The receiver can then recover the encoded signal

by correlating the spreading code with the data received the shared radio channel.

Spreading codes are of much higher bit rate than the baseband signal. Spreading is

simply just multiplication of the binary spreading code and the user information, also in

binary format. The higher bit rate of the spreading code increases bandwidth of the

signal.

Spreading Code

Resulting Spread Signal 0 0 1 1 lm

Bit 1

0

Bit L I

Figure 1: The spreading effect on baseband data

Base band Data

2.3 Direct Sequence Spread Spectrum System

A spread spectrum system is defined as using a bandwidth which is much larger

than the information bit rate. Also, the user information that was spread is then recovered

with the same signal used in the spreading. Spread spectrum systems can either be

frequency hopping or direct sequence. Frequency hopping involves spreading the signal

by a frequency pattern. Direct Sequence systems use a digital bit stream to spread

information, as used in Direct Sequence WCDMA systems, or DS-WCDMA.

1

The ratio between the transmission bandwidth (after spreading), and the

information bandwidth is called the spreading factor (SF),

where R, is the bit rate of the spreading code, and Rb is the information bit rate. The

processing gain resulting from spreading, G,, is equal to the spreading factor.

The effect of spreading on the transmission bandwidth is shown below in Figure

2. For de-spreading, the received signal is multiplied with the same spreading code. The

correlation between the received signal and the spreading code allows for recovery of the

information. Noise and interfering components from other users' signals are scrambled

during this process, but their energy is now uniformly distributed over the spreading

bandwidth.

The processing gain after de-spreading is expressed as

SNRcorr Gp = SNR, ,

where SNR,,, is the signal-to-noise ratio of the user signal after de-spreading, and SNRch

is the signal-to-noise ratio of the transmitted signal at the transmission band. This

processing gain makes WCDMA effective against noise and other coded signals.

Figure 2: Effects of spreading on transmitted bandwidth

In DS-WCDMA systems, the non-spread baseband signal contains both in-phase,

I, and quadrature, Q, components. Both I and Q signals for a single user are pulse

shaped, and then spread with the same spreading code. In the base station, the spread

signals for different users are then summed together to create the downlink signal. This

signal is pulse shaped, then up-converted to a higher carrier frequency before it can be

amplified for transmission. A system overview of the process is in Figure 3. Note that

the baseband user data is still a digital bit-stream.

System Overview of the Downlink Signal Process

Baseband Signal for user 1

Baseband Signal for user k

cos(wn)

I

I t ; 1 , , 3

k, I

Spread signals are summed, Spread each user signal Then split their I & Q, with a Spreading Code followed by Pulse Shaping

4

Up-convert signals lo a higher frequency carrier, Re-combine I & Q signals

Pulse I Shaping

Figure 3: System overview of downlink signal creation

Baseband 1r z - Split Signal for I & Q

J user 2 AL

Downlink Signal to Transmit

Summing multiple user signals is what causes peaks to occur. More user signals

could possibly create higher peaks. These peaks are of significantly higher power

compared to the average power, which then limit the performance of the amplifier as

explained in section 2.5.

Downlink

Transmit 1

The user signals are grouped together by a frequency channel or carrier, and each

carrier has a capacity limit for number of users. Carriers are adjacent to each other

spaced 5MHz apart. The composite signal for transmission includes multiple carriers as

they are all amplified and transmitted together. Just like with adding users onto a carrier,

as more carriers are included for transmission the PAR becomes larger, and therefore the

Pulse

I I I Q Q?

number of carriers is an important variable. For the purpose of this project, only a single

carrier case is considered.

2.4 Quality Parameters

2.4.1 Crest Factor

The crest factor (CF) is defined as the ratio of the peak power to the mean power

of the signal:

Crest Factor measures the peak-to-average ratio of the signal, how high the peaks in the

signal are. To measure how often the peaks occur, the Complementary Cumulative

Distribution Function (CCDF) of the signal is used. The CCDF describes the probability

of exceeding a particular signal level with respect to the average power.

2.4.2 Adjacent Power Leakage Ratio

The Adjacent Channel Leakage power Ratio (ACLR) is the ratio of the

transmitted power centered on the assigned channel frequency to the power after a

receiver filter centered on an adjacent channel. For WCDMA, the 3GPP technical

specifications [3] state a minimum allowable ACLR limits for first and second adjacent

channels. These limits are 45dB for a first adjacent channel (5MHz channel offset), and

50dB for a second adjacent channel (10MHz channel offset).

ACLR can be calculated by summing the power spectral density over the desired

frequency ranges

ACLR = lolog,, 3

where range B is for frequencies in the transmission channel, Badj is the range of

frequencies in the adjacent channel, and S, is the power spectral density of the received

signal. For this project, the upper adjacent band wilI be used in all references to the

ACLR calculation.

2.4.3 Error Vector Magnitude

The error vector magnitude (EVM) is a measure of signal degradation between

the input reference signal, r', and the transmitted version of the signal after clipping, z'.

The error vector, e, is defined as the difference in power between the 2 signals,

The error vector magnitude is the square rooted ratio of the mean error vector

power to the mean reference signaI power:

EVM is expressed as a percentage. A very small value for EVM indicates that the signal

under test is almost identical to the reference signal. For WCDMA, 3GPP have defined

maximum EVM limits as 12.5% for a 16QAM modulated signal, and 17.5% for a QPSK

modulated signal. [3]

2.4.4 Complementary Cumulative Distribution Function

The Complementary Cumulative Distribution Function (CCDF) is used to

describe the power characteristics of a signal with respect to the probability of

occurrence. The power levels are expressed in dB relative to average signal power,

therefore, a ratio of OdB occurs 50% of the time. The CCDF plot can be viewed as a

histogram for the peak to average ratio, or Crest Factor, of a signal.

2.5 Power Amplifier

A large crest factor in a WCDMA signal sets high linearity requirements for

power amplifier linearity. From amplifier characteristics, a non-linear transfer function is

known to cause decreased ACLR and increased EVM. The output of the amplifier is

where A is the maximum output of the amplifier, and g(x) is the amplifier transfer

function for input x. The function g(x) can be approximated by

Large peaks at the amplifier input limits the average output power to be much less

than the maximum saturated output power. This output power gap is a result of

accommodating the large peaks to stay within the linear region of the transfer function.

The output back-off (OBO) is the measurement of this power output difference,

When the power amplifier is assumed to be operating in the linear region, the

OBO becomes equal to the Crest Factor in Equation (3). In a real system, the amplifier

characteristic is not linear near the saturation point. Therefore, the assumption of OBO

equal to CF does not hold, but can be approximated as equal.

PowerOut

t Saturation point \

I I

Opwating point I I

Po werh

Figure 4: Illustration of Amplifier Output Back-Off in relation to Crest Factor

3 CREST FACTOR REDUCTION

3.1 Overview of CFR Techniques

The system overview to illustrate how peaks are formed was shown in Figure 3.

It was noted that the summing of the individual user signals is the cause for large PAR

after pulse shaping. The Crest Factor Reduction (CFR) techniques of interest would

operate after the pulse shaping, immediately after the large peaks are realized into an

analog signal. The system diagram in Figure 3 is now updated to include the CFR block

in Figure 5 below.

System Overview of Crest Factor Reduction for the downlink signal



Pulse

Split 1:Q 1

Pulse

Downlink Signal to Transmit

I

$ sin(wn) I

I I ",

I \

Crest Factor Reduction uses the individual I & Up-convert signals to a

I Spread signals are summed, Q pulse shaped signals higher frequency camer, Spread each user signal Then split their I & Q, Re-combine I & Q signals with a Spreading Code followed by Pulse Shaping

Figure 5: System overview of downlink signal creation with Peak Windowing block added in

3.1.1 Clipping

Basic hard clipping involves saturating the signal at the set clipping level. It is a

simple technique. But this abrupt clipping creates sharp comers in the signal and

increases of high out-of-band emissions as shown in Figure 6.

Input Signal

L

Sample Number

Figure 6: Simple signal clipping in time domain

3.1.2 Coding

The properties of the composite downlink WCDMA signal can be greatly changed

by the set of spreading codes used for each user. Large peaks in the composite envelope

are due to the constructive contributions during summing of each signal after spreading.

Spreading codes greatly influence how high of a peak can occur. The set of unused codes

by the base station can be utilized to create an additional spread dummy-user signal. The

additional signal can be set in such a way to create destructive contributions to the

composite signal at the large peak points. This method of CF reduction by coding limits

the large peaks with no additional out-of-band reduction. However, this method has a

high degree of complexity and system modification. CFR by Coding cannot be reduced

to a single block technique, as was shown in Figure 5. For these reasons, this CFR

technique was not investigated any further.

3.1.3 Peak Windowing

Peak windowing [I] builds on the idea of basic clipping by smoothing the sharp

comers from hard clipping. This is accomplished by multiplying the signal in the region

of the peak with a windowing function. The smoothening increases the ACLR of the

hard clipped signal while maintaining the peak limiting. This method has shown good

results with minimum complexity. The windowing algorithm is explored further in

section 3.2.

3.1.4 Adaptive Clipping

An adaptive clipping method [7] was published that uses hard clipping combined

with a bandpass filter for smoothening. The clipping level is adjusted based on the output

of the filtering operation. But there is peak power regeneration from the bandpass

filtering, requiring that the process be repeated again until a desired peak level is reached.

Its multistage operation with clipping level control through feedback greatly increases

system complexity, making the system undesirable to implement.

3.1.5 CFR Engine

Analog Devices published a paper on a Crest Factor Reduction Engine [5] . This

engine uses peak limiting, peak estimation & compensation block, and an error vector

estimator. An error vector is added back to the transmitted signals to compensate for

signal peaks. However, they admit that elimination of peaks may not be perfect because

the subtracted error vector is smeared over the length of the pulse shaping filter,

potentially causing other peaks to occur in other regions of the signal. The solution is of

high complexity with very few details revealed. But it should be noted that even with this

technique the peak limiting suffers from peak re-growth.

3.2 Windowing Algorithm

3.2.1 System Overview

Basic hard clipping of a signal will achieve limiting the signal power to a specific

peak power, with minimum effect on EVM. Sharp comers resulting from the hard

clipping cause the undesired out-of-band radiations. These sharp comers are smoothed

by windowing as shown in Figure 7. It can be noticed in the diagram that in order to

smoothen out the sharp corners many samples both before and after the clipped region are

also affected. The number of additional samples windowed is related to the window

length. It follows that the longer the windows result in smoother output signals and

improve ACLR. At the same time increasing window length further increases the gap

between the input and windowed signals and worsens EVM, as seen in the figure below.

Input Signal Clipped Signal

Clipping Point - - - - - - - - - _ _ _ _ - - - - - J - - . . - - - - - _ - - - - - _ _ _ _ _ _ _ ;-.-.

i i. I

I" I ;i\ Windowed

j - Signal ,fly 0

9 I P P ". t . 0, j i i. j? i ? ! s " ? I i ! I 1

\ i 8.

i 6 ! i b i ' ; ! i i r 1 i ? i 5 P 8, 8' ", ? i 'd ! 8 s' !

I i i 8% i \, 8" 8. '*-,d ! i

y L'

Sample Number

Figure 7: Clipped and Windowed signals in time domain

The windowing operation must follow the clipping. And it is desired to have the

windowing limited to clipped regions only and not the entire input signal. A simple

linear process of clipping followed by windowing does not satisfy this requirement. A

more effective method is to extract the weighting coefficients that will clip the input

signal, and then window those coefficients. The windowing can be limited to the peak

regions, indicated by the clipping coefficients. A system diagram for this algorithm is

illustrated in Figure 8.

The windowing coefficients can be of any window such as Gauss, Kaiser,

Hanning and Hamming. Previous work [2] has shown that Hamming and Hanning

windows have a more suitable spectrum for reducing out-of-band emissions, and the

Hamming window showing best results overall. Therefore, a Hamming window is used

with this algorithm in this project.

High Level System Block

Baseband Input Signal I

Peak Detection

Diagram for Windowing - - - - - - - - - Algorithm . - - - - - - - - - - -

1 Clipping Coefficients, c(n) I

Value of 1 w~ll not change mgnd

j These coefficients , will Iimtt signal to : clippmg level I

, I . . -------I---- J

, I

; i Windowed Clipping I

I , , ; Coefficients, b(n) L I

I I

6 I

I

I

I

I

I

- I

I

I

I

I

Baseband Output Signal

Figure 8: High Level System Block Diagram of Windowing Algorithm

3.2.2 Algorithm Details

Basic hard clipping can be expressed as

y(n>=c(n>x(n>, (10)

where x(n) is the signal to be clipped, y(n) is the signal after clipping, and c(n) are

the clipping coefficients. For hard clipping, c(n) expands to

with A being the clipping level. Clipping limits y(n) to a maximum value of A,

and this method creates the signal with sharp edges and high out-of-band radiation. The

windowing will replace the clipping coefficients c(n) with b(n), where

w(n) is the windowing function, and a k is a weighting coefficient. This is

basically a convolution of the windowing function and the weighting coefficients, then

subtracted from 1 . This convolution can be implemented in a Finite Input Response

(FIR) filter.

To maintain a maximum allowed amplitude of A, b(n) cannot be greater than c(n).

That is, the following inequality

must be satisfied for all n. The higher the coefficient values, the closer the

clipped signal is to the original signal, x(n). To minimize EVM, the above inequality

must be as near equality as possible. The window length, W, and the coefficients, ak,

determine how close b(n) is to c(n). If clipping probability and window length are low

such that the windows do not overlap in time, then an easy way to create b(n) is to set ak

equal to c(n). If the windows do overlap, then the convolution result is generally larger,

causing b(n) to be lower, and resulting in more attenuation than needed for the

windowing operation of x(n). In certain cases b(n) may become negative, indicating that

a form of control on the convolution output is needed. A good illustration of the

overlapping window case is found in [2] has been included here as Figure 9. The lower

than desired final b(n) values are quite visible.

Figure 9: Functions c(n) and b(n) when windows are overlapping

A feedback structure was introduced in [I] to scale the input values to the FIR

filter. The resulting output coefficients have a synchronization delay with the input

signal containing peaks. This delay is equal to the time required for an input value to

reach the center tap of the filter. At this point the center filter tap is equal to unity,

meaning it could result in 1-b(n) equaling 1-c(n). But the filter output will be larger than

1-c(n) due to the contributions of adjacent filter taps when clipping spans several

samples. A much smaller value of b(n) results usually due to peaks wider than a single

sample. In this case, the result drives inequality (13) further away from equality and

increases EVM.

The feedback path recognizes that these adjacent values in the filter can be used to

adjust the next filter input value. Looking forward to when the next input value reaches

the center tap, the contribution of all previous input values (currently sitting between lst

and center taps) can be calculated for this future situation. Once this contribution is

known in advance, it can be used to correct that incoming next input value. When the

incoming input value reaches the center of the filter, there is a unity weighted tap and the

output contributions from all previous values still in the filter have already been

compensated for. The resulting output is the input value before it received correction

from the feedback structure (assuming the filter output receives no contribution from taps

between the first and center taps). The windowing filter with the described feedback path

is shown in Figure 10 as the expanded version of the Windowing sub-system in Figure 8.

The filter taps have been shaded to easier identify the feedback filtering to the window

filtering.

The feedback structure not only perfectly corrects any new input values to the

filter based on previous values, but it also scales down all additional input values to keep

filter output at a controlled level. This has been a problem in previous windowing

methods where the filter output grows and extra complex output control is required to

adaptively scale the result.

4 SIMULATIONS

4.1 Simulation Model

A generated WCDMA carrier is used in Matlab simulations of the CFR algorithm.

The data is for a single carrier only and signal parameters are listed below in Table 1.

Table 1: WCDMA Test Signal Parameters

I Number of Carriers I I I I Number of Samples 1 100,000 1 I Sampling Rate 138.4 MHz I I Crest Factor 110 .56d~ I

--

/ ACLR (Upper 1 st adjacent channel) 1 64.58 dB I I ACLR (Lower 1" adjacent channel) 1 65.47 dB

The signal CCDF is shown below in

Figure 11. The lack of smoothness at high CF values is due to a limited sample

size. The spectral properties of the test signal can be viewed in Figure 12, note the 5MHz

signal bandwidth at the center, this is the assigned channel in baseband.

CCDF for Single Carrier WCDMA signal, 100,000 samples

Crest Factor (dB)

Figure 11: CCDF Plot for WCDMA Single carrier test signal

Spectrum of WCDMA Test Signal

-100'- -20 -15 -10 -5 0 5 10 15 20

Frequency (MHz)

Figure 12: Spectrum of WCDMA Test Signal Used

4.2 Results and Analysis

The clipping algorithm can be simulated in Matlab or Simulink environment. The

basic results are tabulated in Table 2 to Table 5 for a set clipping level as window length

is varied. It is known that continually reducing PAR will eventually increase EVM and

reduce ACLR past specified values [2]. The tabulated data is formatted to show effects

of varying filter size for a specific PAR reduction.

As the filter length is decreased from a length of 75 presented in [I], the lower CF

and EVM values are an improvement, but the decline in ACLR values indicate signal

quality deterioration. It is visible that the shorter clipping regions account for the smaller

EVM, but do not provide enough smoothening of the clipping to maintain desired ACLR.

Longer filters suffer in EVM due to peaks in close succession where the windowing of

each peak overlaps, causing the region between the peaks to be further changed than

expected. This explanation is illustrated with the windowing results for 2 different

window lengths in Figure 13.

Table 2: Simulation results for Peak Windowing Algorithm, clipping level for 7 dB PAR

Table 3: Simulation results for Peak Windowing Algorithm, clipping level for 6.5 dB PAR



Figure 13: Simulation results of WCDMA carrier after clipping for 2 filter lengths. x(n) is filter input, y(n) is filter output

5 FPGA IMPLEMENTATION

5.1 Design

5.11 Overview

The target hardware for implementing the windowing algorithm is an Altera

Stratix FPGA. The Stratix family of FPGAs is aimed for DSP applications, with design

tools in Simulink to aid simulation and hardware development. Altera advertises a Crest

Factor Reduction scheme optimized using their DSP targeted FPGAs such as Stratix [4].

The algorithm shown by Altera is the Peak Windowing method [ I ] discussed earlier.

However, when approached, Altera could not provide a reference design. The advanced

optimization techniques presented by Altera cannot easily be implemented without the

reference design.

The Stratix EPlSSO DSP development board was used for this project. The board

had on-board Analog-to-Digital (AD) and Digital-to-Analog (DIA) converters, which

allows for connection and testing with lab equipment. Advantages of using the board

include debugging tools such as hardware-in-loop simulation used for accelerating

simulations, and signal tap analysis as a built-in logic analyzer. To simulate I & Q data

as received from digital sources, the vector data was to be stored in a look-up table

(LUT). Since the LUT only requires memory blocks in the FPGA, which are otherwise

unused and available with this design, there is almost no impact to the design and

performance.

The FPGA can accept the I & Q input signals of the WCDMA signal, and will

result in filtered I & Q output signals. Input resolution is 12-bit signed and the output is

14-bit unsigned, as dictated by the development board AID and D/A converters. The

main system is broken down into peak detection and coefficient filtering as shown in

Figure 14. The FIR filter was implemented with a length of 75 taps, as was presented in

111.

Figure 14: Block diagram of algorithm implementation

x(n)= I +jQ

1

Q

The final compiled design had low resource usage with most items like Logic

Element usage, DSP blocks, and Logic Array Blocks (LAB) all below 20%. The selected

device can handle a larger design or provide additional functionality if timing

requirements allow.

5.1.2 DSP Builder

DSP Builder is a block-based design tool. The tool resides in the Simulink

environment of Matlab. A library of functional blocks is available for bit and bus

functions, as well as development board functionality. Each block is translated by DSP

-+ 4

-----+ C(n)

Peak Detection

FIR b(n)

Builder into a VHDL model that is ready for synthesis and FPGA fitting. The benefits of

DSP Builder include the fast design time from drag and drop functionality, use of sub-

systems designs, and quick functional simulation inherited from Simulink. However,

there have been minor problems observed with the tool in simulations and in the

conversion of the design to VHDL. The observed issues have included working with *

bus-widths, creation of look-up tables, and delay estimates for specific blocks.

5.1.3 Peak detection

The first stage and sub-system of the algorithm is peak detection for calculating

the hard clipping coefficients c(n). First it calculates the complex envelope, x(n), using

the conventional square, add, and square root operations. Each input vector is squared

and summed using the Multiply Add block, and then a Square Root block completes the

operation. The implementation requires that the square root of a fairly large integer be

taken.

An additional signed 12 bit input is used as the clipping amplitude, A, which is

compared with the complex amplitude, x(n), to determine the value of clipping

coefficient c(n). Once a sample is identified to require clipping, it has to be divided into

A to provide c(n). Division operations are usually iterative, resulting in unknown timing

delays and complicating design further. In this design however, we know our input is

already bounded in range and therefore affords the use of a look-up table to perform

lllx(n)l, with the result then multiplied with A. The subsystem is diagrammed below in

Figure 15.

Multiply and Add Block

I2 + 02

Input Data Q I Block

Comparator Block Mux Select

Clipping value, A

Figure 15: Block diagram of peak detection sub system for FPGA design

5.1.4 FIR Filter

The FIR filter consists of a feedback structure which adds the timing requirement

of computing the feedback before the next filter input sample is received. The received

c(n) is first subtracted from 1, with the result then corrected by the feedback loop. The

feedback corrected value has a lower saturation point of 0, and is then passed into the FIR

structure as the next sample. This is diagrammed in Figure 16. The FIR structure

consists of multiple levels of sub-systems that implement the shift register and multipliers

for both forward and feedback paths. Large adder trees complete the filtering stage.

Block FIR Filter 75 tap window

FIR Filter 37 tap half window

Figure 16: Block diagram of FIR filter sub system for FPGA design

The filter values are kept as 13 bit signed numbers wherever possible, 1 extra bit

of resolution compared to the I & Q input vectors. A suitable balance of accuracy and

timing delays are found with the selected filter resolution. However, the filter

coefficients were implemented as 16 bit numbers for accurate representation. It is after

the multiplication that the width of the result is reduced back down to 13 bits to keep the

adder tree structure optimized.

According to the Altera DSP guide [S], the multipliers can also be further

optimized by removing the shift registers for the filter samples and replacing them with a

long series of simple delay blocks. This optimization would be realized at the fitting

stage, but it is not significant when operating at the development board speed. The gains

of the multiplier optimization are minor and could be utilized when operating at higher

clock speeds.

5.2 Testing

5.2.1 Development Board Testing

The development board offers 2 forms of testing, Hardware-In-Loop (HIL)

Simulation and SignalTap Logic Analyzer. The HIL simulations offer a Hardware

implemented extension of the design to provide faster Simulink simulations. The faster

simulations are beneficial for any blocks implemented as a custom VHDL black box

system, and also for simulating the design with a large input data set. The HIL did not

help in this project, but will be useful in any future optimization work on this design.

The embedded SignalTap Logic Analyzer allows setting probes on any data line

in the top level DSP Builder design. Probing occurs during operation on hardware, and is

controlled through the development board and DSP Builder in Simulink. The controls

include setting trigger conditions and downloading the captured probe data back into

Simulink. Each probe has a memory limit on how much data can be captured on every

trigger. Using this tool many problems were found in the original design when running at

the development board fixed clock speed of 80MHz. Examples include:

The LUT sometimes provided random data on the output. The problem

occurred rarely, but the cause was found to be a hardware limitation for

data set size where the LUT has to be replaced with a ROM block. The

LUT data was then created in Intel hex file format and linked to the ROM.

The Square Root function was not always accurate or it produced spikes in

the output. This is due to not being able to handle such a large integer

input at the operating speed. Again this was a rarely occurring problem

but its affects were severe. Dividing the development board clock by 2

allowed an accurate output every time.

The timing requirements for feedback loop would not hold. The setup

time for feedback correction is not met. However, dividing the

development board clock speed for the square root problem also solved

this issue.

The SignalTap Logic Analyzer was valuable in development and was also used in

collecting output data to evaluate the design. In addition to checking the output data

captured from the FPGA, the D/A output was also tested in the lab with a Spectrum

Analyzer. The output signal bandwidth was found to be correct, and the CCDF plot

resembled that for simulations.

5.2.2 Test Results

The output data sent from the FPGA tothe D/A is captured using SignalTap

analysis and used for analysis of results. Due to the limited memory the SignalTap

probes are able to use, only 16,000 samples were used for analysis over 3 different

clipping levels. The results are tabulated below in

Table 6. Captured data sets are compared with the limited input data with a CCDF plot in

Figure 17 and a time domain snapshot in Figure 18. The CCDF plots are close to

expected results, and similarly with the time domain plot.

Immediate observations from the tabulated data include a higher than expected

resulting Crest Factor, higher than expected resulting ACLR (except for 1 case), and a

lower measured EVM. All of the differences were minor. The reason for the differences

relate to the measured signal being clipped at a slightly higher power level than in the

simulation, which explains the higher CF. Also, there was less clipping taking place,

meaning the output signal has a smaller error relative to the input, compared with the

simulation, and this explains the lower EVM and higher ACLR. A time domain plot to

compare the measured and simulated output data shows they are almost the same, so to

measure how different they really are the EVM for the measured data referenced to the

simulated data is calculated. EVM values are small for the measured data compared to

simulated data.

It should be noted that the low number of samples used are not enough to

characterize the actual algorithm, but they do indicate how close the FPGA output data is

to the simulated output data.

Table 6: Analysis of measured FPGA output data compared to simulated data, 16,000 samples, filter length of 75 taps

1 EVM from Simulation (o/o) I 5.216 1 10.003 1 13.696 1

Data Set 1

CF as used in Simulation (dB)

CF measured from FPGA for same clipping factor (dB)

I EVM measured from FPGA output (%) I 5.180 1 9.961 1 13.631 1

Data Set 2 / Data Set 3 / 7.001

7.053

CCDF for FPGA output, 16,000 samples

. . .

EVM between FPGA output and Simulation ( O h )

I I I , I 1 I I 1 I I I I 1 I I

0 1 2 3 4 5 6 7 8 9 10 Crest Factor (dB)

5.927

6.043

Figure 17: CCDF plot for captured data sets from FPGA compared against limited input data set

5.445

5.597

0.214

I

0.328 0.426

6900 6920 6940 6960 6980 7000 7020 7040 7060 7080 Sample Number

Figure 18: Time domain plot for captured data sets from FPGA compared against input data

5.3 Further Work

One area for improving this design is to further improve the accuracy of the

output data so that it is better matches the simulations. A higher bit resolution should fix

this and keep the clipping to be exact and avoid the slight change in measured clipping

level currently observed. Additionally, a PC script could be used to generate the

necessary VHDL for the FIR filter with feedback, allowing the whole FIR block to be a

black box in DSP builder. This process could mean faster experimenting with different

filter accuracies compared to changing each tap individually at the block based design

level.

General time delay improvements can also be made. One area for a delay

improved is the calculation of the complex envelope. Envelope calculation can be

improved with Altera's CORDIC function which is advertised to translate Cartesian to

Polar coordinates at speeds up to 300MHz (based on minimum bit resolution of input

signal). The function requires an additional license, however, the general concept behind

the function is published and available. A version of the CORDIC algorithm is not

publicly available in VHDL and would require a useable design to be created or

purchased.

6 ALGORITHM MODIFICATION

As the issues limiting the windowing technique to improve are identified,

modifications to the algorithm can be explored in an effort to improve results. Three

ideas are explained here.

6.1 Combining Filters

Combining filters involves switching between 2 different windowing operations

to achieve better results. Earlier in section 4.2 for simulation results, it was noted that

longer window lengths maintain good ACLR values but suffer from overlapping peaks.

It is the reverse case for shorter window lengths which can mostly avoid overlapping

windowing but lack the smoothness to maintain ACLR The suggested algorithm

modification is to use the long filter but switch to shorter filters when it is known

multiple peaks in close succession are approaching. This way the longer filter is used the

majority of the time for good ACLR, and the shorter filter is occasionally used to

minimize the significant overlapping effects on EVM. A short summary of results for a

single clipping value using combined windows is tabulated in Table 7.

Table 7: Windowing results for Combined Window Filters, clipping level for 7 dB PAR, 100,000 samples

For any given value of ACLR in the dual-window results, a longer filter with

similar CF, similar ACLR and lower EVM can be found in the single filter case. A better

ACLR - EVM pairing can always be found in the single filter case. This pattern

continues throughout the rest of the raw data for various clipping levels. Combined

windowing does not provide any benefit in its most simple form, but these results are still

interesting.

A 75-tap filter was used the majority of the time in the combined case, and the

EVM results with the dual filter do become lower in comparison to the single 75-tap filter

case. But the results indicate that the ACLR is significantly lowered by occasionally

switching to a shorter window. Even using the shorter window rarely causes more

damage to the ACLR than it helps EVM. This method was no longer pursued.

6.2 Soft clipping

Soft clipping involves continually adjusting the clipping value for successive

samples until no more samples are higher than this clipping level. The idea behind soft

clipping is based on the fact that successive samples requiring clipping will already

receive more clipping than needed from the windowing. If the initial level of clipping for

each consecutive sample is reduced, then the extra attenuation produced in the

windowing can be avoided.

This new algorithm did not work, the results were extremely poor with not

enough clipping provided. Having both soft clipping and the filter feedback structure

doubles the efforts in reducing level of clipping provided to consecutive peak samples,

resulting in a much lower than expected affect on the final result. Both soft clipping and

the feedback filter are designed to have similar effects on the coefficient samples fed into

the windowing filter. The main difference between the 2 is that feedback filter structure

can better control the filter output, which can otherwise grow as found in other CFR

techniques. The feedback structure also provides a more precise form of correction to the

coefficients since it exactly calculates the affect of previous peak samples, whereas the

soft clipping would be using a generic function to successively lower the clipping

amount. Soft clipping is unsuitable to add into the windowing with feedback algorithm.

6.3 Multi-peak correction

In section 3.2.2 it was explained how the feedback structure helps the windowing

function. This can be better realized with the plot in Figure 19 where the input to the

filter, 1 -c(n), with the filter output. Here we see a good windowing for a single peak first,

followed by a multi-peak case. The result for the 2nd peak of the multi-peak is closer to

the single peak case because of the feedback loop. The feedback loop has corrected for

the 1" peak. But the 1" peak receives no correction for the 2nd peak which arrives later.

Addressing this issue with another correction loop is the basis for this version of

modifying the peak windowing algorithm.

Result of Windom'na Filter Output, 1-b(nj'

Filter Input, Ic (n ) .

Gap due to 2nd peak entering fllter will result

in extra attenuation and increase EVM \

, . i i , . ; 9

6350 6400 6450 Sample Number

The 2nd peak into the Filter has less growth in

output due to the feedback correction for the 1st peak

/

Figure 19: Filtering of multiple clipping coefficients

Adding a structure similar to the feedback loop could provide a corrective factor

when peaks are close together. A calculation of the later peak's contribution to the

windowing of the first peak is needed. Then a fraction of that contribution can be used to

correct the earlier peak's clipping coefficients. A fraction is used because the filter

feedback will provide further correction to the filter input values, and a smooth transition

into and out-of using this correction is required to maintain the smooth output pulse shape

for reducing out-of-band emissions. The system level diagram of this structure is

diagrammed below in Figure 20.

Clipping coefficients, c(n), from Peak Detection System

Calculation Correction of later peak operation contribution

Figure 20: Block diagram of multi-peak correction system

Windowed Clipping

Coefficients, bh)

For the filter feedback, it was shown in Figure 10 that the 2nd-half of the

windowing coefficients were used with the lst-half of the filter inputs. A good starting

point for this structure is to use the lst-half of the windowing coefficients as the objective

is to correct for newer peaks. Looking back at Figure 19 for the multi-peak windowing

case, as the earlier peak's clipping coefficients reach the center of the windowing filter,

the later peak's coefficients enter the lSt-half of the windowing filter and create the noted

extra gap between the output and the first input peak.

Windowing Filter with Feedback structure

Delay to allow later peaks to be

detected

Using all the half-window taps may not be required since they are using samples

related to the same peak as the sample being corrected by this structure. It may also

cause an abrupt change in the level of correction to be provided, a concern for

maintaining a smooth series of values reducing out-of-band emissions. Therefore the

number of taps removed, starting with the taps closest to the center, is defined as R, and is

varied in simulations. The fraction for correction is defined as a, and is also varied in

L r * A L -

simulations. The structure used for simulations is shown in Figure 21, and the results are

tabulated in Table 8 to Table 1 1.

Figure 21: Multiple Peak Correction Structure for M-tap filter

46

Table 8: Windowing results for Multi-peak correction, clipping level for 7 dB PAR

Table 9: Windowing results for Multi-peak correction, clipping level for 6.5 dB PAR

Crest Factor (dB)

6.458

6.445

6.436

6.422

6.408

Crest Factor (dB)

7.003

6.999

6.990

6.985

6.981

Results Compared to Original Windowing Algorithm

Window Length (Taps)

75

67

59

5 1

43

Modified Peak Windowing Algorithm

EVM (%)

3.90

3.80

3.70

3.57

3.43



75

A EVM (%)

-0.03

-0.02

-0.01

-0.01

-0.02

A ACLR (dB)

0

0.05

0

0

0.01

EVM (%)

5.85

Taps Removed

10

3

8

8

2

ACLR (dB)

64.1 2

64.03

64.00

63.24

61.14

Correction Scaling

0.25

0.25

0.1 5

0.25

0.25

ACLR (dB)

63.62

Correction Scaling

0.05

Taps Removed

10

A EVM (%)

-0.02

A ACLR (dB)

0.01



Crest Factor (dB)

5.432

5.397

Crest Factor (dB)

5.925

5.906

5.883

5.864

5.846 -

I Modified Peak Windowing Algorithm


75

67

59

51

43


Modified Peak Windowing Algorithm

EVM (%)

8.54

8.31

8.07

7.88

7.62


Compared to the original windowing structure with feedback sharing the same

number of taps, the results show slight improvements. The improvements are mainly in

EVM, with occasional improvement in ACLR. As the level of clipping increases (lower

CF), the gains of this structure are more noticeable. It is also shown that there is

generally more affect on longer window lengths, which are more likely to have multiple

peaks windowed together. Although the gains are not significant, they do indicate the

A EVM (%)

-0.09

-0.09

-0.09

-0.01

-0.01


75

ACLR (dB)

62.78

62.69

62.44

60.67

56.90

A ACLR (dB)

0.01

0.01

0

0

0

EVM (%)

12.18

Correction Scaling

0.25

0.25

0.15

0.15

0.1 5

Taps Removed

16

14

9

15

15

ACLR (dB)

61.58

Correction Scaling

0.15

Taps Removed

15

A EVM (%)

-0.19

A ACLR (dB)

0.03

general concept is on the right path and could realize better performance gains with

further exploration. Possible exploration could involve a slightly more sophisticated

approach for the multi-peak correction block. This multi-peak correction block is the

best improvement option compared to combining windowing filters and soft clipping.

7 CONCLUSION

Crest Factor Reduction is a major concern for wireless network equipment

vendors due to the power amplifier performance limitations imposed by high peak-to-

average (PAR) ratio. The performance limitations result in expensive equipment and

large power bills to operate the base stations. Finding a way to lower the PAR can result

in an improvement in amplifier efficiency and reduced costs, a topic that large companies

including Analog Devices [5] and Lucent Technologies [6] are actively pursuing.

This project has presented the Peak Windowing algorithm [I] for Crest Factor

Reduction. A detailed description has shown the algorithm to be effective at clipping

peaks that are spaced apart in time, but had performance issues when multiple peaks fell

into the windowing period. This was verified with simulation results where windowing

lengths were varied for various levels of clipping and measured using EVM and ACLR.

The algorithm was then implemented onto an FPGA. The FPGA results closely

followed that from simulations with minor differences. A limited accuracy implemented

in the hardware had caused a small reduction in the amount clipping achieved. This can

be fixed though. For the selected FPGA, the resource usage with the final design was

very low, allowing further possible expansion of the design if desired. Accuracy and

speed improvements for the FPGA design were also noted, with improvements to

accuracy coming from more experimentation with the design. The speed can also be

increased by implementing, or purchasing, pre-defined algorithms to accelerate envelope

calculation. The envelope calculation is one of the major gating factors for operating

speed.

Improvement ideas were also presented. Combining different multiple

windowing filters was proposed to take advantage of the shorter window's strength in

minimizing EVM and the longer window's ability to maintain high ACLR. The results

showed the opposite case where the shorter window pulled ACLR lower and could not

improve EVM significantly. Soft clipping was also explored to adaptively change

clipping level and minimize EVM, but yielded extremely poor results due to

incompatibility with the feedback structure of the peak windowing algorithm.

Finally, an additional multi-peak correction structure was added before the peak

windowing system. The idea is to correct for peaks appearing later in time, resembling

how the feedback structure of the peak windowing corrects for peaks previous in time.

This modification builds upon the strength of the current peak windowing algorithm and

aims to improve its weakness area. Results for this modification showed only slight

improvement, but it is an indication that improvements are possible. The multi-peak

correction algorithm should be further investigated, with more attention paid to how and

when the calculated correction is applied. Advancing and experimenting with the

correction system could eventually yield an algorithm much more effective than the peak

windowing algorithm on which it is based.

BIBLIOGRAPHY

[ I ] 0 . Vaananen, J. Vankka, and K. Halonen, Effect of Clipping in Wideband CDMA System and Simple Algorithm for Peak Windowing, Helsinki University of Technology, 2002.

[2] 0 . Vaananen, Clipping in Wideband CDMA Base Station Transmitter, Master's Thesis, Helsinki University of Technology, 2001.

[3] 3GPP, Base station conformance testing, TS 25.141

[4] Altera, Crest Factor Reduction, http://www.altera.com/end- markets/wireless/advanced-dsplcfrlwir-cfrhtl , Wireless End Market

[5] K. Yadavelli, D. Efstathlon, M. Manglani, Crest Factor Reduction Engine for Multi- carrier WCDMA Transmitted Signals, Analog Devices Inc., 2004

[6] R. van Nee, A. de Wild, Reducing the Peak-to-Average Power Ratio of OFDM, Lucent Technologies Bell Labs, 1998.

[7] T. Fujii and M. Nakagawa, Adaptive Clipping Level Control for OFDM Peak Power Reduction Using Clipping and Filtering, IEICE Trans. Fundamentals, Vol. E85-A, No.7, July 2002.

[8] Altera, Implementing High Perjhormance DSP Functions in Stratix & Stratix GX Devices, vl.1 September 2004. Stratix Device Handbook, Chapter 7, Section IV, Volume 2. http://www.altera.com/literature/1it-stx-jsp

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