*UNIT 3CIRCUIT DESIGN PROCESS

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*Stick DiagramsObjectives:To know what is meant by stick diagram.To understand the capabilities and limitations of stick diagram.To learn how to draw stick diagrams for a given MOS circuit.

Outcome:At the end of this module the students will be able draw the stick diagram for simple MOS circuits.Stick Diagrams

*Stick DiagramsN+N+Stick Diagrams

*Stick Diagrams

Stick DiagramStick Diagrams

*Stick DiagramsStick Diagrams

*Stick DiagramsVLSI design aims to translate circuit concepts onto silicon.stick diagrams are a means of capturing topography and layer information using simple diagrams.Stick diagrams convey layer information through colour codes (or monochrome encoding).Acts as an interface between symbolic circuit and the actual layout.Stick Diagrams

*Stick Diagrams

Does show all components/vias.It shows relative placement of components.Goes one step closer to the layoutHelps plan the layout and routingA stick diagram is a cartoon of a layout.Stick Diagrams

*Stick Diagrams

Does not show Exact placement of componentsTransistor sizesWire lengths, wire widths, tub boundaries.Any other low level details such as parasitics..Stick Diagrams

*Stick Diagrams Notations Metal 1 polyndiffpdiffStick DiagramsSimilarly for contacts, via, tub etc..

*Stick Diagrams Some rulesRule 1. When two or more sticks of the same type cross or touch each other that represents electrical contact. Stick Diagrams

*Stick Diagrams Some rulesRule 2.When two or more sticks of different type cross or touch each other there is no electrical contact. (If electrical contact is needed we have to show the connection explicitly).Stick Diagrams

*Stick Diagrams Some rulesRule 3. When a poly crosses diffusion it represents a transistor.Note: If a contact is shown then it is not a transistor.Stick Diagrams

*Stick Diagrams Some rulesRule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff. All pMOS must lie on one side of the line and all nMOS will have to be on the other side.Stick Diagrams

*How to draw Stick DiagramsStick Diagrams

*Stick Diagrams

*PowerGroundBCOutAStick Diagrams

Cross-Section of CMOS Technology

Design RulesInterface between designer and process engineerGuidelines for constructing process masksUnit dimension: Minimum line widthscalable design rules: lambda parameterabsolute dimensions (micron rules)

CMOS Process Layers

Intra-Layer Design RulesMetal243

Transistor Layout

Vias and Contacts

Select Layer

CMOS Inverter Layout

ScalingVLSI technology is constantly evolving towards smaller line widthsReduced feature size generally leads to better / faster performanceMore gate / chipMore accurate description of modern technology is ULSI (ultra large scale integration

Scaling FactorsIn our discussions we will consider 2 scaling factors, and 1/ is the scaling factor for VDD and oxide thickness D1/ is scaling factor for all other linear dimensionsWe will assume electric field is kept constant

Scaling Factors for Device Parameters Simple derivations showing the effects of scaling are derived in Pucknell and Eshraghian pages 125 - 129It is important that you understand how the following parameters are effected by scalingGate AreaGate Capacitance per unit areaGate CapacitanceCharge in ChannelChannel ResistanceTransistor DelayMaximum Operating FrequencyTransistor CurrentSwitching EnergyPower Dissipation Per Gate (Static and Dynamic)Power Dissipation Per Unit AreaPower - Speed Product

Scaling of InterconnectsResistance of track R ~ L / wtR (scaled) ~ (L / ) / ( (w/ )* (t /))R(scaled) = Rtherefore resistance increases with scalingtwLAB

Scaling - Time ConstantTime constant of track connected to gate, T = R * CgT(scaled) = R * ( / 2) *Cg = ( / ) *R*CgLet = , therefore T is unscaled!Therefore delays in tracks dont reduce with scalingTherefore as tracks get proportionately larger, effect gets worseCross talk between connections gets worse because of reduced spacing