IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF...

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 3, MARCH 2018 517

Accelerated and Reliable Analog Circuits YieldAnalysis Using SMT Solving Techniques

Ons Lahiouel, Student Member, IEEE, Mohamed H. Zaki, Member, IEEE,and Sofiène Tahar, Senior Member, IEEE

Abstract—Existing yield analysis methods are computationallyexpensive and generally encounter challenges with high-dimensional process parameters space. In this paper, we proposea new method for accelerated and reliable computation of para-metric yield that combines the advantages of sparse regressionand satisfiability modulo theory (SMT) solving techniques, andavoids issues in both. The key idea is to characterize the fail-ure regions as a collection of hyperrectangles in the parametersspace. Toward this goal, the method constructs sparse polynomialmodels based on adaptive least absolute shrinkage and selectionoperator to find low degree approximations of the circuit per-formances. A procedure inspired by statistical model checkingis then introduced to assess the model accuracy. Given the con-structed models, an SMT-based solving algorithm is employed tolocate the failure hyperrectangles in the parameters space. Theyield estimation is based on a geometric calculation of proba-bilistic volumes subtended by the located hyperrectangles. Wedemonstrate the effectiveness of our method using circuits thatrequire expensive run-time simulation during yield evaluation.They include: an integrated ring oscillator, a 6T static RAMcell and a multistage fully-differential amplifier. Experimentalresults show that the proposed method is suitable for handlingproblems with tens of process parameters. Meanwhile, it canprovide 5×–2000× speed-up over Monte Carlo methods, when ahigh prediction accuracy is required.

Index Terms—Analog circuit, interval arithmetic, processvariations, satisfiability modulo theory (SMT), surrogate model,yield.

I. INTRODUCTION

W ITH aggressive technology scaling, process variationhas become a major concern for today’s analog inte-

grated circuits (ICs), due to significantly increased circuitfailures and parametric yield loss [1]. Indeed, analog IC com-ponents must be designed with sufficiently high yield in lightof large-scale process variations (e.g., local mismatches causedby random doping fluctuations) [2]. For this reason, it becomesimportant to estimate the parametric yield both efficiently andaccurately within the IC design flow [3].

The standard approach is the brute-forceMonte Carlo (MC) [4], which repeatedly draws samples

Manuscript received July 21, 2016; revised November 7, 2016; acceptedDecember 19, 2016. Date of publication January 11, 2017; date of currentversion February 16, 2018. This paper was recommended by Associate EditorS.-C. Chang.

The authors are with the Department of Electrical and ComputerEngineering, Concordia University, Montréal, QC H3G 1M8,Canada (e-mail: [email protected]; [email protected];[email protected]).

Color versions of one or more of the figures in this paper are availableonline at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TCAD.2017.2651807

from a predefined distribution of the process parametersand evaluates circuit performances with transistor-levelSPICE simulation. MC has the advantages of simplicity andextremely general applicability. However, it can require verylarge numbers of expensive simulations for accurate yieldestimation.

MC is inefficient especially for circuits with rare fail-ure events [e.g., static random access memories (SRAMs)],because most of the samples fall into the feasible region, andonly an extremely small fraction of samples are in the failureregion [5]. It is then desirable that the simulation cost can bereduced. This is especially important if the yield estimationneeds to be plugged into yield optimization flow since yieldestimation needs to be done for many times.

To mitigate the inefficiency issue of MC method, vari-ous methodologies have been proposed in the past decadeincluding advanced sampling techniques [6], [7] and bound-ary searching methods [8]. However, most of the existingapproaches are either not general enough [7] or can be suc-cessfully applied to problems with a small number of processparameters, but, perform poorly with high-dimensional prob-lems [8]. Given such limitations, a yield analysis method thattries to address the shortcoming of the above approaches ishighly demanded.

Response surface-based surrogate modeling is a commonapproach to analyze the effects of process variations [9].Accurate and not complex surrogate models can replacetransistor-level simulation and significantly fasten the perfor-mances assessment and consequently the yield estimation.Though, the high-dimensional variational space and the strongnonlinearity of the performances models posed by advancedIC technologies lead to a large-scale modeling problem that ishard to solve [9]. Furthermore, since the outcome of existingapproaches is an approximation of the circuit response, weakguarantees on its accuracy can be provided.

This paper is largely motivated by the powerful and newsolving techniques in modern satisfiability (SAT) modulo the-ory (SMT) [10] solvers. These solvers check the SAT offirst-order formulas containing operations from various the-ories such as real numbers and integers. They are built upona tight integration of modern conflict-driven clause learning-style SAT solving techniques with interval-based arithmeticconstraint solving within an SMT framework. They are capa-ble of handling constraints containing nonlinear functions overa very large number of variables [11], one inherent character-istics of analog circuits operation/performances models. Mostimportantly, they can be leveraged to exhaustively explore thesearch space of a constraint-satisfaction system, making thema potentially appealing choice for parameters space explorationstrategies of analog circuits. Though, they should be properlyemployed.

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518 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 37, NO. 3, MARCH 2018

In order to optimize the convergence of the yield estimation,our proposed work is based on two main directions:

1) Focusing on the localization of only the failure regionsin the parameters space: subsequently, the yield rate canbe estimated by analytic computation of the probabilistichypervolume [12] of all failure regions. The challengehere is how to efficiently ensure a reliable character-ization of the failure regions in a high-dimensionalspace.

2) Time-consuming MC simulations should be impera-tively avoided so that the efficiency is further enhanced:this goal can be achieved through performance mod-eling. In this case, the fundamental challenge isnot only the large-scale modeling problem but alsoverifying the model accuracy in any point of theparameters space with a minimum number of circuitsimulations.

Toward these goals, we rethink the yield analysis from acompletely different perspective. Principally, the key innova-tion of the proposed methodology is the formulation of thefailure regions localization problem as a set of nonlinear con-straints, that we solve using modern SMT solving techniques.To the best of our knowledge, this is the first work for yieldestimation that is able to provide a guarantee on an exhaus-tive coverage of the circuit failure regions and hence tries toachieve reliable yield results.

The rest of this paper is organized as follows. Section IIreviews existing techniques for analog circuit yield analy-sis. Section III details our yield estimation methodology. InSection IV, we provide experimental results for three analogcircuits: an integrated ring oscillator, a 6T static RAM celland a multi-stage fully-differential amplifier. In Section V, wepresent our conclusions and future work.

II. RELATED WORK

State-of-the-art advanced MC methods for circuit yieldanalysis methods can be roughly divided into two cate-gories: 1) variance reduction techniques (e.g., latin hypercubesampling (LHS) [13], importance sampling (IS) [7]) and2) low-discrepancy sequence (LDS)-based methods (e.g., quasiMC (QMC) [14]). LHS partitions the range of each variableinto nonoverlapping intervals of equal probability and selectsrandom values within each grid for every coordinate. Byrandomly combining the coordinate values, a set of latin hyper-cube are constructed. Because of this stratification technique,the LHS method is capable of providing variance reductionof the yield estimation. However, it does not work much bet-ter than the conventional MC, especially for some problemsthat are difficult to be decomposed into a sum of univariatefunctions [14].

The key idea of IS-based methods is to shift the originalprobability density function (PDF) of the process parameterstoward the most likely failure region. They have achievedremarkable speed-up when applied for the yield analysis ofcircuits characterized by rare failure event. However, IS lacksgenerality as it is designed for circuits with very high/lowyield rate. Furthermore, generating the shifted/distorted PDFis often challenging and circuit specific, since this dependson the actual distribution of the circuit performance which isunknown beforehand.

Another critical issue of IS is that the proposed (i.e.,shifted) sampling distribution may not cover effectively all

failed samples when the circuit presents multiple disjointfailure regions induced by conflicting or multiple specifi-cation requirements [5]. Besides the multiple specificationrequirements, high-dimensional process variables also inducethe multiple failure regions since the process parametersmay have opposite influence on the performance metrics [7].Only few attempts have tackled the multiple failure regionscase [7], [15]. In spite of that, while the method in [15] isapplicable only to rare failure rate estimation in a very high-dimensional variation space (i.e., few hundreds), Yao et al. [7]cited that reduction techniques are required before apply-ing their method for problems with more than 24 processparameters.

QMC is a popular approach that generates quasi-randomnumbers rather than purely-random samplings. It utilizes sam-ple sets called LDSs, in which deterministically generatedsamples are uniformly distributed on the parameter space [14].QMC methods are able to provide improved integration errorcompared to LHS [14]. Yet, its convergence rate is found tobe only asymptotically superior to MC only for circuit with amoderate number of process parameters [13].

Other existing methods try to construct a surface bound-ary which separates the success and failure regions [8]. Oncethe boundary is constructed, the yield can be obtained bycomputing the volume of the failure region without circuitsimulation. For low-dimensional problems, this method canbe efficient. However, such methods cannot handle high-dimensional problems with no more than three process vari-ables. Even when considering only three process parameters,searching the whole failure boundaries in the parametersspace is extremely complicated. The high-dimensional analysis(18–24 process variables) is common and necessary in practi-cal applications. Though, it makes the discrimination betweenfailure and success regions by hypersurfaces very hard toachieve.

While above cited approaches present a variety of tech-niques to speed up and enhance the convergence of thetraditional MC method, they fall short in addressing criticalissues that can be summarized as follows:

1) Optimally exploring the variational space that guar-antees an acceptable accuracy and minimum compu-tational time (i.e., a small number of transistor-levelsimulations).

2) Scalability with respect to the process parameters size.3) Generality of application (i.e., handling different levels

of yield rate, multiple performances metrics and multiplefailure regions).

SMT solvers have been employed for formally verifyingproperties of analog circuits [16]. Recently, SMT solvers havebeen used for a primarily attempt to integrate formal tech-niques in the circuit sizing process. The goal was to avoidthe instability of constrained optimization techniques in termsof convergence and local minima [17]. Different from thispaper, our solving strategy operates in the process parametersspace for yield estimation purpose. Similar to our approach,Lin and Li [18] subdivided their SMT-based reachability anal-ysis problem into subproblems that are solved in parallel inorder to decrease the computational complexity. To do so, aanalog circuit is decomposed into a set of smaller subcircuitswhich decreases the number of variables involved in the SMTproblems. Second, each SMT problem associated with a sub-circuit is further decomposed into a set of subproblems withless constraints to further improve the efficiency. However,

LAHIOUEL et al.: ACCELERATED AND RELIABLE ANALOG CIRCUITS YIELD ANALYSIS USING SMT SOLVING TECHNIQUES 519

Fig. 1. 2-D parameters space.

the splitting strategy in [18] gives rise to significant complica-tions. Indeed, the authors attempt to deal with the correlationsbetween the partitioned subcircuits. In contrast, in the pro-posed work, the partitioned subproblems are uncorrelated andthe output of the SMT-based parameters space explorationis the union of all failure hyperrectangles located by allsubproblems.

Sparse regression (SR) based on least absolute shrinkageand selection operator (LASSO) [19] explores the fact thateven though a large number of unknown model coefficientsmust be used to capture the high-dimensional variation space,many of these model coefficients are close to zero, thereby ren-dering a unique sparse pattern. However, as discussed in [19],the LASSO shrinkage may not select the true coefficients val-ues, as it causes the estimates of the nonzero coefficients tobe biased toward zero, and in general they are not consis-tent [19]. One approach that overcomes this issue is to run theLASSO to identify the set of nonzero coefficients, and then fitan unrestricted linear model using least square regression asit has been proposed in [20]. Still, this solution is not alwaysfeasible, if the selected set is large.

III. YIELD RATE ESTIMATION METHODOLOGY

Before presenting the proposed methodology, we brieflyexplain our main objective and define terms that will be usedin the rest of this paper. Suppose that p = [p1, p2, . . . , pl]is a l-dimensional continuous random variable modeling pro-cess variations. Such random variables include the variationsof gate length �L, oxide thickness �tox and threshold voltage�Vth, etc., associated with each circuit device. Without lossof generality, we further assume that the random variables inthe vector p are mutually independent and follow a truncatednormal distribution with ±3σ and zero mean. We define theparameters (i.e., variation) space P as the set of all possiblecombinations of the random variables. In general, the yieldrate can be mathematically represented as

Y∗ = 1− Pf = 1−∫

�

pdf( p)dp (1)

where pdf(p) is the joint PDF of p, � denotes the failureregion, i.e., the region of the parameters space where theperformances are not satisfied (can be a single region or mul-tiple disjoint regions). We denote the integral in (1) to be theprobabilistic hypervolume of � [12]. Fig. 1 is a geometricalillustration in 2-D.

In general, the multidimensional integral in (1) cannotbe directly computed since the failure region � usuallyestablishes a complex nonlinear integration boundary. In ourmethod, we propose to characterize � as a collection ofhigh-dimensional subregions (i.e., hyperrectangles). The prob-abilistic hypervolume of each subregion is then evaluated and

Fig. 2. Yield estimation method overview.

employed to estimate the total yield. Obviously, the accu-racy of the yield estimation depends strongly on how wellthe subregions are approximated. In this paper, we will mainlyfocus on this characterization problem and develop novel algo-rithms to make it tractable and computationally efficient. Themethodology in Fig. 2 details our proposed approach.

First, an adaptive SR technique is applied to extract surro-gate models of the circuit performances. In order to optimizethe modeling step, a dimension reduction technique keepsthe most significant process parameters. The proposed algo-rithm sorts the process parameters by weight assignment andprunes the unimportant parameters. Then, a low-degree andsparse polynomial model of each circuit performance is con-structed in a stepwise fashion. The LASSO method assignsadaptive weights for penalizing the coefficients of the poly-nomial terms and yields a consistent estimate of the modelcoefficients. The model is iteratively built until the requirementin terms of accuracy is met. A procedure inspired by statisticalmodel checking is then introduced to verify the model accu-racy for a chosen confidence level. The resulting model can beviewed as a statistically guaranteed approximation of the cir-cuit behavior. The subset of the circuit response space whereeach performance of interest does not meet the specificationis conservatively characterized as a set of intervals. Basedon the extracted models, SMT solving is not employed tocompute the exact failure subregions in the parameters space.Instead, it is used to find only an over-approximation of them.The integration of interval arithmetics to remove the unde-sirable over-approximation, intelligently tradesoff between thecomputational cost and the conservativeness of SMT. A par-allel exploration of the failure performance space allows thesimultaneous finding of multiple satisfiable solutions and sig-nificantly speeds up the search process. Finally, the yieldis estimated based on the probabilistic hypervolumes of thefailure subregions.

A. Adaptive Sparse Regression

In this section, we seek to produce an accurate surrogatemodel using polynomials with structured sparsity. The model-ing technique should be performed with a minimum numberof circuit simulations. Besides, the model must be computa-tionally efficient (i.e., not complex) and hence tractable for thesubsequent SMT solving stage.

1) Presampling and Dimension Reduction: The goal ofpresampling is to approximately sketch the circuit behavior.


We use the LHS method in the parameters space to gener-ate a set of training samples. Given n training samples, wedenote X = [x1, x2, . . . , xn] an l × n matrix, where eachsample xi = [pi1, pi2, . . . , pil] is an l-dimensional vector.Next, transistor level SPICE simulation is performed to eval-uate the performance metric using these samples. We denoteY = [y1, y2, . . . , yn] the n observations of the property, i.e.,the value of the circuit response we seek to fit.

The parameters reduction maps the high-dimensional pro-cess parameters space to a lower-dimensional space. In thispaper, we leverage the regressional reliefF (RReliefF) [21]algorithm to prune the process parameters and to select asmaller number of features. The algorithm uses samples-basedlearning to assign a relevance weight to each parameter. Eachfeature weight reflects its ability to perturb the circuit response.The quality estimate ranges in [−1, 1]. Equation (2) [21]shows the weight updating formula for each feature of theprocess parameter vector p

V(p) =W(p)+ NdCdp

NdC−

(Ndp − NdCdp

)n− NdC

Ndp =∣∣value(p, xi)− value

(p, xj

)∣∣max(p)−min(p)

d(i, j)

NdC =∣∣yi − yj

∣∣d(i, j)

NdCdp =∣∣yi − yj

∣∣∣∣value(p, xi)− value(p, xj

)∣∣d(i, j) (2)

RReliefF starts with a l-long weight vector, V , of zeros, anditeratively updates V for all features in p. This process isrepeated for the total number of instances n. In each itera-tion, the algorithm randomly selects a sample xi and finds allk nearest samples xj around xi, in terms of Euclidean distance.The relevance level of each feature is then assigned by approx-imating the terms in (2), where Ndp is a normalized differencebetween the values of parameters in the vector p for the twoinstances xi and xj, the quantity d(i, j) [21] takes into accountthe distance between samples by assigning greater weight tocloser samples, and NdC corresponds to the difference betweenthe performances of the two samples. The term NdCdp quan-tifies the probability that two nearest samples have differentperformances and different values of parameter. The weightincreases if the circuit responses of nearest samples differsand decreases in the reverse case. In practice, a feature is rel-evant when the weight is strictly positive and irrelevant in theopposite case [22]. The algorithm only requires O(lnlog(n))time, and is noise-tolerant and robust to feature interactions.

2) Adaptive Least-Squares Regression Using LASSO: Oncethe most relevant process parameters are captured, we seekto construct a surrogate model of each performance metricinvolved in the circuit specification. The performance func-tion is a local perturbation around its nominal value. We usepolynomial basis which are very often used to approximatesuch a local variation [9]

f(p) �M∑

m=1

cmgm(p) (3)

where f is a smooth circuit performance approximated as alinear combination of M basis functions, cm are the modelcoefficients, and gm(p) is a basis functions (linear, quadratic,or cubic polynomials). The unknown model coefficients cm aredetermined by solving a set of linear equations at a numberof sampling points (training data), which is usually solved as

a least squares problem

mincm,m∈[1,M]

‖f(p)− q(p)‖22, q(p) =M∑

m=1

cmgm(p) (4)

In fact, the number of process parameters is often large, whilethe number of training samples is greatly limited by the com-putational cost. Given the limited computational budget, theunderlying system is rank deficient. Therefore, the solutioncm (i.e., the vector containing unknown model coefficients)is not unique and impossible to identify without additionalconstraints. To solve this problem, we propose to employadaptive LASSO as a weighted regularization technique forsimultaneous consistent estimation and variable selection [19]

mincm,m∈[1,M]

‖f(p)− q(p)‖22 + α

M∑m=1

∥∥∥∥ cm

wm

∥∥∥∥1

(5)

where α is a nonnegative regularization parameter. ‖‖1 standsfor the l1-norm of a vector which denotes the sum of theabsolute values of all elements in the vector. The weighted

penalty function αM∑

m=1‖(cm/wm)‖1 is an additional constraint

that forces the coefficients cm to behave regularly by shrink-ing the coefficients toward 0 as α increases. Data-dependentweights w are employed for penalizing different coefficientsin the l1 penalty. By allowing relatively higher penalty func-tion (higher weight) for small coefficients and lower penaltyfunction (lower weight) for larger coefficients, the adaptiveLASSO neutralizes the influence of the coefficient magnitudeon the l1 penalty function. Thus, it reduces the coefficient esti-mation bias compared with the standard LASSO. Furthermore,the adaptive LASSO shrinkage retains the attractive convex-ity property of the standard LASSO [19]. Most importantly,it is proved to be near-minimax optimal [23]. The weightw can be any consistent estimate of cm. Here, we selectw = (XTX)−1XTY to be the ordinary least square estimateof cm [23], where XT denotes the vector transpose of X.

Algorithm 1 provides a simplified description of the adap-tive SR algorithm. This algorithm is applied to construct asurrogate model q(p) of each performance metric interveningin the circuit specification. It requires as inputs a set of trainingX and test samples Xt and their corresponding circuit responsesY and Yt, respectively. Typically, the number of training sam-ples can be selected from 200 to 500 while the test samplesfrom 100 to 300. In line 1, we use the RReliefF algorithm toselect a smaller number of features p and filter out featuresthat hardly have contributions to the circuit response.

The parameter k is the number of nearest instance con-sidered by RReliefF [24]. In all experiments conducted inthis paper (see Section IV), we find that k = 15 providesstable and reliable reduction results. In line 2, the functionselect extracts the observation Xp and Xt

p corresponding tothe reduced process parameters space p from the original setX and Xt, respectively. Then, the algorithm operates in aniterative fashion. At each iteration, the polynomial degree isincremented (line 4). The idea is that higher degree terms areincluded only when necessary to avoid high order model. Inline 5, we construct a set of polynomial basis gm(p) of degreed. The polynomial terms of gm(p) are obtained by expandingall the terms in the d-degree polynomial (1+p1+· · · )d. Then,Xf maps the reduced data matrix Xp to each expansion termsof gm(p). In lines 6 and 7, the weights w are computed and the


Algorithm 1 Response Surface-Based Surrogate ModelTraining

Require: X, Xt: Data samples, Y , Yt : Circuit response,D = 3: Maximum degree, d = 0, k = 15, Rth: Accuracythreshold

1: p←RReliefF(X, Y, k),2: Xp ← select(X, p), Xt

p ← select(Xt, p)

3: while d < D and ε > Rth do4: d← d + 15: Xf ← expand_polynomial_basis (Xp, p, d)6: w← compute_weight(Xf , Y)

7: q(p)← adaptive_lasso(w, Xf , Y)8: ε← verify(q, Xt

p, Yt)9: end while

10: if ε ≤ Rth then11: Return (Accuracy model metI)12: else13: Generate fresh samples and go to 514: end if

adaptive LASSO problem in (6) is solved using the coordinatedescent algorithm [24]

mincm,m∈[1,M]

∥∥Y− Xfcm∥∥2

2 + α

∥∥∥∥ cm

wm

∥∥∥∥1

(6)

The coordinate descent iterations terminate when the relativechange in the size of the estimated coefficients drops below1e−9. It is important to note that cm are computed each timethe degree d is incremented. This recalculation is requiredbecause the new basis function constructed at the current iter-ation step may change the model coefficient values calculatedat previous iteration steps. The regularization parameter α ischosen during the training process. It is selected such thatit minimizes an estimate of expected prediction error basedon tenfold cross-validation applied to the training samples. Inline 8, the test samples Xt

p are used to verify the accuracyof the current trained model. The prediction ability of themodel is tested by calculating the normalized mean squareerror (NMSE=(‖q(Xt

p)− Yt‖22/‖Yt‖22)). When the error of theperformance model ε is less than a given threshold, namedRth, or the degree d reaches the limit D, the iteration stops.

If the desired accuracy is not met and d reached the max-imum degree D, then fresh samples are generated and addedincrementally to the training sample set as long as the modelaccuracy does not satisfy the convergence condition (line 13).The generation of the fresh samples uses a triangulationapproach as explained in [7]. How to select the parameterRth will be discussed in Section IV-D.

In practice, the number of samples required to compute εcannot be fixed in advance. If a very large evaluation set isemployed to evaluate the error ε, then the resulting modelaccuracy can be trusted. However, this would prohibitivelyincrease the computational cost. Next, we propose to employstatistics to provide a certain confidence level on the modelaccuracy with a probability of error which can be prespecified.

B. Accuracy Generalization and Verification

On one hand, the surrogate model error ε can never betotally eliminated. On the other hand, its accuracy verificationis primordial to prove the reliability of the yield estimation

methodology. The surrogate model accuracy (1 − ε) can beconsidered ϕ-guaranteed if

∀p, p ∈ P, Pr((

err(f(p), q

(p)) ≤ ε

)≥ ϕ (7)

where Pr and err stand for probability and model error, respec-tively. In other words, the model error is at most ε for atleast ϕ portion of the parameter space. Clearly, at this stagethere is no guarantee on the model accuracy (1 − ε). Thepurpose of this step is to determine a generalized accuracyunder the process parameter space, given a probability/level ofconfidence ϕ.

To do so, we employ and extend the statistical procedureproposed by Younes [25] that regards the model checking ofa system as a hypothesis testing problem and solves it usingWald’s [26] sequential probability ratio test (SPRT). The ideais to check the accuracy property in (7) on a samples set ofsimulations and to decide whether the model q(p) satisfies theproperty based on the number of executions for which theproperty holds compared to the total number of executions.With such an approach, we do not need to explore and testall possible values of process parameters. We rather answerthe question of whether the model satisfies the property witha probability greater than or equal to a value ϕ ∈ [0, 1].Furthermore, we propose a simple, yet elegant modificationto the SPRT test which allows the computation of a general-ized model accuracy ε. The problem is treated based on twoexclusive hypothesis testing given as follows:

H0 = Pr(err

(f(p), q

(p)) ≤ ε

) ≥ ϕ + δ = ϕ2

H1 = Pr(err

(f(p), q

(p)) ≤ ε

)< ϕ − δ = ϕ1 (8)

where H0 and H1 are known as the null and the alternativehypothesis and 2δ forms a small region called the indifferenceregion [25], on both sides of the cutting point ϕ. If the proba-bility is between ϕ1 and ϕ1 (the indifference region), then wesay that the probability is sufficiently close to ϕ so that weare indifferent with respect to which of the two hypothesesis accepted. The method determines on the fly the number ofsimulations needed to achieve a desired accuracy and providesa convenient way to control the tradeoff between precision andcomputational cost. To decide between the two hypothesis, thetest proceeds by computing at the nth stage of the test, i.e.,after making n observations, a log likelihood ratio given as

n = log

∏ni=1 zϕ1(bi)∏ni=1 zϕ2(bi)

= log

∫ ϕ10

∏ni=1 zbi(1− z)1−bidz∫ 1

ϕ2

∏ni=1 zbi(1− z)1−bidz

(9)

where n represents the total number of samples or the testlength, b1, b2, . . . , bn is a collection of Bernouilli randomvariables denoting the outcome of the accuracy property (7)with random samples x1, x2, . . . , xn drawn from the parame-ters space. zϕ1(bi) and zϕ2(bi) are the probability mass functionof the Bernouilli distribution parameterized by ϕ1 and ϕ2,respectively. The quantity n is finally given as

n = logBϕ1(k + 1, n− k + 1)

A− Bϕ2(k + 1, n− k + 1)(10)

where 0 ≤ k ≤ n is the number of successful inequality test,A = (1/(n+ 1)Cn

k ) and Bϕ1 and Bϕ2 are the incomplete Betafunctions. H0 is accepted if n ≤ a and H1 is accepted ifn ≥ b, where a and b are given in line 1 of Algorithm 2. αand β are two decision error rates that determine the strength


Algorithm 2 Verification and Generalization of the ModelAccuracyRequire: q: Surrogate model, ε: model error, p,p: Process

parameters, ϕ1, ϕ2: Probabilities, α, β: Error rates.1: a = log( α

1−β); b = log( 1−α

β), Xt

p, Yt

2: n = 0; k = 0;3: while a < n < b do4: n← n+ 15: xn ← Sample the parameters space P6: f ← Simulate the circuit at the parameters xn and

measure f7: Xt

p, Yt ←Update(Xtp, Yt, xn, f )

8: if err(q(Xtp), Yt)> ε then

9: ε← err(q(Xtp), Yt)

10: else11: k← k + 112: end if13: Evaluate n(n, k, ϕ1, ϕ2)14: end while15: if n ≤ a then16: Accept H017: else18: Accept H119: end if

of the test, where α is the type I error rate or false positiveand β is the type II error rate or false negative.

The procedure is summarized in Algorithm 2. It repeatedlychecks the accuracy property with fresh samples xn drawnfrom the parameters space p (line 5). After measuring the sam-ple response f (line 6), we add the fresh observation (xn, f )to the testing samples (Xt

p, Yt) (line 7) and we compute theNMSE (line 8). We say that the inequality test is a successif the property holds, and a failure otherwise. Upon each suc-cess, we increment the counter k (line 11) and continue withfresh samples until a failure occurs. In this case, we updateand generalize the error ε (line 9). We can therefore character-ize the required number of observations as inf{n,n /∈ ]a, b[}.Clearly, this number increases if α and β are smaller but also ifϕ is very close to one. We provide in Section IV-D a discussionconcerning these parameters.

C. SMT-Based Parameters Space Exploration

The objective of this stage of the methodology is toexhaustively probe the parameters space and to determinefailure hyperrectangles, i.e., regions where the circuit failsto satisfy the design specification. Our approach is summa-rized in Algorithm 3. In order to conservatively find thereachable parameters values, we formulate the SMT prob-lem constr as a conjunction of the space of the processparameters, the constructed surrogate models and the speci-fication violation constraints. In general, the problem can beformulated as

pmin ≤ p ≤ pmax

fk(pk

) = qk(pk

)fminK ≤ fK ≤ fmax

K , K = 1K∨

k=1

fmink ≤ fk ≤ fmax

k , K > 1 (11)

Algorithm 3 SMT-Based Parameters Space Exploration

Require: S, K, constr, NS = SK

1: for all ind = 1→ NS do in parallel2: fk ⊆ [f min

k , f maxk ]ind

3: repeat4: Invoke iSAT3(constr)5: if a candidate is found then6: Invoke INTLAB(constr, candidate)7: if Locate pbox then8: Return(Perf box, pbox)9: Update(Perf box, fk)

10: end if11: end if12: until Unsatisfiable13: end for

where fk(pk), k = 1 . . . K, are the performance equations, Kis the total number of performance metrics involved in thedesign specification, and pk is the reduced process parametersset associated to the kth performance metric. [pmin, pmax] arethe ranges of the process parameters determined from theirprobabilities distributions, where p = [p1, p2, . . . , pr] and r =dim(∪k

1pk) is the dimension of the reduced parameters space.As mentioned before, a truncated normal shape is used in thispaper to model the process parameters. If ±3σ variation isconsidered then, the upper and lower bounds of the processparameters pmin and pmax, respectively, are defined as

pmin = pnom − 3σ ;pmax = pnom + 3σ (12)

where pnom is a vector of nominal values. [f mink , f max

k ] are thebounds that approximate the failure region of the circuit opera-tion in the performance space. For example, if we are given anoscillator circuit designed at a nominal frequency fnom and themaximum allowed frequency deviation is �f , then the failurefrequency region is defined as: [f l, fnom−�f [∪]fnom+�f , f u],where f l and f u are the minimum and maximum performancesvalues reached by the circuit. It is important to set a conser-vative approximation of f l and f u in order to let the solverdiscover any possible failure of the circuit response underthe defined parameters variation. The over-conservativeness isespecially necessary for circuits with rare failure event wherethe circuit simulation in the initial presampling cannot besufficient to sketch the performance bound. We provide inSection IV-D a discussion concerning the setting of the failureperformance bound.

In case of multiple performance metrics, the specificationviolation is mathematically formulated as a disjunction of fail-ure performance bounds, as given in line 4 of (11), where

∨denotes the logical OR operator. In fact, a high-dimensionalregion in the parameters space is considered as a failure regionif any performance metric involved in the specification is notsatisfied.

The SMT solver iSAT3 [11] we are using in this paperis known to attempt to solve NP-complete problems. Solvingthese problems, in their worst case, would take time which isexponential in the number of variables to solve. It would bethen infeasible to run the search over a large initial spaceof failure performance bounds [f min

k , f maxk ]. For these rea-

sons, we propose first to split the SMT problem constr intoNS = SK subproblems that we solve simultaneously (line 1).For example, if the circuit requires two performance metrics(K = 2) with S = 5 uniform discretization steps, then the


Fig. 3. Illustration of the coordinates of a failure subregion in 2-D parametersspace.

overall combinations of performance space to be exploredis NS = SK = 52. Each subproblem is limited to a possi-ble combination of performance boundaries. More precisely,for each subproblem, a possible combination of the failureregions in the performance space is traversed and the spec-ification violation constraint is formulated as:

∨Kk=1 fk ⊆

[f mink , f max

k ]ind, k = 1 . . . K. Also, it is important to note thatall subproblems have the same SMT constraints and the sameprocess parameters variables. Based on this, solving all sub-problems is completely equivalent to solving the original SMTproblem.

Obviously, we can observe that the complexity increaseswith more performance metrics and greater precision in sam-pling. For this reason, the SMT subproblems are solved inparallel to reduce the timing complexity. The solver returnsa set of continuous ranges of each variable (i.e., a hyperrect-angle) in the SMT constraints (line 5). However, the set ofinterval solutions is only an over-approximation (candidate)that can be devoid of any real solution to the constraints.The uncertainty can be alleviated by setting a high resolu-tion of the returned candidate. Still, this will dramaticallyincrease the computation time. Owing to this, the size of theinterval solution (resolution) is adjusted for a tradeoff betweencomputational cost and over-approximation.

In fact, we only use the SMT solver to refine the ini-tial search space toward a candidate solution and to discardthe infeasible solution. Afterward, for each set of intervalsproposed by iSAT3, we exploit the MATLAB toolbox forinterval arithmetic INTLAB [27] to further refine the candidatesolution (line 6). Given the candidate solution as interval ini-tial condition and the performance equations, INTLAB eitherrefutes the existence of any solution in the candidate solutionreturned by the SMT solver or produces an hyperrectanglepbox that is contained in the candidate region and guaranteedto contain the solution (line 7). The widths of the interval solu-tion pbox returned by INTLAB are smaller than the candidateregion proposed by the SMT solver.

The result of the refinement process is a set of intervalprocess parameters pbox and its corresponding reachable per-formances Perfbox (line 8). The function Update in line 9removes Perfbox from the search space by adding the con-straint Perfbox � fk. This will force the solver to search fornew solutions. Finally, when all reachable hyperrectangles arefound, the solver will return Unsatisfiable, providing a guar-antee on a complete coverage of the search space (i.e., thefailure region). In fact, Algorithm 3 exploits the strength ofthe SMT solver (i.e., its search space coverage capabilities)while avoiding its disadvantages.

Algorithm 4 Yield Rate ComputationRequire: {pbox}1−→nf

Pf = [∏r

i=1 CDF(pui )− CDF(pl

i)]11: for all j = 2→ nf do2: pbox

j ← pboxj −⋂

(pboxj , pbox

1→j−1)

3: Pf ← Pf + [∏r

i=1 CDF(pui )− CDF(pl

i)]j4: end for5: Y∗ ← 1− Pf

D. Yield Estimation

In the previous stage of the methodology, we have char-acterized � as a set of high-dimensional subregions in theparameters space: � � {pbox}1−→nf , where nf is the totalnumber of located subregions. A failure subregion is a hyper-rectangle that is modeled as a cartesian product of orthogonalintervals pbox = ([pl

1, pu1]× . . .× [pl

r, pur ]]). We recall that the

parameters p are assumed independent and continuous randomvariables. The probability that the process parameters fall intoa single subregion pbox is estimated in 2-D (for illustrativepurposes) as

P(

p1, p2 ∈ pbox)=

∫pbox

pdf(p)dp =2∏

i=1

P(

pli ≤ pi ≤ pu

i

)

=2∏

i=1

CDF(pu

i

)− CDF(

pli

)(13)

where P stands for probability, pu1, pl

1, pu2, pl

2 are the coor-dinates of the subregion in 2-D (as shown in Fig. 3), andCDF(pi) [24] represents the cumulative distribution function ofpi. For the total nf failure subregions in r-dimensional param-eters space, the probability that the design constraints are sat-isfied in the presence of parameters variation is generalized as

Y∗ = 1− Pf = 1−nf∑

j=1

∫{pbox}j

pdf(p)dp

= 1−nf∑

j=1

[r∏

i=1

CDF(pu

i

)− CDF(

pli

)]

j

(14)

The multidimensional integral in (14) is the probabilistichypervolume of a single subregion. Obviously, the contributionof a located subregion to the failure probability Pf is higherwhen the the coordinates of the hyperrectangles are closer tothe center of the process parameters space. The circuit yieldis computed according to Algorithm 4. In line 2, the hyper-rectangle is refined for more precision and accuracy. The term⋂

(pboxj , pbox

1→j−1) is the region resulting from the overlappingbetween the located boxes. The overlay may occur if somehyperrectangle share the same values of process parameters ordue to the conservativeness of interval arithmetic computation.

IV. APPLICATIONS

In this section, we present the application of the yield rateestimation methodology on the examples of a three-stage ringoscillator, a six transistor SRAM cell and a three-stage opera-tional amplifier (op-amp). In the experiments, the circuits aredesigned in a commercial TSMC 65-nm process and simulatedin HSPICE with BSIM4 transistor models. The local mismatch


Fig. 4. Three-stage ring oscillator.

Fig. 5. Weight of all 24 process variations for the frequency oscillationperformance.

variables are considered as the process parameters includingthe oxide thickness �tox, threshold voltage under zero bias�Vth, channel width �w and channel length �L. We use theTSMC 65-nm transistor mismatch model with Vdd = 1 V andstandard threshold voltage. The mismatch model uses princi-pal component analysis [19] to model the process parametersas a set of independent random variables.

The algorithms parameters are selected as follows. Thevalue of the convergence condition Rth in Algorithm 1 isselected as 2. 10−2. We also choose a degree limit D of 3 forall performances models. For the model verification step, weused ϕ = 0.95, a symmetric test strength α = β = 0.01 andan indifference region of size 10−3, indicating that the statisti-cal test covers at least 95% of the parameter space with a highstatistical conAdence. All simulations were performed usingan 8-core Intel CPU i7- 860 processor running at 2.8 GHzwith 32 GB memory and Linux operating system.

A. Three-Stage Ring Oscillator

We consider a three-stage ring oscillator as shown in Fig. 4.The oscillation frequency is chosen to be the performancemetric of interest. The nominal frequency fnom is 3.207 GHzcalculated via periodical steady state simulation. The designspecification requires that the variation of the frequency shouldbe within 2.5% of fnom.

The oscillation frequency is affected by various processparameters in the transistors. The local mismatch variablesof each transistor are considered as the process parameters,which results in a 24-D problem.

First, we consider 400 LHS data samples with 300 of themfor training and 100 for testing. On this 24-dim problem,RReliefF is performed to reduce the dimension before con-structing the frequency model. For each process parameter,the weight is evaluated and ranked as illustrated in Fig. 5.The process parameters with negative weight are discardedand 12 parameters are kept.

We measure the oscillation frequency under the effect ofthe reduced set of process parameters, in order to check theaccuracy of the reduction process. Fig. 6 shows the frequency

Fig. 6. Ring oscillator frequency responses under the original and the reducedprocess parameters variational space.

TABLE IFREQUENCY MODELING RESULT

performance of 300 LHS data samples when considering thetotal number of process parameters (original dim-24) and thereduced one (reduced dim-12). The frequency responses areevaluated using the circuit simulator HSPICE. As it can beobserved in Fig. 6, the frequency response with the reducedset exhibits some deviation as expected. The reduction erroris checked by calculating the NMSE, which is given as:((‖freq(12− dim)− freq(24− dim)‖22/‖freq(24− dim)‖22) =0.0245%). The actual error is less than 0.1% which isconsidered excellent in practice [28].

After applying the proposed adaptive LASSO scheme forsurrogate modeling, we extract a frequency model of degree 3.The ability of the proposed modeling technique is comparedto the generic SR using the standard LASSO method, appliedwithout the parameters pruning stage. The frequency of the testsamples are calculated by both constructed frequency modeland HSPICE simulation. The modeling results are summarizedin Table I.

First, the proposed ASR algorithm appropriately selects asmall subset of important monomial polynomial basis whencompared to SR. Second, ASR achieves 33% better fittingaccuracy than the standard LASSO. This in turn demonstratesthe advantage of the weighted regression approach to consis-tently approximate the frequency model coefficients so thatthe results are not over-fitted due to the limited training set.Third, the fitting time (i.e., the cost of solving all model coef-ficients from the sampling points) is almost two time less thanthe generic SR. The fitting time reduction has been achievedthanks to the process parameters pruning.

Algorithm 2 computes 160 circuit simulations required togeneralize and verify the frequency model accuracy. Fig. 7shows a graphical representation of the statistical test. The linea is the acceptance line. Similarly, the line b is the rejectionline for the test. The curve intersects the line a at the observa-tion number 160. The test is achieved at this point with a highgeneralized accuracy of 98.1%. At the 80th and 82nd circuitsimulation, the accuracy test has failed and the model errorhas been updated (i.e., generalized).

In Table II, we compare our results with different sam-pling methods including the brute-force MC, QMC, and LHS(MC+LHS), implemented in HSPICE. Column 2 of Table IIshows the number of harmonic balance (HB) circuit sim-ulations and “time cost” is the time spent on simulations.The brute-force MC with 10 000 is able to compute a highly


TABLE IIYIELD RESULTS FOR THE RING OSCILLATOR WITH 24 PROCESS PARAMETERS

TABLE IIIYIELD RESULTS FOR THE RING OSCILLATOR WITH THREE PROCESS PARAMETERS

Fig. 7. Generalization and verification of the frequency model accuracy.

accurate result of the yield rate with an estimated error < 1%at a 99% level of confidence. It is used as the goldenI resultto assess the accuracy and efficiency of all others methods inthis experiment.

For our method, the number of HB simulations includesthe number of simulations performed in the model fitting andaccuracy verification phases. The 560 HB simulation runs cor-respond to 300 training samples, 100 testing samples and160 samples for accuracy verification. The column time costincludes the time for all stages in the proposed methodology(i.e., the surrogate model fitting and verification, the param-eter space exploration and the yield calculation). During theSMT-based parameters exploration stage, we define the full failperformance intervals as [2.5 GHz, fnom− fnom2.5%[∪] fnom+fnom2.5%, 4 GHz]. In this experiment, SP = 52 = 25 com-binations of performance boundaries have been explored inparallel. The SMT solver [11] has reported 2820 candidateregions. Two thousand six hundred forty-three regions wereconfirmed by INTLAB during the solution refinement step.The regions found by the SMT solver and not confirmed dur-ing the refinement step are spurious. In this case, INTLABrefuted the existence of any solutions within the candidateregions.

On the basis of Table II, it can be observed that theperformance of the MC variants do not achieve significantimprovement when compared to the brute-force MC analy-sis engine. QMC is able to reach the MC golden result witharound 2.16× speedup, while the MC+LHS method is 1.54×times faster than MC with approximately the same yield rate.Collecting extra random samples for MC+LHS does not helpto converge exactly to the MC golden estimation. This obser-vation can be explained by a bad exploration of the parametersspace and a moderate uniformity properties of MC+LHS inthis 24-D problem.

Since the proposed method attempts to ensure an exhaus-tive coverage of the failure regions in the parameters space, it

tends to under-estimate the yield. It explains why the predictedyield from our procedure is slightly lower than the samplingyield from MC simulations. However, the computed yield rateis almost identical to that estimated by the brute-force MCengine with 10 000 samples. Algorithm 3 completed the searchfor the failure subregions in 0.16h, which is affordable andclearly demonstrates the scalability of the proposed method.In fact, the SMT problem subdivision allowed the reductionof the search space (i.e., failure performance space), and whencoupled with the parallel implementation, it highly relieves thecomputational cost of the SMT solver.

Our method can achieve 11× speedup over the MC methodwhile it adopts a more exhaustive approach for the yield esti-mation. The achieved speedup can be explained by: (1) theprocess parameters reduction step; (2) the employment of asurrogate model of the frequency model to replace time con-suming transistor-level HB simulation; and (3) the trackingof a complete hyperrectangle in the parameters space ratherone sample point which allows a faster coverage of the failureregions.

In order to illustrate the capability of our method in han-dling multiple and distinct failure regions, we use a simplifiedprocess variational space, which only considers the thresholdvoltages of the nMOS transistors M1, M3, and M5 as thesources of process variations. In this experiment, we appliedthe proposed scheme without the parameters pruning stage andwe formulate the SMT constraints to locate the failure regionsin this 3-D problem. The results are summarized in Table III.As less process variables are taken into account, the time costhas significantly decreased comparing with the 24-D problemand the yield rate has also increased. The failure subregionslocated by our method and the fail samples of the brute-forceMC engine can be clearly visualized on a 3-D parame-ters space as shown in Fig. 8(a) and (b), respectively. Thedata is projected on the three directions (VthM1, VthM3, VthM5)of the 3-D space, where VthMi = Vth0Mi + �VthMi,i = 1, 3, 5.

Fig. 8(b) shows that, similarly to the MC method, the pro-posed method locates two failure regions. The two regionsresult from the interval specification of the frequency perfor-mance metric which can be equivalently expressed as twoconflicting specifications. For both methods, the frequencyspecification is violated for high and low threshold volt-age variations of the nMOS transistors of M1, M3, and M5.However, while the MC method randomly samples the pro-cess parameters probability distribution pdf(p) toward locating


(a)

(b)

Fig. 8. (a) Fail samples of the brute-force MC method. (b) 3-D failuresubregions probed by the proposed method.

Fig. 9. Schematic of a 6-T SRAM cell.

the failure operation, our method directly locates 3-D failuresubregions in the parameters space. Also, during the SMT-based parameters space exploration, the process parametersare modeled as a set of intervals in the SMT constraints. Itexplains why the located failure-subregions covers the com-plete parameters space in Fig. 8(b) and differs from the failurecharacterization of the brute-force MC method in Fig. 8(a).It is only at the yield calculation step that the pdf(p) of theprocess parameters are taken into consideration to estimate theprobabilistic hypervolume of each single subregion as givenin (14).

Furthermore, although the proposed approach may misssome failure subregions due to the modeling error, the prob-abilistic hypervolume of the located subregions still can beemployed to estimate the yield with 0.077% relative errorwhen compared with the MC method. Based on this exam-ple, the ability of the proposed method in solving problemswith multiple failure regions is verified.

B. 6-Transistor SRAM Cell

In this section, a standard 6-transistor (6-T) SRAM cell,shown in Fig. 9, is used to validate the proposed methodon a circuit with extremely high yield probability [i.e., verylow failure rate (Pf )]. In this example, a larger number ofsigma variation (6σ ) is considered. We also suppose that thebrute-force MC methods converges when the relative stan-dard deviation of the failure probability (std(Pf )/Pf ) is equalto 0.1 (i.e., 90% accuracy with 90% confidence) [29]. TheSRAM cell is used to store one memory bit: the four transis-tors M1–M4 have two stable states, i.e., either a logic 0 or 1,and the two additional access transistors M5 and M6 serve tocontrol the access to the cell during read and write operations.

The circuit performance is chosen as the read static noisemargin (SNM) to evaluate the stability of the SRAM cell dur-ing read operation. The SNM is defined as the maximum value

Fig. 10. Weight of all 24 process parameters for the SNM performance.

Fig. 11. SNM responses under the original and reduced process parametersspace.

Fig. 12. Generalization of the SNM model accuracy.

of DC noise voltage that can be tolerated by the SRAM cellwithout changing the stored bit [30]. A positive value of SNMrepresents a stable read operation while a zero or negativevalue of SNM signifies that the read operation will cause thecell to lose its state, resulting in the read stability failure. Inthis paper, the SNM is measured by the length of the maxi-mum embedded square in the butterfly curves (i.e., the voltagetransfer curves of the two inverters). When SNM is smallerthan zero, the butterfly curves collapse and a data retentionfailure happens [30].

The local �tox, �Vth, �w, and �L mismatch of each tran-sistor are considered as the process variables, which resultin 24 process parameters. On this 24-D problem, RReliefF isapplied to reduce the dimension before constructing the SNMperformance model. For each process variation parameter, theweight is evaluated based on 300 training samples. The reduc-tion process discarded eight process parameters as it can beobserved in Fig. 10. Fig. 11 plots the SNM responses sim-ulated by HSPICE, under the effect of the full and reducedprocess parameters set. We evaluate the NMSE to estimatethe responses deviation. The computed error is 0.5% which islow and can be considered as negligible.

We apply the adaptive LASSO scheme for modeling theSNM surrogate model. We extract a polynomial model ofdegree 2 and we use 100 test samples to evaluate its accu-racy. We verify and generalize the SNM model accuracy. Theaccuracy verification result is shown in Fig. 12. Algorithm 2computes a generalized model accuracy equal to 98.7% basedon 128 simulation runs.

The experimental results are summarized in Table IV.For our method, we define the full SNM fail interval as:[−0.3V, 0V]. We subdivide the SMT problem into SP =51 = 5 that we solve in parallel according to Algorithm 1.


TABLE IVYIELD RESULTS FOR THE SRAM WITH 24 PROCESS PARAMETERS

Fig. 13. Evolution of the failure rate estimation as function of samples forthe brute-force MC and the QMC method.

Fig. 14. Evolution of failure rate estimation as function of tracked failuresubregions for the proposed method.

Column 2 of Table IV reports the number of simulations per-formed in the SNM model fitting and accuracy verificationphases. The column time cost shows the time for the totalstages in the proposed methodology.

The MC method tries to randomly select samples to coverthe entire parameters space, so it needs a huge number of sam-plings to achieve the target 90% level of accuracy as shownin Fig. 13. QMC is able to reduce the number of samplingsby covering the entire space with deterministic sequences. Itcan be observed that the QMC method achieves around 2×speedup over the MC method with very close failure rateestimation. The method we propose in this paper achievesa speedup of approximately 2000× comparing with the MCmethod.

As shown in Fig. 14, the proposed algorithm covers thefailure region in the parameters space within 2205 locatedregions, which explains the relief in terms of computationalcost. The first 400 refined regions had more contribution tothe failure rate estimation in terms of probabilistic hypervol-umes. The method also reaches a higher failure probability(Pf ) compared to the MC method. This can be explained bythe approach adopted in the proposed methodology that con-centrates on the localization of only the failure regions in theparameters space. Meanwhile, the sampling methods waste alarge number of samples that are far from the failure region.

Fail samples of the MC simulation result are drawn inFig. 15(a) which clearly shows two regions with rare failuresamples. The failure occurs for asymmetrical local Vth vari-ation affecting the adjacent pulling-down transistors M1 andM2. A similar localization of the failure region is reached bythe proposed yield analysis scheme as it can be observed in

(a)

(b)

Fig. 15. (a) Fail samples drawn from the simulation of the brute-force MC.(b) Failure subregions located by the proposed method.

Fig. 15(b). In both figures, the simulation data is projectedon the three directions (VthM1, VthM2, VthM5) for visualizationpurpose. The proposed failure regions localization techniqueneutralizes the rare failure event issue of the SRAM circuit.Based on this example, the advantage of the proposed methodin locating very rare failure regions has been demonstrated.

C. Three-Stage Operational Amplifier

In this section, we will verify that the proposed methodis suitable for solving problems with multiple performancesspecifications as well as high-dimensional parameters space.We consider a three-stage amplifier (op-amp) as shown inFig. 16.

We select �tox, �Vth, �w, and �L as the process variables.The local mismatch in each transistor pairs is considered. Itleads to a total of 56 process parameters. The performance ofthe circuit is characterized by many properties, such as voltagegain (Av) and phase margin (PM). The op-amp is designed tosatisfy the list of specifications shown in Table VI.

First, 300 initial LHS simulations are used to build a sur-rogate model of for all properties. 200 of them are employedfor model training and 100 for subsequent model testing. Eachproperty is measured using a specific type of simulation. Notethat even though we analyze and model each performance met-ric individually, these performance metrics are not necessarilyindependent as they are sharing the transistor-level simulationsof the presampling stage. In fact, by evaluating all performancemetrics for each individual sample drawn from the processparameters space, we substantially reduce the total number ofsimulation runs and, hence, the computational cost.

On this 56-dim problem, RReliefF is performed to reducethe dimension the process parameters. The experimentalresults of the reduction process are summarized in Table VII.It can be observed that in this example the dimension of theoriginal set of process parameters for each performance metricdid not largely decrease. This can be explained by the consid-eration of multiple performance metrics that depend on mostof the process variables. Furthermore, the accuracy of the cir-cuit response under the reduced set of process parameters ismaintained.


TABLE VYIELD RESULTS FOR THE OP-AMP WITH 56 PROCESS PARAMETERS

Fig. 16. Three-stage operational amplifier.

TABLE VISET OF SPECIFICATIONS FOR THE THREE-STAGE OP-AMP

TABLE VIIRESULT OF THE PROCESS PARAMETERS REDUCTION STAGE

We evaluate the accuracy of the models trained using theadaptive LASSO scheme. We report the final degree of theapproximations and the models accuracies in Table VIII. Inthe “degree” column, we see that for some properties, we areable to construct polynomial models with a degree lower thanthe limit D = 3. The accuracy generalization step statisticallyverify the op-amp properties model with respect to the reducedset of process parameters. In the column “gen-accuracy,” wereport the result of the accuracy generalization stage. We canfind that the accuracy is more than 97% for all models.

We apply the brute-force MC, QMC, and MC+LHS to esti-mate the yield of the op-amp. The brute-force MC method isrun with a target accuracy of 99% and a confidence level of95%. For the sampling methods, time cost is the circuit sim-ulation time and “Sim(�)” refers to the number of samples.The column Sim(�) in our method includes the number of cir-cuit simulations performed in the surrogate model fitting andaccuracy verification phases. “Sim time” shows the total cir-cuit simulation time and “fitting/verif time” indicates the timespent in the model fitting and verification stages excluding the

TABLE VIIISURROGATE MODELS DEGREE AND ACCURACY (1-NMSE)%

circuit simulation time. “Time” is the time spent in the param-eter space exploration and the yield calculation. Finally, timecost is the total computational time.

As in the previous experiments, we observe that the pre-dicted yield from our approach closely matches the yieldestimation of the MC method. Our method requires fewersimulations and finishes faster with a speedup of almost 5×.This application shows again the benefits of a model build-ing approach rather than direct yield estimation from a circuitsimulator. Also, the column fitting/verif time in our methodshows that even though the reduction result was not very sig-nificant, the proposed adaptive SR algorithm still renders thefitting time quite affordable. This result further demonstratesthe scalability of the proposed technique to handle larger prob-lems. The regression time of the model performance with adegree lower than the degree limit (i.e., GBW and DCOffset)is significantly smaller. In fact, the major cost in regressionlies in the computation of the LASSO coefficients. The for-mer can be easily parallelized, leading to further performanceimprovements.

D. Parameters Discussion

In this section, the key parameters in the proposed methodwill be discussed.

1) Parameter Rth in Algorithm 1: We construct the fre-quency model of the ring oscillator example in Section IV-Awith different Rth from 9.10−2 to 1.10−2. Fig. 17 shows theerror of the yield rate with respect to the model accuracydefined as (1 − Rth)%. The error of the yield is computedrelatively to the yield result of 10 000 MC simulations run.We can find that when the accuracy is smaller than 97%, therelative error resulting primarily from the fitting error of thefrequency model increases significantly. To ensure the viabil-ity of the proposed method, we must ensure that the accuracyis high enough at the modeling stage. So, in practice, the valueof Rth should be selected from 3.10−2 to 1.10−2.

2) Parameters (α, β, ϕ) in Algorithm 2: We appliedAlgorithm 2 to verify and generalize the frequencymodel accuracy freq(p) of the Ring Oscillator example inSection IV-A. We checked the property

∀p, p ∈ P Pr((err(f (p), freq(p)) ≤ ε) ≥ ϕ (15)


Fig. 17. Relative error with respect to Rth.

TABLE IXRUN LENGTH FOR COMMON VALUES OF ϕ AND (α, β)

where ε = 0.0135 (i.e., 98.65% accuracy). We applied thealgorithm for different values of ϕ and equal error rates (α, β).We used an indifference region [ϕ − δ, ϕ + δ] where δ =0.001. The results are summarized in Table IX. Increasing ϕand decreasing (α, β) requires a larger number of simulations,leading to a model verification with better statistical guarantee.The model accuracy has been verified and generalized to 0.019(i.e., 98.1% accuracy). In practice, we find that ϕ = 0.95 andα = β = 0.01 often provide a good tradeoff between statisticalguarantee and computational cost.

3) Tolerance Margin in Failure Performance Bounds: Ifthe circuit specification includes a performance metric f thatshould be greater than a limit flimit (i.e., f > flimit), thenthe failure performance region is defined as f ∈ [f l, flimit].If the value f l is over-approximated (i.e., it is below the valuethat can be reached in reality), it will not affect the result ofthe yield estimation and it will slightly affect the computa-tion time. In fact, the SMT solver rapidly discards parts fromthe search space that contains no solutions. However, if it isunder-approximated (i.e., it is greater than the value that can bereached in reality), it will prevent the SMT solver from locat-ing failure regions in the parameters space and affect the finalyield estimation. In practice, we first set fl = fmin−�f , where�f = |f min − fnom|, fnom is the nominal value of f and f min isthe minimum value of f discovered during the initial presam-pling and circuit simulation step. If the SMT solver discoversfailure regions in the parameters space with performance val-ues f in the neighborhood of fl, that is f ∈ [fl, fl + 3ε], whereε is the model error, then fl should be further decreased by�f . Otherwise, the user can be highly assured that the failureperformance bounds have been conservatively characterized.

V. CONCLUSION

This paper presented a methodology for analog circuitsyield analysis. Different techniques such as parameters prun-ing, adaptive SR, and SPRT were used to build performancesmodels and verify their accuracy. We then employed an SMTsolving technique and interval arithmetic to exhaustively probethe parameters space and locate the failure regions of thecircuit operation. The yield is calculated based on the proba-bilistic volume of the located failure regions. Compared withexisting methods, the proposed method tried to handle yieldproblems with: 1) many process parameters; 2) multiple anddistinct failure regions; 3) multiple performances specification;and 4) extremely high yield rate. The experimental results on

several analog circuits show that the presented method is reli-able while leading to a simulation speedup when compared tothe brute-force MC.

The proposed method enhanced the run-time and scalabil-ity of SMT solving techniques by adopting multiple strate-gies including: 1) reduction of the SMT problem variables;2) building low complex performances models; 3) reduction ofthe SMT problem search space; and 4) adjustment of the SMTsolver resolution and solution refinement. Furthermore, thecomputational cost of the proposed surrogate modeling algo-rithm has been enhanced by reducing the number of processparameters and avoiding high polynomial degree.

Also, note that the computational cost of the modelingalgorithm may increase if the number of process parametersand the number of performance metrics largely increases. Forexample, in the case where the dimensionality is extremelyhigh, the adaptive regression must choose a set of importantpolynomial terms from numerous (e.g., millions of) possiblecandidates and, hence, the surrogate model training algorithmdescribed in this paper may become computationally unaf-fordable. In our future research, we will further study moreefficient heuristics and parallelization techniques that mayaddress this issue. We also plan to integrate the yield estima-tion method with the nominal sizing method proposed in [17]to further prove its usefulness in analog design.

REFERENCES

[1] M. Wirnshofer, Variation-Aware Adaptive Voltage Scaling for DigitalCMOS Circuits. Amsterdam, The Netherlands: Springer, 2013.

[2] B. Liu, F. V. Fernandez, and G. G. E. Gielen, “Efficient and accurate sta-tistical analog yield optimization and variation-aware circuit sizing basedon computational intelligence techniques,” IEEE Trans. Comput.-AidedDesign Integr. Circuits Syst., vol. 30, no. 6, pp. 793–805, Jun. 2011.

[3] T. Mukherjee, L. R. Carley, and R. A. Rutenbar, “Efficient handling ofoperating range and manufacturing line variations in analog cell synthe-sis,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 19,no. 8, pp. 825–839, Aug. 2000.

[4] C. Jacoboni and P. Lugli, The Monte Carlo Method for SemiconductorDevice Simulation. Vienna, Austria: Springer, 1989.

[5] S. Sun, Y. Feng, C. Dong, and X. Li, “Efficient SRAM failure rateprediction via Gibbs sampling,” IEEE Trans. Comput.-Aided DesignIntegr. Circuits Syst., vol. 31, no. 12, pp. 1831–1844, Dec. 2012.

[6] H. Niederreiter, Random Number Generation and Quasi-Monte CarloMethods. Philadelphia, PA, USA: Soc. Ind. Appl. Math., 1992.

[7] J. Yao, Z. Ye, and Y. Wang, “Importance boundary sampling for SRAMyield analysis with multiple failure regions,” IEEE Trans. Comput.-AidedDesign Integr. Circuits Syst., vol. 33, no. 3, pp. 384–396, Mar. 2014.

[8] F. Gong et al., “Quickyield: An efficient global-search based parametricyield estimation with performance constraints,” in Proc. Design Autom.Conf., Anaheim, CA, USA, pp. 392–397.

[9] X. Li, “Finding deterministic solution from underdetermined equation:Large-scale performance variability modeling of analog/RF circuits,”IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 11,pp. 1661–1668, Nov. 2010.

[10] M. Fränzle, C. Herde, T. Teige, S. Ratschan, and T. Schubert, “Efficientsolving of large non-linear arithmetic constraint systems with complexboolean structure,” J. Satisfiability Boolean Model. Comput., vol. 1,pp. 209–236, May 2007.

[11] (Jan. 2017). iSAT3. [Online]. Available: https://projects.avacs.org/projects/isat3

[12] C. Gu and J. Roychowdhury, “Yield estimation by computing probabilis-tic hypervolumes,” in Extreme Statistics in Nanoscale Memory Design.Boston, MA, USA: Springer, 2010, pp. 137–177.

[13] J. Jaffari and M. Anis, “On efficient LHS-based yield analysis of ana-log circuits,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst.,vol. 30, no. 1, pp. 159–163, Jan. 2011.

[14] A. Singhee and R. A. Rutenbar, “Why Quasi-Monte Carlo is better thanMonte Carlo or latin hypercube sampling for statistical circuit analysis,”IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 11,pp. 1763–1776, Nov. 2010.

https://projects.avacs.org/projects/isat3

https://projects.avacs.org/projects/isat3


[15] S. Sun, X. Li, H. Liu, K. Luo, and B. Gu, “Fast statistical analysis of rarecircuit failure events via scaled-sigma sampling for high-dimensionalvariation space,” IEEE Trans. Comput.-Aided Design Integr. CircuitsSyst., vol. 34, no. 7, pp. 1096–1109, Jul. 2015.

[16] L. Yin, Y. Deng, and P. Li, “Simulation-assisted formal verificationof nonlinear mixed-signal circuits with Bayesian inference guidance,”IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 32, no. 7,pp. 977–990, Jul. 2013.

[17] O. Lahiouel, M. H. Zaki, and S. Tahar, “Towards enhancing analogcircuits sizing using SMT-based techniques,” in Proc. Design Autom.Conf., San Francisco, CA, USA, 2015, pp. 1–6.

[18] H. Lin and P. Li, “Parallel hierarchical reachability analysis for analogverification,” in Proc. Design Autom. Conf., San Francisco, CA, USA,2014, pp. 1–6.

[19] T. Hastie, R. Tibshirani, and J. Friedman, The Elements of StatisticalLearning (Springer Series in Statistics). New York, NY, USA: Springer,2001.

[20] Y. Zhang, S. Sankaranarayanan, and F. Somenzi, “Sparse statisti-cal model inference for analog circuits under process variations,”in Proc. Asia South Pac. Design Autom. Conf., Singapore, 2014,pp. 449–454.

[21] M. Robnik-Sikonja and I. Kononenko, “An adaptation of Relief forattribute estimation in regression,” in Proc. Int. Conf. Mach. Learn.,Nashville, TN, USA, 1997, pp. 296–304.

[22] K. Kira and L. A. Rendell, “A practical approach to feature selec-tion,” in Proc. Int. Conf. Mach. Learn., Aberdeen, U.K., 1992,pp. 249–256.

[23] H. Zou, “The adaptive Lasso and its oracle properties,” J. Amer. Stat.Assoc., vol. 101, no. 476, pp. 1418–1429, 2006.

[24] (Jan. 2017). MATLAB. [Online]. Available: http://www.mathworks.com/[25] H. L. S. Younes, “Verification and planning for stochastic processes with

asynchronous events,” Ph.D. dissertation, Comput. Sci. Dept., CarnegieMellon Univ., Pittsburgh, PA, USA, 2005.

[26] A. Wald, “Sequential tests of statistical hypotheses,” Ann. Math. Stat.,vol. 16, no. 2, pp. 117–186, Jun. 1945.

[27] S. M. Rump, Developments in Reliable Computing. Amsterdam,The Netherlands: Springer, 1999.

[28] P. R. Bevington and D. K. Robinson, Data Reduction and Error Analysisfor the Physical Sciences. New York, NY, USA: McGraw-Hill, 2003.

[29] L. Dolecek, M. Qazi, D. Shah, and A. Chandrakasan, “Breaking thesimulation barrier: SRAM evaluation through norm minimization,” inProc. Int. Conf. Comput.-Aided Design, San Jose, CA, USA, 2008,pp. 322–329.

[30] E. Seevinck, F. J. List, and J. Lohstroh, “Static-noise margin analysisof MOS SRAM cells,” IEEE J. Solid-State Circuits, vol. 22, no. 5,pp. 748–754, Oct. 1987.

Ons Lahiouel (S’17) received the Bachelor’s andMaster’s degrees in Telecommunication Systemsfrom the National Engineering School of Tunis,Tunisia, in 2011 and 2012, respectively, andthe Ph.D. degree in electrical engineering fromConcordia University, Montréal, QC, Canada,in 2017. She continued her graduate studies in thefield of analog and mixed signal systems in theHardware Verification Group, Concordia University,under the supervision of Prof. S. Tahar. Her currentresearch interests include design and verification of

analog and mixed-signal integrated circuits and formal hardware verification.

Mohamed H. Zaki (M’05) received the bachelor’sdegree in electrical engineering from Ain ShamsUniversity, Cairo, Egypt, in 2000, and the mas-ter’s and Ph.D. degrees from Concordia University,Montreal, QC, Canada, in 2002 and 2008, respec-tively. He continued his graduate studies with theHardware Verification Group, Concordia University,under the supervision of Prof. S. Tahar.

He then conducted Post-Doctoral training withthe Department of Computer Science, University ofBritish Columbia, Vancouver, BC, Canada, where he

is currently a Research Fellow in intelligent transportation systems. He hasbeen a Consultant at the start-up company Innovia Technologies, Vancouver,since 2010.

Sofiène Tahar (M’96–SM’07) received the Diplomadegree in computer engineering from the Universityof Darmstadt, Darmstadt, Germany, in 1990, andthe Ph.D. (Hons.) degree in computer science fromthe University of Karlsruhe, Karlsruhe, Germany, in1994.

He is currently a Professor and Research Chairin Formal Verification of Systems-on-Chip with theDepartment of Electrical and Computer Engineering,Concordia University, Montreal, QC, Canada, wherehe is also the Founder and the Director of the

Hardware Verification Group. He has made contributions and published papersin the areas of formal hardware verification, system-on-chip verification,AMS circuit verification, and probabilistic, statistical, and reliability analysisof systems.

Prof. Tahar was a recipient of the University Research Fellow upon receiv-ing the Concordia University’s Senior Research Award in 2007. He is a SeniorMember of ACM and a Professional Engineer in the Province of Quebec.

http://www.mathworks.com/

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