IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008 2177

A Large Swing, 40-Gb/s SiGe BiCMOS Driver WithAdjustable Pre-Emphasis for Data Transmission Over

75 � Coaxial CableRicardo Andres Aroca and Sorin P. Voinigescu, Senior Member, IEEE

Abstract—A fully differential 40-Gb/s cable driver with ad-justable pre-emphasis is presented. The circuit is fabricated ina production 0.18 m SiGe BiCMOS technology. A distributedlimiting architecture is used for the driver employing high-speedHBTs in the lower voltage predriver, and a high-breakdownMOS-HV-HBT cascode, consisting of a 0.18 m n-channelMOSFET and a high-voltage HBT (HV-HBT), for the high voltageoutput stages. The circuit delivers up to 3.6 V peak-to-peak perside into a 75 � load with variable pre-emphasis ranging from0 to 400%. S-parameter measurements show 42 dB differentialsmall-signal gain, a 3-dB bandwidth of 22 GHz, gain peakingcontrol up to 25 dB at 20 GHz and input and output reflectioncoefficients better than -10 dB up to 40 GHz. Additional featuresof the driver include output amplitude control (from 1 �� to3.6 �� per side), pulse-width control (35% to 65%) and anadjustable input dc level (1.1 V to 1.8 V) allowing the circuit tointerface with a SiGe BiCMOS or MOS-CML SERDES. Thetransmitter is able to generate an eye opening at 38 Gb/s after10 m of Belden 1694A coaxial cable which introduces 22 dB ofloss at 19 GHz. Measurement results also demonstrate that thetransmitter IC operates as a standalone equalizer for 10-Gb/sdata transmission over 40 m of Belden cable without the need forreceiver equalization.

Index Terms—Amplitude control, cable equalizers, high speeddata communication, modulator drivers, optical fiber communica-tion, pre-emphasis, SiGe BiCMOS.

I. INTRODUCTION

E VOLVING consumer applications such as HDTV and dig-ital cinema are driving communication and video distribu-

tion standards to multi-gigabit per second rates. As bit rates in-crease, loss (caused by skin effect and dielectric loss) in coppercables causes significant attenuation of the transmitted data athigh frequencies. A critical success factor for the serial digitalinterface (SDI) [1] has been its ability to evolve over time whileretaining the use of the installed, bandwidth limited, coaxialcable infrastructure [2].

Belden 1694A coaxial cable is commonly used for transmis-sion of 3-Gb/s data and HDTV studio signals [3]. To distribute40-Gb/s data along this cable requires a transceiver (TXRX) IC

Manuscript received March 3, 2008; revised May 13, 2008. Current versionpublished October 8, 2008. This work was supported by Gennum Corpora-tion and NSERC. Fabrication was provided by Jazz Semiconductor and MarcoRacanelli.

The authors are with the Edward S. Rogers Sr. Department of Electrical andComputer Engineering, University of Toronto, Toronto, ON, M5S 3G4, Canada(e-mail: [email protected]).

Digital Object Identifier 10.1109/JSSC.2008.2002928

capable of equalizing cable losses anywhere from 15 dB over10 m, up to 60 dB over 50 m. An adjustable transmitter (TX)equalization approach is developed herein to address this appli-cation.

Unlike in parallel channel chip-to-chip communication, thecoaxial cable provides a well-shielded and crosstalk-immunechannel. Therefore, the amount of TX equalization is not con-strained by crosstalk and should be maximized. Demonstrationsof high-speed TX equalization of attenuation-limited channelsinclude feed forward equalizers (FFE) at 10 Gb/s [4], digitalpre-emphasis up to 25 Gb/s [5], and analog pre-emphasis usingtransformer boosting and inductive peaking techniques at 8 Gb/s[6]. Transmitters with large single-ended output swings, up to3 in GaAs p-HEMT [7], 3.5 in SiGe [8], and 5.65in InP [9] technologies, without pre-emphasis control have beenreported. To the best of the authors’ knowledge, large swingand adjustable TX equalization at 40 Gb/s has not been demon-strated to date.

This work describes the first fully differential 40-Gb/s SiGeBiCMOS cable driver, with 3 swing per side and adjustablepre-emphasis. The driver employs 0.18 m n-channel MOS-FETs and high-breakdown HBTs in the high-voltage distributedoutput stage, and high-speed HBTs in the predriver. Togetherwith the equalizers described in [10] and [11], the driver rep-resents a key milestone towards the single-chip integration ofa 40-Gb/s transceiver with equalization aimed at compensatingup to 50 dB of loss over 75- coaxial cable. In addition, themeasured characteristics of the driver in a 50- environmentindicate that it can also be used as an electro-absorption (EA)modulator driver in a 40-Gb/s optical communication link.

The paper is organized as follows. Section II presents the cir-cuit design methodology. Fabrication and layout are next de-scribed in Section III and are followed by experimental veri-fication of the driver in Section IV. A serial link cable demois presented in Section V where the driver is used to transmit10- to 40-Gb/s data over different lengths of standard Beldencoaxial cable. Conclusions are given in Section VI.

II. CIRCUIT DESIGN

A block diagram of the large swing cable driver is illustratedin Fig. 1. The circuit architecture follows that of the GaAsp-HEMT driver reported in [7], and consists of a six-stagelumped predriver with duty cycle control (DCC) and vari-able amplitude control, followed by a seven-stage distributedamplifier (DA). However, unlike [7], 0 to 400% ( 25 dBgain peaking) pre-emphasis control is also implemented. Thedriver is fabricated in Jazz Semiconductor’s 0.18 m SiGe

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2178 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 10, OCTOBER 2008

Fig. 1. Driver architecture schematic with distributed adjustable pre-emphasis. Insets show further details in the lumped predriver chain and in each DA section.

TABLE I0.18-�m SiGe BiCMOS TRANSISTOR SMALL-SIGNAL MODEL PARAMETERS AND BREAKDOWN VOLTAGES

The emitter area of the HS- and HV-HBTs is � � �� m .

The width of the n-channel MOSFET is 80 �m with 2 �m finger width.

� is reported in fF per micron of emitter length because the exact collector-to-substrate junction area is unknown

BiCMOS technology [12], which offers 0.18 m MOSFETs,high-speed HBTs (HS-HBT), and high breakdown voltageHBTs (HV-HBT). The small signal transistor parameters ofeach device are compared in Table I.

A. Driver Topology

The target output swing for this application is 5 per sidewhen driving the 75- coaxial cable. That specification leads toa tail current mA in thelarge-voltage output switch of the driver. In a cascode output

stage, the common-base transistor experiences a dc collector-to-emitter voltage equal to at least

(1)

where is 5 per side and is the collector-to-emitter voltage that ensures the minimum slew rate necessaryfor 40-Gb/s operation. is topology dependent, and maybe determined by examining the deterministic jitter in the sim-ulated eye diagram of the output stage under different bias

AROCA AND VOINIGESCU: LARGE SWING, 40-Gb/s SiGe BiCMOS DRIVER WITH ADJUSTABLE PRE-EMPHASIS FOR DATA TRANSMISSION 2179

conditions for the common-base output device. is ini-tially approximated by for the HS-HBT. Itfollows that the HS-HBT requires a nominal dc collector-to-emitter voltage of 2.8 V. When the output swing reaches itspeak, the rises to 5.3 V. Although these values are belowthe rated of the device, a long string of 1’s will stress thecommon-base HS-HBT beyond its reliability limit [13]. There-fore, the higher breakdown voltage SiGe HBT (HV-HBT) isneeded at the output of the driver.

Unfortunately, the HV-HBT transistor has low andvalues of 75 GHz and 90 GHz respectively, and a low peak

current density of 3 mA m . A lumped outputstage implemented as a cascode inverter with a HV-HBT as thecommon-base device and biased for maximum speed [14], hasa small-signal bandwidth given by

(2)

where and are the HV-HBT collector-to-sub-strate and base-to-collector capacitances per m of emitterarea,1 respectively, is the tail current in the differentialoutput stage, and is the output load capacitance. In (2) it wasassumed that the output stage is dc-coupled and matched to thecharacteristic impedance of the channel . Using the valuesin Table I along with mA and , (2)predicts a small-signal bandwidth of only 12 GHz for a lumpedrealization of the driver. Therefore, a distributed amplifiertopology will be required to meet the target specification at40 Gb/s with HV-HBTs.

A search of existing publications indicates that it is difficultfor the gain of a large-swing and large bandwidth DA to exceed12 dB. To meet the target output swing specification of 5per side, the signal at the input of the DA must be larger than 1.2

per side. This dictates the choice of input device in each DAsection. The HS-HBT is preferred due to its high speed, how-ever, since its is only 1.3 V, emitter degeneration must beemployed. Degeneration significantly reduces the transconduc-tance and the gain of the DA stage and introduces a significantdc voltage drop. Alternatively, a 0.18 m n-channel MOSFETcan be operated reliably with 1.2 at its gate without the needfor source degeneration [15]. Furthermore, unlike the HBT,2 theinput capacitance of a MOSFET is constant over a wide rangeof tail current values [17]. This is important in a DA since thecapacitance loading the input transmission line will remain con-stant when changing the DA stage bias current to implementamplitude and pre-emphasis control. As a result, the bandwidthand phase-linearity of the DA will also remain unaffected.3 TheMOS-HV-HBT cascode adds high-voltage to the list of provenbenefits of the MOS-HBT cascode which includes a low input

1When using (2), the value of � reported in Table I must be divided bythe emitter width �� m� to ensure that the units are consistent with� which is reported in ��m .

2The variation in input capacitance is less when the HBT is degenerated.3Assuming the output impedance of each DA cell is kept constant by ensuring

that the emitter current in the HV-HBT common-base device does not change.This is accomplished by introducing offset currents.

time constant [16] and excellent stability [18]. Although the0.18 m n-channel MOSFET has low and values ofonly 50 GHz and 75 GHz, respectively, the next subsections willdemonstrate that the bandwidth of the MOS-HV-HBT cascodeis sufficient for realizing a robust, large-swing, 40-Gb/s DA withwaveshape control.

B. Core DA Section

In order to maximize the DA bandwidth, the output am-plitude and pre-emphasis control functions are implementedwithin each DA section, as illustrated in Fig. 1 and in moredetail in Fig. 2. The input signal is applied simultaneously toa pre-emphasis block and to a MOS-HV-HBT differential pair( , , and ), whose tail current is varied to controlthe output amplitude. The former is comprised of a RC-differ-entiator followed by a differential pair realized with HS-HBTtransistors and , and degeneration resistor as shownin Fig. 2. The pre-emphasis path and the main path are com-bined at the low-impedance nodes connecting the drains of ,

, collectors of , and the emitters of the common-baseHV-HBT transistors , . This signal-summation schemeresults in minimal degradation of the DA bandwidth whilemaximizing the range of output amplitudes and pre-emphasisthat can be controlled. Finally, offset current sources, added atthe low-impedance node of the cascode, ensure that the biascurrents in transistors and remain constant for differentoutput amplitude and pre-emphasis settings.

1) Bias Circuit for Pre-Emphasis and Amplitude Control:The degree of pre-emphasis is controlled by steering an ad-justable current, , between the main and pre-em-phasis paths, such that , as shown inFig. 2. The associated bias control circuit is illustrated in Fig. 3.Two external voltages, and , control the outputamplitude and the pre-emphasis of the entire DA. gener-ates , which is mirrored and split into andby the steering voltage . and are mir-rored independently to each DA section to control the refer-ence currents and , respectively. For brevity, only the dis-tribution of the pre-emphasis current is shown in Fig. 3.The extreme operating conditions of the driver correspond to

and for maximum swing with no pre-em-phasis, and and for max-imum pre-emphasis around a minimum dc output level definedas , where is the number of DAsections and is the characteristic impedance of the channel.

2) Source Follower—Emitter Follower (SF-EF) Stage Designand Matching Networks: The role of the broadband matchinginductors and the SF-EF stage is to maximize the bandwidthof the DA and to ensure that the conditions for phase synchro-nization and dispersionless operation along the input and outputtransmission lines are satisfied [19]–[23]. As a result, the gainflatness and phase linearity of the DA are preserved. These con-ditions are satisfied when

(3)


Fig. 2. DA section schematic.

Fig. 3. Simplified bias circuit illustrating how bias currents for pre-emphasis and amplitude control are distributed to the DA sections. � � � in this design.

and

(4)

where , , and are the RLGC parameters ofthe input (gate) and output (drain) transmission lines per unitlength, and are the physical lengths of transmission linebetween each DA section, and are the total lumped in-ductances used for matching at the input and output of eachDA section respectively, and and are theinput and output capacitances of each DA section respectively.The SF-EF stage and matching networks in Fig. 2 are designedto satisfy (3) and (4), in the ideal case, over the entire band-width of the driver. The role of the SF-EF stage is to bufferthe large input capacitance introduced by the main path and by

the pre-emphasis path, , from the input t-line. Ideally,, so that and (3) and (4)

are readily satisfied. The SF-EF must be carefully designed tosimultaneously satisfy (3) and (4) without degrading the phaselinearity of the DA as a result of excessive negative resistanceon the input transmission line [24]. The matching networks atthe input and at the output of each DA section are implementedas m-derived T-sections for maximum bandwidth[17]. The matching networks mitigate the impact ofand on the characteristic impedance of the input andoutput transmission lines of the DA, as seen by (3). The valuesfor and are calculated from (3) and (4) and in this designare equal to 260 pH and 200 pH, respectively.

C. Design for Maximum Pre-Emphasis

The transconductance of the core DA section depicted inFig. 2, defined as , and the pre-emphasis boost


in the transconductance of the core DA section, defined as, can be cast as (5) and (6), respectively.

(5)

(6)

where is the transconductance of , is the ef-fective transconductance of transistor when degenerated byresistor , and is the total input capacitance lookinginto the base of in Fig. 2. The pre-emphasis boost is propor-tional to the ratio . Thus pre-emphasis is max-imized by using a MOSFET with low on the main path,and a HBT with large on the pre-emphasis path with min-imal degeneration. Equation (6) is used to capture the designtrade-offs for the pre-emphasis path. is defined by thetotal output current, the number of DA sections and the valueof the degeneration resistor in Fig. 2. Considering its im-pact on the input capacitance of the DA section, is designedto minimize the insertion loss to the pre-emphasis path and tomaximize the passband. The high pass filter cut-off frequency isdesigned for optimal pre-emphasis by maximizing the expres-sion . Initial values for

and in the iterative optimization process may be approx-imated by and ,where is the small-signal bandwidth of the cascadeof the predriver and DA, and is the bandwidth ofthe coaxial cable.

In this 0.18 m SiGe BiCMOS technology, simulations showthat using seven stages maximizes the gain of this 75 DA. Theoptimized circuit parameters for this design are given in Fig. 2.Using these values, the analytical expression for the transcon-ductance of the DA section, described by (5), can be employedto calculate the overall voltage gain of the 7-stage DA underlow-loss conditions. The analytical gain of the DA is comparedto Spectre simulations in Fig. 4 for different pre-emphasis set-tings. The good agreement shown indicates that the analyticalmodel can be a useful tool for the design of the DA, linking thecircuit parameters to the pre-emphasis boost.

D. Predriver

The block diagram of the predriver is shown in Fig. 1. Asmentioned, it must deliver at least 1.2 per side into thematched 75- load formed by the input transmission line of theDA. This condition sets the tail current in the last inverting stageof the driver to 32 mA. The input of the predriver must interfacewith either MOS-CML or BiCMOS CML circuits. As a result,it is designed to accept an input signal as low as 150 perside at an input DC level ranging from 1.1 V to 1.8 V. The input

Fig. 4. Analytical model versus Spectre simulated gain of the seven-stage DAwith different pre-emphasis settings. Settings for maximum gain are not shown.

stage features on-chip 50- resistors, spiral inductors and min-imum size devices with 3- mA tail current to provide good inputmatching over a broad bandwidth without the use of emitter fol-lowers (EF). In order to scale up the current driving capabilityof the predriver from 3 mA in its input stage, to 32 mA in itsoutput stage, while maintaining a 3-dB bandwidth exceeding30 GHz, six stages are required. As seen in Fig. 1, all stagesemploy shunt-peaking inductors in order to extend the band-width of the predriver. To further maximize the bandwidth of thepredriver and to save power, duty-cycle control (DCC) is imple-mented at the low-impedance cascode node of the third invertingstage, as shown in Fig. 1. In the later stages of the predriverwhere the tail current exceeds 10 mA, MOS-HBT cascodes areused to avoid the potential instabilities that plague high-currentHBT-cascodes. Stage 5 uses a common-mode resistor to maxi-mize the headroom in the output stage of the predriver. Further-more, a common base HV-HBT device is needed in the outputstage of the predriver in order to interface with the DA that op-erates from a higher supply voltage. The last stage is terminatedwith resistors that are matched to the characteristic impedanceof the input transmission lines of the DA.

III. LAYOUT AND FABRICATION

The chip was fabricated in Jazz Semiconductor’s SBC18HX0.18 m SiGe BiCMOS process [12]. The backend features 6metal layers with thick aluminum top metal. MIM capacitorsand polysilicon resistors are also available. The chip die photois reproduced in Fig. 5. It occupies an area of 1.2 mm 2.5 mm.The key layout design considerations were (i) minimization oflayout parasitics, (ii) power and bias distribution to each DAcell, (iii) isolation, and (iv) stability.

The fully differential DA features 75- input and outputtransmission lines realized in the thick top metal of the tech-nology, with “Metal 2” as the ground plane. As in [10], thisallows for the routing of bias and control lines below the groundplane. The input and output lines are meandered symmetricallyon both sides of the DA. All transmission lines are shieldedby Faraday-cage style isolation structures realized with ‘Metal1’ to ‘Metal 6’ shunted together. The isolation structures areclearly visible in Fig. 5. In this technology, 75- microstriptransmission lines require thin line widths that come close to


Fig. 5. Driver microphotograph. Total area is 2.5 mm � 1.2 mm, includingpads.

Fig. 6. DA section layout illustrating bias distribution network. Main path(LPF) is indicated with a solid line, and pre-emphasis path (HPF) is shownwith a dashed line.

violating electromigration rules when the dc current of the DApasses through them. Therefore, transmission line attenuationis a primary concern and must be accurately modeled. AnsoftHFSS was used to generate the S-parameters for a long andshort length of transmission line from which a scalable RGLCcircuit model was extracted [25] for transient circuit simula-tions.

The layout of a DA stage is illustrated in Fig. 6. The primarygoal was to reduce the footprint occupied by active devices. Themain high-speed signal path is represented as a solid line, andthe pre-emphasis path is shown as a dashed line. The bias volt-ages for each block are generated and decoupled locally withemphasis on symmetry and on minimizing line inductance.

IV. EXPERIMENTAL RESULTS

The circuit requires three supply voltages of 4 V, 6 V, and 8V, and has a worst case power consumption of 3.6 W whichcorresponds to the maximum output swing. All time-domainand frequency-domain measurements were conducted on waferin a 50 environment.

S-parameters were measured up to 67 GHz for all pre-em-phasis and output amplitude bias conditions, using a Wiltron360B Vector Network Analyzer. S-parameters for varyingoutput amplitude with no pre-emphasis are collected in

Fig. 7. Measured versus simulated S-Parameters showing (a) 10 dB amplitudecontrol and 36 dB single-ended gain (42 dB differential) and (b) controllablepre-emphasis with up to 25 dB of peaking. Simulated S21 data corresponds tosetting for maximum gain in (a) and maximum pre-emphasis in (b).

Fig. 7(a) and compared to simulation results. The driver ex-hibits an overall small-signal gain of 36 dB per side (42 dBdifferentially) when DC-coupled to an external 75 load bymeans of a bias-T. A 3-dB bandwidth of 22 GHz is observedwhile achieving up to 10 dB of output amplitude control.Fig. 7(b) shows the measured S-parameters for various pre-em-phasis control settings. The maximum pre-emphasis reaches 25dB at 20 GHz, in good agreement with the simulated maximumof 23 dB. The input and output return loss are insensitive tochanges in the amplitude and pre-emphasis settings. and

are better than 10 dB up to 40 GHz, as seen in Fig. 7,while the isolation exceeds 50 dB up to 45 GHz.

The real and imaginary parts of the output impedance weremeasured and reported in [26]. The measured DC outputimpedance of 82 is close to the 75- design target. Thedifference is attributed to the DC resistance of the microstripT-line, to the resistance of the inductors in the matching net-works and to process variability.

Eye diagrams were captured using an Agilent 86100DCDCA-J oscilloscope and an Agilent E8257D signal source.Figs. 8 and 9 show 3:1 ( 10 dB) output amplitude controlat 40 Gb/s for a multiplexed PRBSinput pattern. The driver is capable of output swings ranging


Fig. 8. Measured and simulated 40-Gb/s eye diagram with 3� output swingper side at 25 C.

Fig. 9. 40 Gb/s eye diagram with 1 � output swing per side at 25 C.

from 1.0 to 3.0 per side, for a single-ended inputsignal of 300 at room temperature. As shown in Fig. 8,there is close agreement between the measured and simulated3.0 eye diagrams. Similarly, measured and simulated40-Gb/s eye diagrams with 400% pre-emphasis at 25 C areshown in Fig. 10. The vertical asymmetry in the eye-diagramoccurs when the DA is biased for maximum pre-emphasis.Under this bias condition, the current in Fig. 2 is steeredto the pre-emphasis transistors and , resulting in asignificant drop in the current density of transistors and

. This degrades the and of the MOS differentialpair resulting in different rise and fall times in the eye diagram.The driver continues to function correctly even at 125 C,but with lower gain and lower output swing. A 40-Gb/s eyediagram captured at 125 C with 180% pre-emphasis is shownin Fig. 11. S-parameter simulations of the driver after extractionof RC layout parasitics indicate that the maximum achievablepre-emphasis boost at 125 C is 18 dB, compared to 23 dB at25 C. Duty cycle control of 35% to 65% was also achievedas reported in [26]. Although the target output swing for thedriver was 5 , when measured in a 50- environment, theswing is limited to 4 per side. To estimate the voltageswing in a 75- environment, the voltage swings displayedin all the eye diagram measurements should be multipliedby 1.25. Therefore, it is estimated that the maximum outputamplitude is at least 3.6 per side, as shown in Fig. 12 at38 Gb/s. The corresponding bathtub curve, generated by theAgilent oscilloscope, in Fig. 13 indicates a timing margin of

Fig. 10. 40 Gb/s eye diagram with 400% pre-emphasis at 25 C.

Fig. 11. 40-Gb/s eye diagram with 180% pre-emphasis at 125 C.

Fig. 12. 38-Gb/s eye diagram illustrating a maximum driver output swing of3.6 � per side or 7.2 � when taken differentially.

nearly 0.5UI at an extrapolated BER of , with a totalpeak-to-peak jitter of 13.66 ps.

V. SERIAL LINK DEMO OVER BELDEN 1694A COAXIAL CABLE

The driver was designed for 40-Gb/s data transmission overstandard 75- Belden 1694A coaxial cable. The test setupfor the cable demo is shown in Fig. 14. One of the differen-tial outputs of the driver is connected to the coaxial Beldencable via a cascade of cables and connectors, consisting ofa 67-GHz bias-T, a K-to-SMA transition, two SMA cablesand an SMA-to-BNC transition. These transitions introducereflections that impact high data rate transmission. The other


Fig. 13. Bathtub curve for a 3.6� single-ended output signal from the driverat 38-Gb/s. Input signal is a multiplexed �� PRBS pattern.

Fig. 14. Test setup for the cable equalization demo.

Fig. 15. Measured loss of different lengths of coaxial cable including test setupcables and transitions.

differential output is connected to the oscilloscope through a67 GHz cable. This allows the input and the output from theBelden cable to be viewed simultaneously on the oscilloscope.

The measured S-parameters for 10 m, 20 m, 30 m, 40 m and50 m of coaxial Belden cable are plotted in Fig. 15. The 40-mlong cable was realized by cascading the 10-m long and the30-m long sections of cable.

The 10-Gb/s eye diagrams measured at the input and after the40-m Belden cable are shown in Fig. 16(a) when the driver hasno pre-emphasis, and in Fig. 16(b) when optimal pre-emphasisis applied, respectively. The optimal pre-emphasis setting wasfound by maximizing the eye opening at the output of the cable.As seen in Fig. 16(a), the eye is completely closed after trav-elling through 40 m of cable. When pre-emphasis is applied,as seen at the bottom of Fig. 16(b), the 24 dB of channel loss at

Fig. 16. 10-Gb/s eye diagrams measured at the input of the 40-m Belden cableand after the 40-m Belden cable (a) when the driver has no pre-emphasis, and(b) when optimal pre-emphasis is applied. The cable loss at 5 GHz is 24 dB.

5 GHz is equalized and the eye is opened after travelling through40 m of coaxial cable. Similar measurements were conducted at20 Gb/s over 30 m of coaxial cable, and at 30 Gb/s and 38 Gb/sover 10 m of coaxial cable. At 20 Gb/s, the circuit can produce apartial eye opening after transmitting data across 30 m of coaxialcable as seen in Fig. 17. The measured loss for this experimentwas 29 dB at 10 GHz. At 30 Gb/s and at 38 Gb/s the driverwas able to partially open the eye after passing through 10 mof cable, where the loss at the Nyquist frequency is 18 dB and23 dB, respectively. The 38-Gb/s eye diagrams are presented inFig. 18. The driver performance is summarized in Table II.

VI. CONCLUSION

A 40-Gb/s differential distributed cable driver IC usingn-channel MOSFETs and HV-HBTs has been designed andfabricated in a production 0.18 m SiGe BiCMOS technologyand is intended for data transmission over standard 75 coaxialcable. To the best of the authors’ knowledge, this work marksthe first 40-Gb/s driver with large output swing andadjustable pre-emphasis. The IC achieves a maximum swing of3.6 per side and features adjustable pre-emphasis, outputamplitude control and duty-cycle control. The worst case powerconsumption is 3.6 W. The driver operates as a standalone10-Gb/s equalizer capable of compensating up to 24 dB of lossover 40 m of low-quality Belden cable. For data distributionbeyond 10 Gb/s up to 40 Gb/s, a combination of FFE andDFE similar to the published work in [10] and [11] must beimplemented in the receiver. The driver is designed to interface


Fig. 17. 20-Gb/s eye diagrams measured at the input of the 30-m Belden cable(bottom) and after the 30-m Belden cable (top) when optimal pre-emphasis isapplied. The cable loss at 10 GHz is 29 dB.

Fig. 18 38-Gb/s eye diagrams measured at the input of the 10-m Belden cable(bottom) and after the 10-m Belden cable (top) when optimal pre-emphasis isapplied. The cable loss at 19 GHz is 22 dB.

TABLE IILARGE-SWING DRIVER PERFORMANCE SUMMARY

At 20-, 30- and 38-Gb/s, the driver is only capable of partially opening theeye after transmitting over the indicated length of cable.

with MOS-CML circuits and operates reliably with DC input

levels down to 1.1 V. Measurements indicate that the circuitcan also be used as a 50- EA modulator driver in 40-Gb/soptical communication links.

ACKNOWLEDGMENT

The authors would like to acknowledge CMC and Jaro Pris-tupa for CAD support.

REFERENCES

[1] SMPTE 259M-2006—Television. SDTV Digital Signal/Data-SerialDigital Interface. [Online]. Available: www.smpte.org

[2] J. Hudson and N. Seth-Smith, “3G: The evolution of the Serial Dig-ital Interface (SDI),” SMPTE Motion Imaging J. Nov. 2006 [Online].Available: www.smpte.org

[3] SMPTE 424M-2006—Television. 3 Gb/s Signal/Data Serial Interface.[Online]. Available: www.smpte.org

[4] J. F. Bulzacchelli, M. Meghelli, S. V. Rylov, W. Rhee, A. V. Rylyakov,H. A. Ainspan, B. D. Parker, M. P. Beakes, A. Chung, T. J. Beukema, P.K. Pepeljugoski, L. Shan, Y. H. Kwark, S. Gowda, and D. J. Friedman,“A 10-Gb/s 5-tap DFE/4-tap FFE transceiver in 90-nm CMOS tech-nology,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2885–2900,Dec. 2006.

[5] P. Westergaard, T. O. Dickson, and S. P. Voinigescu, “A 1.5-V,20/30-Gb/s CMOS backplane driver with digital pre-emphasis,” inIEEE Custom Integrated Circuits Conf. Dig., Orlando, FL, Oct. 2004,pp. 23–26.

[6] J. Kim, H. Hatamkhani, and K. C.-K. Yang, “A large swing trans-former-boosted serial link transmitter with � � swing,” IEEE J.Solid-State Circuits, vol. 42, no. 5, pp. 1131–1142, May 2007.

[7] D. S. McPherson, F. Pera, M. Tazlauanu, and S. P. Voinigescu, “A3 V fully differential distributed limiting driver for 40-Gb/s opticaltransmission systems,” IEEE J. Solid-State Circuits, vol. 38, no. 9, pp.1485–1496, Sep. 2003.

[8] G. Freeman, M. Meghelli, Y. Kwark, S. Zier, A. Rylyakov, M. A.Sorna, T. Tanji, O. M. Schreiber, K. Walter, J. Rieh, B. Jagannathan,A. Joseph, and S. Subbanna, “40-Gb/s circuits built from a 120-GHz� SiGe technology,” IEEE J. Solid-State Circuits, vol. 37, no. 9, pp.1106–1114, Sep. 2002.

[9] Y. Baeyens, N. Weimann, P. Roux, A. Leven, V. Houtsma, R. F. Kopf,Y. Yang, J. Frackoviak, A. Tate, J. S. Weiner, P. Paschke, and C. Young-Kai, “High gain-bandwidth differential distributed InP D-HBT driveramplifiers with large (11.3 � ) output swing at 40 Gb/s,” IEEE J.Solid-State Circuits, vol. 39, no. 10, pp. 1697–1705, Oct. 2004.

[10] A. Hazneci and S. P. Voinigescu, “A 49-Gb/s, 7-tap transversal filterin 0.18 �m SiGe BiCMOS for backplane equalization,” in IEEE CSICDig., Oct. 2004, pp. 101–104.

[11] A. Garg, A. C. Carusone, and S. P. Voinigescu, “A 1-tap 40-Gbslookahead decision feedback equalizer in 0.18 �m SiGe BiCMOStechnology,” IEEE J. Solid-State Circuits, vol. 41, no. 10, pp.2224–2232, Oct. 2006.

[12] M. Racanelli et al., “Ultra high speed SiGe NPN for advanced BiCMOStechnology,” in IEEE IEDM Tech. Dig., Dec. 2001, pp. 336–339.

[13] M. Rickelt, H.-M. Rein, and E. Rose, “Influence of impact-ioniza-tion-induced instabilities on the maximum usable output voltage ofSi-bipolar transistors,” IEEE Trans. Electron Devices, vol. 48, no. 4,pp. 774–783, Apr. 2001.

[14] H.-M. Rein and M. Moller, “Design considerations for very-high-speedSi-bipolar IC’s operating up to 50 Gb/s,” IEEE J. Solid-State Circuits,vol. 31, no. 8, pp. 1076–1090, Aug. 1996.

[15] T. Yao, M. Q. Gordon, K. K. W. Tang, K. H. K. Yau, M.-T. Yang, P.Schvan, and S. P. Voinigescu, “Algorithmic design of CMOS LNAsand PAs for 60-GHz radio,” IEEE J. Solid-State Circuits, vol. 42, no.5, pp. 1044–1057, May 2007.

[16] T. O. Dickson, R. Beerkens, and S. P. Voinigescu, “A 2.5-V, 45-Gb/sdecision circuit using SiGe BiCMOS logic,” IEEE J. Solid-State Cir-cuits, vol. 40, no. 4, pp. 994–1003, Apr. 2005.

[17] T. O. Dickson, K. H. K. Yau, T. Chalvatzis, A. Mangan, R. Beerkens,P. Westergaard, M. Tazlauanu, M. T. Yang, and S. P. Voinigescu, “Theinvariance of characteristic current densities in nanoscale MOSFETsand its impact on algorithmic design methodologies and design portingof Si(Ge) (Bi)CMOS high-speed building blocks,” IEEE J. Solid-StateCircuits, vol. 41, no. 8, pp. 1830–1845, Aug. 2006.

[18] S. P. Voinigescu, R. Beerkens, T. O. Dickson, and T. Chalvatzis,“Design methodology and applications of SiGe BiCMOS cascodeopamps with up to 37-GHz unity gain bandwidth,” in IEEE CompoundSemiconductor Integrated Circuits Symp. Tech. Dig., Nov. 2005, pp.283–286.

[19] T. T. Y. Wong, Fundamentals of Distributed Amplification. London,U.K.: Artech House, 1993.


[20] Y. Ayasli, R. L. Mozzi, J. L. Vorhaus, L. D. Reynolds, and R. A. Pucel,“A monolithic GaAs 1–13 GHz traveling-wave amplifier,” IEEE Trans.Microw. Theory Tech., vol. 30, no. 7, pp. 976–981, Jul. 1982.

[21] E. L. Ginzton, W. R. Hewlett, J. H. Jasberg, and J. D. Noe, “Distributedamplification,” Proc. IRE, vol. 36, pp. 956–959, Aug. 1948.

[22] W. H. Horton, J. H. Jasberg, and J. D. Noe, “Distributed amplifiers:Practical considerations and experimental results,” Proc. IRE, vol. 38,pp. 748–753, Jul. 1950.

[23] J. B. Beyer, S. N. Prasad, R. C. Becker, J. E. Nordman, and G. K. Ho-henwarter, “MESFET distributed amplifier design guidelines,” IEEETrans. Microw. Theory Tech., vol. 32, no. 3, pp. 268–275, Mar. 1984.

[24] K. W. Kobayashi, R. Esfandiari, and A. K. Oki, “A novel HBT dis-tributed amplifier design topology based on attenuation compensationtechniques,” IEEE Trans. Microw. Theory Tech., vol. 42, no. 12, pp.2583–2589, Dec. 1994.

[25] W. R. Eisenstadt and Y. Eo, “S-parameter-based IC interconnect trans-mission line characterization,” IEEE Trans. Compon., Hybrids, Manu-fact. Technol., vol. 15, no. 4, pp. 483–490, Aug. 1992.

[26] R. A. Aroca and S. P. Voinigescu, “A large swing 40-Gb/s SiGeBiCMOS driver with adjustable pre-emphasis for data transmissionover 75 � coaxial cable,” in Proc. IEEE CSICS, Oct. 2007, pp.169–172.

Ricardo Andres Aroca received the B.A.Sc. (Hons)degree in electrical engineering from the Universityof Windsor, Canada, and the M.A.Sc. degree from theUniversity of Toronto, Canada, in 2001 and 2004, re-spectively.

In 2000, he worked as an intern with NortelNetworks in the Microelectronics Department andmore recently in 2008 with Alcatel-Lucent in theHigh-Speed Electronics Design Research Group,Bell Laboratories, Murray Hill, NJ. He is currentlyworking toward the Ph.D. degree at the University

of Toronto where his research interests lie in the area of equalization and clockand data recovery techniques for 40- to 100-Gb/s wireline integrated circuits.

Mr. Aroca received the Natural Sciences and Engineering Research Councilof Canada (NSERC) Postgraduate Scholarship award in 2002.

Sorin P. Voinigescu (SM’02) received the M.Sc. de-gree in electronics from the Polytechnic Institute ofBucharest, Romania, in 1984, and the Ph.D. degreein electrical and computer engineering from the Uni-versity of Toronto, Canada, in 1994.

From 1984 to 1991, he worked in R&D andacademia in Bucharest, where he designed andlectured on microwave semiconductor devices andintegrated circuits. Between 1994 and 2002 he waswith Nortel Networks and Quake Technologiesin Ottawa, Canada, where he was responsible for

projects in high-frequency characterization and statistical scalable compactmodel development for Si, SiGe, and III-V devices. He later conducted researchon wireless and optical fiber building blocks and transceivers in these technolo-gies. In 2002, he joined the University of Toronto, where he is a full Professor.He has authored or coauthored over 100 refereed and invited technical papersspanning the simulation, modeling, design, and fabrication of high frequencysemiconductor devices and circuits. His research and teaching interests focuson nanoscale semiconductor devices and their application in integrated circuitsat frequencies beyond 200 GHz.

Dr. Voinigescu received NORTEL’s President Award for Innovation in 1996and is a member of the TPCs of the IEEE CSICS and BCTM. He is a co-recipientof the Best Paper Award at the 2001 IEEE CICC and at the 2005 IEEE CSICS,and of the Beatrice Winner Award at the 2008 IEEE ISSCC. His students havewon Best Student Paper Awards at the 2004 IEEE VLSI Circuits Symposium,the 2006 SiRF Meeting, 2006 RFIC Symposium, and 2006 BCTM.

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