Fast Extraction of High-Frequency Parallel Admittance of Through-

Silicon-Vias and their Capacitive Coupling-Noise to Active Regions

Chuan Xu1, Roberto Suaya

2, and Kaustav Banerjee

1

1 Dept. of Electrical and Computer Engineering, University of California, Santa Barbara, CA 93106, USA

2

D2S Division, Mentor Graphics Corporation, 38334 St. Ismier, France

Abstract — We introduce an accurate and efficient method to

extract high-frequency parallel admittance (capacitance and

conductance) among multiple Through-Silicon-Vias (TSVs). Our

method utilize the analytical expression of TSV’s MOS

capacitance and the 3D quasi-electrostatic (QES) scalar potential Green’s function in layered media for extracting the inverse of complex capacitance matrix of TSV segments, with consideration

of low conductivity silicon bulk region and high conductivity well regions with VDD/VSS contact rails. The elements of the complex

capacitance matrix of TSV segments can be summed up to the

final results of parallel admittance matrix of TSVs. Our method is

verified against a full-wave Finite-Element-Method (FEM) electromagnetic solver HFSS, and shows more than 103X speed-up

with good accuracy in the frequency range from digital circuit clock frequency to 100 GHz (<7% error for the self-admittance, the dominant quantity, and <13% error for the mutual-admittance, the smaller quantity). The complex capacitance matrix of TSV

segments and the scalar potential Green’s function is also used to

extract the noise coupling coefficient from TSV to active regions, which is also verified by HFSS simulation.

Index Terms — 3-D ICs, extraction, interconnect, parallel admittance, quasi-electrostatic, scalar potential Green’s function, through-silicon-via.

I. INTRODUCTION

High aspect ratio through-silicon-vias (TSVs) constitute a

key component for 3-D ICs [1],[2]. Both fabrication

technologies of TSVs [3]-[6] and electrical/electromagnetic

modeling and simulation [7]-[13] have been investigated. Full-

wave Finite-Element-Method (FEM) simulations [7] are

accurate but are very slow and memory intensive. Curve fitting

based empirical TSV admittance/impedance models [8] are in

closed form, but lack generality when geometrical and/or

material configurations change. The TSV’s MOS capacitance is

derived in [9]-[11], which is shown to be essential to the TSV

admittance. Analytical expressions for self-admittance of a

single TSV and coupling-noise from a single TSV to active

regions are derived in [12]. Numerical method in computational

electromagnetics to analyze multiple TSVs has been discussed

in [13], and the computation time is ~30 sec per data point for

the case of 4 TSVs. A fully analytical model for the high-

frequency series impedance (resistance and inductance) of

TSVs with consideration of substrate eddy current effect and

coupling with horizontal interconnects is discussed in [14]. The

TSV parallel admittance (capacitance and conductance, CG),

which is shown to be more important [10], needs investigation.

In this paper, we develop an accurate and efficient method to

extract the high-frequency (up to 100 GHz) parallel admittance

of multiple TSVs, which is based on analytical expression of

TSV’s MOS capacitance and scalar potential Green’s function

in layered media. Our extraction method is verified against a

full-wave FEM software (HFSS [15]). A method to extract the

coupling-noise from TSV to active regions when multiple TSVs

are present is also discussed.

II. QUASI-ELECTRO-STATIC (QES) SCALAR POTENTIAL

GREEN’S FUNCTION IN 3-D IC CONFIGURATION

Twin-well configuration is the most typical structure in bulk

CMOS and thin-BOX SOI technologies. In this paper, we

mainly discuss face-to-back 3-D IC with twin-well low

conductivity substrate (Fig. 1). Our methodology can be

extended to other type of configurations, once scalar potential

Green’s function in layered media is properly derived.

Quasi-electro-static (QES) assumption is valid since the

electromagnetic quarter wave length in SiO2 (0.37 mm at 100

GHz) is much greater than the TSV dimension. In such

assumption, the scalar potential in layered media at any (x,y,z)

due to a point source charge at (x',y',z'), can be expressed as:

( , , ) ( , , ; ', ', '); ( ', ', ')V x y z G x y z x y z qN x y zΦ= , (1)

where “<;>” is an operator, which captures the space integration

of sources at various (x',y',z'); qN(x',y',z') is the charge density at

Hbulk

(x=x2,y=y2,z=z2)+(x'=x1,y'=y1,z'=z1)bulk Si

Treat high conductive wells as ground plane

upper dielectric

lower dielectric

x

z

2 ( ') ( ') ( ')( , , ; ', ', ')

Si Si

x x y y z zG x y z x y z

j

δ δ δ

ε σ ωΦ − ⋅ − ⋅ −

∇ = −−

2 ( , , ; ', ', ') ( ') ( ') ( ') dielG x y z x y z x x y y z zδ δ δ εΦ∇ = − − ⋅ − ⋅ −

Fig. 2 The high conductivity wells (connected to VDD/VSS interconnects) can be treated as ground plane. The scalar potential Green’s function GΦ(x,y,z;x',y',z') satisfies Poisson’s equation

Hbulk

Si depletion region

Si bulk region

(P-type, 10 Ω-cm)

Si d

eple

tio

n r

egio

n

TS

V m

eta

l

STI STISTI STI STIN-Well, 0.1 Ω-cm

Si d

eple

tio

n r

egio

n

STI STIP-Well, 0.1 Ω-cm P-Well

TSV isolation SiO2

VDDVSS NMOS PMOS NMOSPMOS

Both p-well and n-well

are present in twin-well

configuration. Substrate

conductivity (~10 S/m)

is typically much lower

than the wells in most

advanced (< 32 nm)

CMOS technologies,

due to less concern of

latch-up effect in lower

supply voltage and more

concern of the substrate

eddy current for RF

components.

Fig. 1 Cross sectional view of TSV in twin-well face-to-back 3-D IC configuration with low conductivity substrate

978-1-4673-1088-8/12/$31.00 ©2012 IEEE

(x',y',z'); GΦ

(x,y,z;x',y',z') is the space domain scalar potential

Green’s function in layered media. The high conductivity wells,

which are connected to VDD/VSS interconnects, can be treated as

a ground plane (Fig. 2). GΦ

can be transformed from the

spectral domain vector potential Green’s function (GΦ ):

00

( , , ') (1 2 ) ( , , ') J ( ) dG z z G z zρ π λ λ ρ λ λ∞

Φ Φ∆ = ⋅∆∫ (2)

where 2 2( ' ) ( ' )x x y yρ∆ = − + − ; λ is the horizontal component

of wave vector; J0 is the 0th

order Bessel function of the 1st

type.

For 0<z<Hbulk and 0<z'<Hbulk (Hbulk is the thickness of Si bulk

region in thinned substrate),

( ) | '| ( ')

, 1

( ') ( ') ( ')

2 3 4

( , , ') 1 2 e e

e e e

z z z z

Si eff

z z z z z z

G z z c

c c c

λ λ

λ λ λ

λ λεΦ − − − +

+ − − −

= +

+ + +

(3)

where εSi,eff = εSi − jσSi/ω is the effective complex permittivity in

the Si bulk region; εSi and σSi are the permittivity and

conductivity in Si bulk region, respectively; ω is the radial

frequency; coefficients c1, c2, c3 and c4 are independent of z and

z', and can be extracted from boundary conditions. Eq. (3) can

be approximated from making a Taylor series of 2

e bulkHλ− :

( )

, 2| '| ( ')

, ,

, 2 4( ') ( ') ( ')

,

1( , , ') e 1 e e

2

e e e e (e )

bulk

bulk bulk

Si eff diel Hz z z z

Si eff Si eff diel

Si eff diel H Hz z z z z z

Si eff diel

G z z

O

λλ λ

λ λλ λ λ

ε ελ

λε ε ε

ε ε

ε ε

−Φ − − − +

− −+ − − −

−= − − +

−+ − − +

+

(4)

where εdiel is the permittivity in lower dielectric. From (2)&(4),

2 2 2 2,

, 2 2

, ,

2 2 2 2

2 2

1 1 1( , , ')

4 ( ') ( ')

11 ( ' 2 )

4

1 ( ' 2 ) 1 ( ' 2 )

1 ( ' 2 )

Si eff

Si eff diel

bulk

Si eff Si eff diel

bulk bulk

bulk

G z zz z z z

z z H

z z H z z H

z z H

ρπε ρ ρ

ε ερ

πε ε ε

ρ ρ

ρ

Φ

∆ ≈ − ∆ + − ∆ + +

− + ∆ + + −+

− ∆ + − + − ∆ + − −

+ ∆ + + +

(5)

Eq. (5) can be interpreted as the contribution from the source

charge itself and its 5 image charges from reflections at the

ground plane and/or the interface between Si bulk region and

lower dielectric. GΦ

with z<0 or z>Hbulk or z'<0 or z'>Hbulk can

be obtained using similar way, but is not presented in this paper.

III. TSV PARALLEL ADMITTANCE EXTRACTION AND

CAPACITIVE COUPLING-NOISE FROM TSVS TO ACTIVE REGIONS

TSVs are segmented as shown in Fig. 3. The segmentation

rule: the TSVs are firstly cut at all interfaces (e.g., the interface

between Si bulk region and lower dielectric); for high aspect

ratio parts (e.g., parts within Si bulk region), they are cut into

more than one segment. For the test cases in Section IV, the

TSV parts within Si bulk region are cut into 5 segments, which

make 8 segments per TSV. Fig. 3 also shows the correlation

among scalar potential Green’s function, P and C matrices of

TSV segments, Y matrix of TSVs and charge on each TSV

segment Qi'. Note that the correlated equation from Green’s

function to Pi,i' is for the case that segments i and i' are within

the two boundaries of Si bulk region, but similar expression can

be found for either segments i or i' outside the two boundaries.

The noise coupling coefficient from a TSV to the active

regions when multiple TSVs are present can be obtained from

current density injected into the well (J(x,y)) and the well

resistance network. The general idea has been presented in [12],

where only one TSV is present. In this paper, J(x,y) is obtained

in a more accurate way, which is proportional to the gradient of

scalar potential at the boundary of Si bulk region and p-well:

( )' ' ' ' 0'

( , ) ( ) ( , , ; , , )Si Si i i i i z

i

J x y j Q G x y z x y z zσ ωε= +

= + ∂ ∂∑ (6)

J(x,y) can then be used to estimate the coupling-noise voltage in

the active regions, as is done in [12].

IV. VERIFICATION AGAINST FULL-WAVE FEM SIMULATIONS

Our extraction method (coded in Maple [16], a symbolic

computation and mathematical programming tool) is verified

against full-wave FEM simulations (HFSS [15]) for two cases.

A. Test Case with 2 TSVs

The calculation results of the self- and mutual-admittance of

the two TSVs (Y11 and Y12) in the test case (top view shown in

Fig. 4) are compared with HFSS simulation in Fig. 5. The

TSV segmentationTSV segmentation

C=P-1

segment segmentTSV ' TSV

, , '

'

TSV TSV

TSV TSV

i i i i

i i i i

i i

Y j Cω′∈ ∈

′ = ∑ ∑

segment TSV

' ',

TSV

TSV

TSV

i i

i i i i

i i

Q V C∈

= ⋅

∑ ∑

When 0<zi<Hbulk and 0<zi' <Hbulk

, '

'

1 1ln

2

1ln

2

( , , )

( ', same TSV and same segment)

( , , )

( ', same TSV but different segm

via ox dep

via ox dep

i i

via ox

i ox via

via ox dep

Si via ox

i i r t w

i i r t w

P

r t

h r

r t w

r t

G z z

i i

G z z

i i

ρ

ρ

πε

πε

ρ

ρ

∆ = + +

∆ = + +

=

+

+ + +

+

+ ∆

=

∆

≠

' ' '

ents)

( , , ; , , )

( ', different TSVs)

i i i i i iG x y z x y z

i i

≠

Fig. 3 Schematic view of TSV segmentation (the TSVs are cut by the dashed

lines) and correlation among scalar potential Green’s function, P and C

matrices of TSV segments, Y matrix of TSVs, and charge on each TSV

segment Qi'. C is the complex capacitance matrix of TSV segments (due to the

conductive silicon substrate, εSi,eff is complex); P=C-1; Y is the parallel admittance matrix of TSVs; ViTSV is the voltage on TSV iTSV. tox and εox are the

thickness and permittivity of TSV oxide, respectively; rvia is the radius of TSV

metal; wdep is the depletion width surrounding the TSV oxide.

VDD

Pla

cin

g

NM

OS

Pla

cin

g

PM

OS

Pla

cin

g P

MO

STSV

Pla

cin

g N

MO

S

VSS

Pla

cin

g

NM

OS

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5

VSS

VSS

1.5 µm 1.5 µm 1.5 µm

TSV

y

xd1 d2

OP1

d1 d2

OP2y1

y1

VDD

Pla

cin

g

NM

OS

Pla

cin

g

PM

OS

Pla

cin

g P

MO

STSV

Pla

cin

g N

MO

S

VSS

Pla

cin

g

NM

OS

Zone 1 Zone 2 Zone 3 Zone 4 Zone 5

VSS

VSS

1.5 µm 1.5 µm 1.5 µm

TSV

y

xd1 d2

OP1

d1 d2

OP2y1

y1

Fig. 4 Schematic top view of 2 TSVs in bulk CMOS technology. The 2 TSVs have center-to-center (c2c) distance of 2y1; observation points OP1 & OP2 and geometrical parameters d1 (=1.0µm) & d2 (=0.5µm) are defined in the plot.

978-1-4673-1088-8/12/$31.00 ©2012 IEEE

greater error of both Y11 and Y12 at higher frequencies is due to

the fact that the ground plane treatment of wells is more valid at

lower frequencies for the condition |σwell/(σSi+jωεSi)|>>1. Our

method gives <7% error for Y11, the dominant quantity, and

<9% error from 4 GHz (typical digital circuit clock frequency)

to 100 GHz for Y12, the smaller quantity. We compare the

results of noise coupling coefficient g31 (ratio of voltage

variation at observation point to that at one of the 2 TSVs) with

HFSS in Fig. 6. The total computation time per data point using

our method is 0.10 sec as compared to 130 sec using HFSS.

B. Test Case with 4 TSVs

The top view of the test case and the results are shown in Fig.

7. Due to the symmetry of the structure, our extraction method

gives Y11=Y22=Y33=Y44, Y12=Y23=Y34=Y14 and Y13=Y24. In HFSS

simulation, there is slight and negligible difference within the

three categories (Y11, Y12 and Y13), due to the slight asymmetry

from the VSS lines. Nevertheless, it is sufficient to just compare

the results of Y11, Y12 and Y13. Similar to the case of 2 TSVs, in

the case of 4 TSVs, our method is generally more accurate

(<6% error) for Y11, the dominant quantity, and less accurate

(<13% error from 4 GHz to 100 GHz) for Y12 and Y13, the

smaller quantities. The computation time per data point using

our method is 0.31 sec as compared to 680 sec using HFSS.

V. SUMMARY

An accurate and efficient method to extract the high-

frequency parallel admittance of multiple TSVs is developed

through utilizing the analytical expression of TSV’s MOS

capacitance and 3D QES scalar potential Green’s functions in

layered media, and is extended to the estimation of electrical

coupling-noise voltage from TSV to active regions. Our method

is verified against full-wave FEM electromagnetic simulations,

which shows good accuracy and 103X speed-up. Our method

gives <7% error for the TSV self-admittance, the dominant

quantity, and <13% error from digital circuit clock frequency to

100 GHz for the TSV mutual-admittance, the smaller quantity.

REFERENCES

[1] K. Banerjee et al, “3-D ICs: A novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration,”

Proceedings of the IEEE, vol. 89, pp. 602-633, 2001. [2] G. L. Loi et al, “A thermally-aware performance analysis of vertically

integrated (3-D) processor-memory hierarchy,” 43th ACM/IEEE DAC, 2006,

pp. 991-996. [3] N. Sillon et al, “Enabling technologies for 3D integration: From packaging

miniaturization to advanced stacked ICs,” Tech. Dig. IEDM 2008, pp. 595-598. [4] F. Liu et al, “A 300-mm Wafer-level three-dimensional Integration Scheme

Using Tungsten Through-Silicon Via and Hybrid Cu-Adhesive Bonding,”

Tech. Dig. IEDM 2008, pp. 599-602. [5] G. Katti et al, “3D stacked ICs using Cu TSVs and die to wafer hybrid

collective bonding,” Tech. Dig. IEDM 2009, pp. 357-360. [6] L. Cadix et al, “Integration and frequency dependent electrical modeling of

Through Silicon Vias (TSV) for high density 3DICs,” 2010 IITC, pp. 1-3. [7] J. S. Pak et al, “Electrical characterization of through silicon via (TSV)

depending on structural and material parameters based on 3D full wave

simulation,” Int. Conf. Electronic Materials and Packaging, 2007, pp. 1-6. [8] I. Savidis et al, “Closed-form expressions of 3-D via resistance, inductance, and capacitance,” IEEE TED, 56(9), pp. 1873-1881, 2009. [9] G. Katti et al, “Electrical modeling and characterization of through silicon

via for three-dimensional ICs,” IEEE TED, 57(1), pp. 256-262, 2010. [10] C. Xu et al, “Compact AC Modeling and Performance Analysis of

Through-Silicon Vias in 3-D ICs,” IEEE TED, 57(12), pp. 3405-3417, 2010. [11] T. Bandyopadhyay et al, “Rigorous Electrical Modeling of Through

Silicon Vias (TSVs) With MOS Capacitance Effects,” IEEE Trans. CPMT, 1(6), pp. 893-903, 2011. [12] C. Xu et al, “Compact Modeling and Analysis of Through-Si-Via-Induced

Electrical Noise Coupling in Three-Dimensional ICs,” IEEE TED, 58(11), pp. 4024-4034, 2011. [13] K. J. Han et al, “Electromagnetic Modeling of Through-Silicon Via (TSV)

Interconnections Using Cylindrical Modal Basis Functions,” IEEE Trans. Advanced Packaging, 33(4), pp. 804-817, 2010. [14] C. Xu et al, “A Fully Analytical Model for the Series Impedance of

Through-Silicon Vias With Consideration of Substrate Effects and Coupling

With Horizontal Interconnects,” IEEE TED, 58(10), pp. 3529-3540, 2011. [15] User’s Guide: High Frequency Structure Simulator (HFSS v10.0), Ansoft Corporation, Pittsburgh, PA, 2005. [16] Maple 14 Student Edition. [Online]. Available: http://www.maplesoft.com

109

1010

1011

-0.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

VSS

TSV1

VSSVSSVSS

6 µm

TSV3

TSV2 TSV4

6 µm VSS

TSV1

VSSVSSVSS

6 µm

TSV3

TSV2 TSV4

6 µm

Lines: This workSymbols: HFSS simulation

Im(Y11

)

Re(Y11

)

Im(Y12

)

Re(Y12

)

Im(Y13

)

Re(Y13

)Ad

mitta

nce (

10

-3 S

)

Im(Y11

)

Re(Y11

)

Im(Y12

)

Re(Y12

)

Im(Y13

)

Re(Y13

)

Frequency (Hz) Fig. 7 The self and mutual admittance of 4 TSVs (Y11, Y12 and Y13) as a function of frequency from our methodology in this work and from HFSS simulation. The schematic top view is shown in the inset. The TSVs are located in between VSS lines and form a square shape with diagonal distance of 6 µm. All other parameters are the same as those in the test case of 2 TSVs.

Symbols: HFSS simulation Lines: our method

109

1010

1011

-0.50.00.51.01.52.02.5 2y

1 = 4

µm

Im(Y11

)

Re(Y11

)

Im(Y12

)

Re(Y12

)

Ad

mitta

nce (

10

-3 S

)

Im(Y11

)

Re(Y11

)

Im(Y12

)

Re(Y12

)

Frequency (Hz)

4 6 8 10 12-0.5

0.0

0.5

1.0

1.5

f = 50 GHzA

dm

itta

nce

(10

-3 S

)

2y1 (µm)

(a) (b)

Fig. 5 The self and mutual admittance of two TSVs (Y11 and Y12) as a function of frequency and c2c distance (2y1) from our methodology in this work and from HFSS simulation. The cross section view and top view of the configuration are shown in Fig. 1 and Fig. 4, respectively. The technology configuration, default material and geometrical parameters are the same as those in Section III.A of [12]. (a) Y11 and Y12 as a function of frequency (f) with 2y1 = 4 µm; (b) Y11 and Y12 as a function of 2y1 with f = 50 GHz.

Symbols: HFSS simulation Lines: our method

109

1010

1011-80

-70

-60

-50

-40

-30

-20

OP2

OP1

dB

(|g

31|)

Frequency (Hz)

2y1 = 4

µm

4 6 8 10 12

-50

-40

-30 OP1

50 GHz

10 GHz

dB

(|g

31|)

2y1 (µm)

(a) (b)

Fig. 6 The noise coupling coefficient g31 from one of the 2 TSVs to the OPs, with the other TSV keeping a constant voltage. (a) dB(|g31|) as a function of frequency (f) with 2y1 = 4 µm for both OP1 and OP2; (b) dB(|g31|) as a function of 2y1 for OP1 with f = 10 GHz and f = 50 GHz.

978-1-4673-1088-8/12/$31.00 ©2012 IEEE