A bridgeless Cuk PFC converter

M. R. Sahid; A. H. M. Yatim: N. D. Muhammad Faculty of Electrical Engineering, Universiti Teknologi Malaysia,

81310 UTM Skudai, Johor, Malaysia Email: rodhi@fke.utm.my

Abstract- A bridgeless Power Factor Correction (PFC) circuit based on Cuk converter is proposed in this paper. The operation during each sub-interval modes of the converter operated in Discontinuous Conduction Mode (DCM) is discussed. The small-signal and large signal models are presented using Current Injected Equivalent Circuit Approach (CIECA). PLECS/Simulink is used to verify the capability of the proposed converter to regulate the output voltage while the input current regulation is inherent. This converter is capable to operate in universal input voltage condition.

I. INTRODUCTION

Since the past several decades, the power factor correction

(PFC) circuit is no more a strange issue among switch-mode power supply (SMPS) designer due to its capability to draw energy effectively from the mains. Besides improving the power factor, PFC circuits are also designed to give the highest efficiency by reducing the number of components conducted during its operation.

Recently, the bridgeless PFC circuit has gained its interest and popularity as part of the topology used in designing SMPS [1]. The first bridgeless PFC circuit proposed in 1983 [2] by D.M. Mitchell based on Boost converter, has paved the way for higher efficiency PFC converter. This can be achieved by reducing the number of components conducted, i.e. diode rectifier. As depicted in Fig. 1, while the conventional PFC converter would have at least two diode rectifiers conducted all the time, the bridgeless PFC only require one diode rectifier conducted, especially during turn ON condition.

A substantial work on bridgeless Boost PFC has been carried out since the last few years. Most of the works are focused on improving the efficiency of the converter by either reducing the energy loss within each component or by introducing the soft-switching techniques [3]. However, one of the drawbacks in Boost converter is the DC output voltage level, which is always higher than the input voltage. For a universal input voltage PFC converter, the output voltage is around 380V DC or more, while most electronic applications always operate at lower value namely 5V to 50V DC. Introducing another DC-DC converter that step down the 380V DC to 5V DC would sacrifice much of the converter efficiency. Thus, considering a PFC converter that capable to give lower voltage at the output would be a great alternative. Besides Boost, several bridgeless PFC topologies such as Buck [4], Buck-Boost [5], SEPIC [6] and Cuk [7] have been proposed.

In this paper, a new bridgeless PFC circuit based on Cuk converter is proposed. One of the advantages inherent in each

Cuk converter is its high quality input and output current. The location of the inductors at the input and output port of the Cuk converter is the main reason to justify that these two currents would never be turned OFF abruptly.

II. OPERATIONS AND ANALYSIS OF THE PROPOSED CONVERTER

The proposed bridgeless Cuk PFC converter schematic with

operation during positive and negative half-line period is shown in Fig. 2(a), 2(b) and 2(c) respectively. The number of components conducted, i.e. input diode, during each half-line period is less compared to the conventional Cuk PFC converter [7] and even less than the normal bridgeless Cuk PFC [8]. For instance, the normal bridgeless and conventional Cuk should have at least two input diode conducted either during MOSFET turned OFF period for normal bridgeless or conducted all the time for conventional PFC. On the other hand, as shown in Fig. 2(b) and (c), the fully-bridgeless Cuk converter only has one input diode conducted all the time which is either Ds2 or Ds1. However, the drawback is the overall number of components used to develop this converter is more compared to the other two Cuk PFC topologies mentioned earlier. It is due to two set of Cuk converters exist during each half-line period.

Co

L

D1

RloadV1

D2

M1

D4D3

Do

(a)

Dm2

C

L

M2

D1

Rload

M1

D2

Dm1

V1

(b)

Fig. 1. Schematic of (a) the conventional Boost PFC and, (b) bridgeless Boost PFC converter.

2011 IEEE Applied Power Electronics Colloquium (IAPEC)

978-1-4577-0008-8/11/$26.00 ©2011 IEEE 81

In this paper, the analysis during positive half line period is discussed while the same model can be used for negative half line period. Since the discontinuous conduction mode (DCM) operation is our concern, three subinterval modes exist within each switching period namely, d1TS, d2TS and d3TS. The equivalent circuit for these three modes is depicted in Fig 3(a), (b) and (c) while the key waveforms are shown in Fig. 4. Throughout the analysis to obtain the high frequency model, the input voltage, vg(t) is assumed to be constant within each switching period. Then, for the low frequency model, this assumption is no longer valid and the sinusoidal waveform will replace the value of vg(t) to get more accurate model for the purpose of PFC model [9].

To further ease the analysis, the Current Injected Equivalent Circuit Approach (CIECA) [10,11] is used to obtain the small-signal model of the proposed converter. In CIECA, the average input and output current injected to/from the circuit within each switching period, TS, is analyzed. In this converter, the input current is iL1 and the output current is iL2 with the average value are represented as

O

OggSTsAVGL vL

vvvTdi

1

21

1 2)( +

=−−

(1) and

02

21

2 2)(

vLvvvTd

i OggSTsAVGL

+=−− (2)

From these two high frequency models, by defining the input voltage as )sin( tvv mg ω= , the low frequency models are

obtained by integrating the high frequency model up to half line period, TL = π rad, such that,

tdvL

vvvTdi

O

OggSTLAVGL ω

ππ

∫+

=−− 01

21

1 2)(1

⎟⎠⎞

⎜⎝⎛ +=

πOm

O

Sm vvLvTdv

41

21 (3)

and

∫+

=−−

πω

π 002

21

2 2)(1 td

vLvvvTd

i OggSTLAVGL

⎟⎠⎞

⎜⎝⎛ +=

πOm

O

Sm vvLvTdv

42

21 (4)

With small perturbation introduce to iL1, iL2, d1, vm and vO, the small signal models are,

OmL vgdjvr

i ˆˆˆ1ˆ111

11 −+= (5)

and

OmL vr

djvgi ˆ1ˆˆˆ2

1222 −+= (6)

where

L3

Co

L1

RD1

Cb2

Ds2

L2

Ds1Vg

D2

Cb1

S1

S2

(a)

S1

L1

Ds2

D1

L2

Vg

Cb1

RCo

(b)

Ds1

L3

L1

Co R

S2Cb2

Vg

D2

(c)

Fig. 2. Schematic of (a) the proposed bridgeless Cuk PFC with operation during, (b) positive and, (c) negative half-line period.

iL1 iCb1 iL2

iCO iO

Cb1

Ds2

Co

L1 L2

S1Vg

R

(a)

iL1 iCb1 iL2

iCO iO

Ds2

Co

L2

RD1

L1

Vg

Cb1

(b)

iL1 iCb1 iL2

iCO iO Vg

Cb1

Co

L1

R

Ds2

L2

(c)

Fig. 3. Equivalent circuit during (a) d1TS, (b) d2TS, and (c) d3TS.

82

( )OmO

S VVVLTD

r2

21

1

21

1

+= ππ

,

( )OmO

mS VVVLVTD

j 42 1

11 += π

π,

21

221

1 4 O

mS

VLVDTg = ,

( )OmO

S VVVLTD

g 22 2

21

2 += ππ

,

( )OmO

mS VVVLVTD

j 42 2

12 += π

π,

22

221

2 41

O

mS

VLVTD

r= .

The small signal equivalent circuit is shown in Fig 5. The input-to-output and control-to-output transfer functions are

⎟⎟⎠

⎞⎜⎜⎝

⎛++

==

2

2

0ˆ 11ˆˆ

1

rRsC

gvv

Odm

O (7)

and

⎟⎟⎠

⎞⎜⎜⎝

⎛++

==

2

2

0ˆ1 11ˆˆ

rRsC

jdv

Ov

O

m

(8)

III. DESIGN AND SIMULATION RESULTS

The small-signal and large-signal model for proposed fully-bridgeless Cuk converter is designed based on the parameters shown in TABLE I. It can be seen that the proposed converter will accept universal input voltage values which ranging from 115Vrms to 240Vrms. As shown in Fig. 6, the converter control-to-output transfer function as presented in Equation (8) is plotted using MATLAB to see the variation of the bode-plot gain and phase with universal input voltage values. It seems that by increasing the input voltage, the gain of the control-to-output bode-plot will increase as well. However, the phase-plot is very much similar when the input voltage is increased.

TABLE I Circuit parameters

Parameters Values Input voltage, Vg 115 – 240Vrms Line frequency, fL 50Hz

Switching frequency, fS 50kHz Input inductor, L1 150uH

Intermediate inductors, L2 & L3 75uH Bulk capacitors, C1 & C2 1uF

Output capacitor, Co 1.41mF Output voltage, Vo 50V DC Output power, Po 100W

Then, the PLECS/Simulink is used to verify the small-

signal model derived earlier. Using the PLECS AC Model, the bode-plot of the converter is plotted using the real switch

2

1

Lvv CbO −

iCb1(t)

iL2(t)

iL1(t)

iDo1(t)

1Lvg

d1TS

S1,S2(t)

d2TS d3TS

1

1

Lvv gCb −

−

1

1

Lvv gCb −

−

2LvO−

2

1

Lvv OCb −

⎟⎟⎠

⎞⎜⎜⎝

⎛+

−−

21

1

Lv

Lvv OgCb

Fig. 4. Key waveforms for the proposed converter in DCM.

mv̂ 1r 11d̂j Ovg ˆ1 12d̂j mvg ˆ2 2r ROC Ov̂

2L̂i1L̂i

Fig. 5. Small-signal equivalent circuit.

-10

0

10

20

30

40

50

Mag

nitu

de (

dB)

10-1

100

101

102

-90

-45

0

Pha

se (

deg)

Bode Diagram

Frequency (Hz) Fig. 6. Gain and phase plot variation with input voltage at 100V, 140V,

240V and 340V rms.

Vg = 70V

Vg = 100V

Vg = 170V

Vg = 240V

83

circuit. As depicted in Fig. 7, the bode-plot is compared with the derived transfer function obtained from CIECA as presented in Equation (8). For Vg = 240V rms, the phase-plot between these two methods are similar while for the gain-plot, a gain gap as small as 2 dB is noticed.

Fig. 8. Large-signal model of the proposed fully-bridgeless Cuk PFC

converter. Using simple PI controller, the converter closed-loop

system is designed and simulated by utilizing the voltage follower method. The voltage loop bandwidth is designed at 20 Hz with 82o phase margin. The PLECS/Simulink is again used to develop the large signal model as shown in Fig. 8.

The inductor current, output (load) voltage and input voltage waveforms for Vg = 115 Vrms and Vg = 240 Vrms are shown in Fig. 9 and Fig. 10 respectively. Suppose the output voltage of a Cuk converter is negative, but the waveform oppositely shows a positive output voltage at 50 VDC. As can be seen from Fig. 8, this is due to the connection of the output voltage measurement which is in the reverse polarity.

From Fig. 9 and Fig. 10, the PI controller is able to regulate the output voltage to 50 VDC when the load change from 100 W to 50 W at t = 0.2 s. At t = 0.4 s, the load is change back to 100 W and the output voltage is successfully regulated to 50

VDC. Similar response can be observed when the input voltage is set at 240 Vrms.

Fig. 11 shows the filtered input current when LC input filter is connected with L and C is designed at 150 uH and 1 uF. With the input filter the current total harmonic distortions (THDi) is measured at 7 % and 14 % for 115 Vrms and 240 Vrms input voltage respectively. At full load, the power factor for 115 Vrms is 0.988 and for 240 Vrms is 0.904.

Inductor current

Load voltage

Input voltage

-2

0

2

40

50

60

0.1 0.2 0.3 0.4 0.5 0.6-200

0

200

Fig. 9. Inductor current and output voltage waveforms with load disturbance of 100W-50W-100W at 0.2s and 0.4s for 115Vrms input voltage.

Inductor current

Load voltage

Input voltage

-2

0

2

40

50

60

0.1 0.2 0.3 0.4 0.5 0.6-400

-200

0

200

400

Fig. 10. Inductor current and output voltage waveforms with load disturbance of 100W-50W-100W at 0.2s and 0.4s for 240Vrms input voltage.

0

10

20

30

40

50

60

Mag

nitu

de (

dB)

101

102

103

-90

-45

0

Pha

se (

deg)

Bode Diagram

Frequency (Hz) Fig. 7. Control-to-output bode-plot obtained from PLECS/Simulink(∅)

(G1&P1) and from CIECA model (*) (G2&P2).

G2

G1

P2 P1

84

Input voltage

Input current-200

-100

0

100

200

0.36 0.37 0.38 0.39 0.4-1.5

-1

-0.5

0

0.5

1

1.5

Fig. 11. Input current for 115Vrms input voltage.

IV. CONCLUSIONS

The small-signal and large-signal model for the proposed bridgeless Cuk PFC converter has been designed and simulated using Matlab/Simulink/PLECS simulator. The small-signal model has been derived using CIECA method and verified using PLECS AC model. Both models show reasonable similarity for wide range of operating frequency. The closed-loop PI controller successfully regulates the output voltage with step-load change up to half the nominal load value.

ACKNOWLEDGMENT

The authors would like to thank to MOHE (Ministry of Higher Education), Malaysia for the financial support.

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Electronics Technology magazine, February 2008. [2] D.M. Mitchell, "AC-DC Converter having an improved power

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[5] Wang Wei; Liu Hongpeng; Jiang Shigong; Xu Dianguo; , "A novel bridgeless buck-boost PFC converter," Power Electronics Specialists Conference, 2008. PESC 2008. IEEE , vol., no., pp.1304-1308, 15-19 June 2008.

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[7] Brkovic, M.; Cuk, S.; , "Input current shaper using Cuk converter," Telecommunications Energy Conference, 1992. INTELEC '92., 14th International , vol., no., pp.532-539, 4-8 Oct 1992

[8] Sabzali, A.J.; Ismail, E.H.; Al-Saffar, M.A.; Fardoun, A.A.; , "A new bridgeless PFC Sepic and Cuk rectifiers with low conduction and switching losses," Power Electronics and Drive Systems, 2009. PEDS 2009. International Conference on , vol., no., pp.550-556, 2-5 Nov. 2009.

[9] Lin, J.-L., Yang, S.-P. and Lin, P.-W., Small-signal analysis and controller design for an isolated zeta converter with high power factor correction. Electric Power Systems Research, Sept. 2005. 76(1-3): p. 67-76.

[10] Chetty, P.R.K.; "Current Injected Equivalent Circuit Approach to Modeling Switching DC-DC Converters", IEEE Transactions on Aerospace and Electronic Systems, vol. AES-17, no. 6, pp.802 – 808, Nov. 1981

[11] Chetty, P. R. K.; "Current Injected Equivalent Circuit Approach to Modeling of Switching DC-DC Converters in Discontinuous Inductor Conduction Mode", IEEE Transactions on Industrial Electronics, vol. IE-29, np. 3, pp. 230 – 234, Aug. 1982

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