IC Layout Generation and Compaction Module by Watanabe

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I Layout Generation and CompactionUsing Mathematical Optimization

by

Hiroyuki WatanabeT 28

Submitted in Partial Fulfillmentof the

Requirements for the DegreeDoctor of Philosophy

Supervised by Gershon Kedem

Department of Computer ScienceThe University of RochesterRochester, N Y 14627

1984


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cknowledgements

Firs t and foremost I would like to thank my advisor Professor Gershon Kedem. Thetechnical guidance received and the long discussions we had in the course of the developmentof the idea in this thesis were truly valuable.

would like to express my appreciation to Professor Christopher Brown for reading mydraft in detail and giving me helpful advice and to Professor Greg Dobson for giving me anadvice concerning mathemat ical optimization techniques.

My thanks are also for Marciej Ciesielski and Yoshio Hayashi for useful and excitingdiscussions we had in the area of design automation and mathematical optimization.

would also thank Emil Rainero for his comments on recent draft s of this thesis and RosePeet for correcting my English.

would like to express special thanks to rank and Barbera Tiesma for providing me anAmerican home since star ted to study in the United States a long time ago.

Finally am truly thankful to my parents Hiroyasu and Hisako Watanabe for supportingme in many ways for eleven years of academic life.

This work was supported in part by the Defense Advanced Research Projects Agencyunder grand number NOOOI4-78-C-0614 and in part by the Semiconductor ResearchCorporation under grant number 83-01-028.

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Table of Content

Chapter 1 Introduction 11.1. Introduction 11.2. Symbolic Layout 11.2.1. Fixed Grid Method 11.2.2. Relative Grid Method 21.3. Stick Compilers 31.3.1. Existing Systems 31.3.1.1. STICKS Compiler 31.3.1.2. SLIP and SLIM 31.3.1.3. C BB GE 41.3.1.4. REST 41.3.1.5. MULG 51.3.2. Problems with the Existing Systems 51.4. Research Objectives 6Chapter 2 Mixed Integer Linear Programming 72.1. Mathematical Optimization for Layout Generation 72.2. Linear Programming 72.3. Mixed Integer Programming 122.4. Further Generality of Mixed Integer Programming 132.5. Difficulty with Mixed Integer Linear Programming 14Chapter 3 Graph Optimization 173.1. Introduction 173.2. Input Convention 173.3. Graph Nodes 173.4. rcs in the Graph 193.4.1. Vertical and Horizontal Groups 193.4.2. Distance Requ irements Imposed by Design Rules 203.4.3. Connection Constraints between Symbols and Wires 243.4.4. Arcs and Groups 273.5. Formalization as a Graph Optimization Problem 273.5.1. Notation for Representation of Graphs 273.5.2. Decision Variables 293.5.3. The Optimization Problem 293.6. Restriction of The Formulation 29

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Chapter Graph Generation 334.1. Introduction 334.2. Electrical Node Extraction 334.3. Groups and Their Ordering 354.4. Constraints from Design Rules 354.4.1. Calculation of Minimum Distance Requirements 354.4.2. Connected Elements without Freedom of Movement 364.4.3. Choosing Between a Simple Arc and Dual Arcs 384.4.3.1. Symbol-Symbol 394.4.3.2. Symbol-Line 404.4.3.3. Line-Line 424.5. Arcs for Connection Requirement 434.6. Elimination of Arcs 434.6.1. Use of Compartments 434.6.2. Reduction by Transitive Closure 45Chapter S Compaction Algorithm 475.1. Introduction 475.2. Upper and Lower Subgraphs 475.3. Mechanism of the Branch and Bound Method 485.4. Pruning Conditions 505.5. Construction of Longest Path Spanning Tree 515.6. Heuristic Method for the Initial Estimate 525.7. Choice of Branching Arcs 535.7.1. Estimating the Change in the Layout Area 535.7.2. Maximum Non-increasing Coordinate 555.7.3. Merit of the Algorithm 56Chapter 6 Application and Extension o the Method 576.1. Introduction 576.2. User Supplied Goals 576.2.1. Connection Points 576.2.2. Minimum Objective Dimension 606.2.3. Preferred Direction of Compaction 626.3. Graph Modification for Recompaction 636.3.1. Jog Point Insertion 636.3.2. Three Way Choices 676.4. Block Level Placement 686.5. Minimization of Wire Length 686.6. Soft Cells 716.6.1. Automatic Rescaling of Ratio and Driving Power 726.6.2. Robustness against Technological Change 73


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Chapter 7 Experimental Implementation and Results 797.1. Experimental Implementation 797.2. Results 797.3. Discussion 82Chapter 8 Conclusion and Future Research 858,I. Conclusion 858,2. uture Research 86References 88Appendix A Documentat ion for Squash User 92

Appendix B Compaction Examples 95


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List o igures

1.1. Compression Ridge and Shear Line 42.1. Constraints between Symbols 82.2. Non-Lineari ty of Compaction Operation 92.3. Linearized but Over Constrained 92.4. Only Horizontal Direction Is Chosen 102.5. Conditional Constraints I I2.6. Linearized Conditional Constraints I I2.7. Varying Horizontal Space Requirement 123.1. Coordinate Variables 183.2. Single Vertical Group 183.3. Two Vertical Group 183.4. Vertical and Horizontal Groups for Shift Cell 203.5. Simple Arcs 203.6a. Dual Arcs: Symbol-Symbol 213.6b. Dual Arcs: Symbol-Wire 223.6c. Dual Arcs: Wire-Wire 233.7. Connection Constraints 243.8. Simple Connection Constraints 253.9. Connection Arcs in Horizontal Graph 263.10. Connection between Wires 263.11. Single Vertical Group 283.12. Vertical Group in Horizontal Graph 283.13. Two Symbols A and B 303.14. Impossible Position for Symbols A and B 303.15. Two Symbols and Their Connected Wires 314.1. Stipple Pattern for N OS Layers 334.2. Enhancement Mode Transistor 344.3. Representation of the Transis tor 344.4. Representation of Electrical Nodes 344.5. Two Non-connecting Symbols 354.6. Two Polysilicon Rectangles 364.7. Two Connected Symbols 374.8. Legal Layout 384.9. Fixed Vertical Clearance 384.10. Connection between Butting Contact and Poly Wire 394.11. Legal Connections 39

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ist of Tables

6.1. Dimensions of Super buffers 616.2. Dimensions of ALU s 747.1. Input Examples 817.2. Resul t of the Compaction 817.3. Computing Time in Seconds 827.4. Goal directed Compaction 847.5. Computing Time in Seconds for Goal directed Compaction 847.6. Dimensions of ALU s 84

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CHAPTER 1

Introduction

1.1. IntroductionLaying out artworkfor the layout design ofan integrated circuit isavery tedious task ofhigh economicimportance. Consequently, there has been active research indesign toolsand in

design automationof integratedcircuits. The research in these areas is being pursued to copewith the complexity ofVLSI permitted bynew fabrication technologies. The research reportedhere isan attempt to increase the generality, capabilityand flexibility of the mask generationprocess. This researchisaimedat the finalendof a spectrumofresearch for asiliconcompiler.The method developed is suitable to be used in the final stage (mask generation stage) of asilicon compiler. t can incorporate goals given by a higher levelautomatic planning process[He179,Sz0801. he compaction method can be used directly by humans at an engineeringwork station. This research introduces a new paradigm in symbolic layout generationalgorithms. Given a dimensionless symbolic layout, a mathematical optimization problem isformulated. A compacted and design rule violation free geometriclayout isobtained bysolvingthis optimization problem. The mathematical optimization formulation used is mixed integerprogramming. The formulation is very powerful in the sense that it can incorporate thefollowing:(}) Simultaneousconsiderationoftwodirections ofcompaction(2) Goaldirectedcompactionand generationofthe layout(3) Automatic generationofjogpointsThe first two features are treated uniformly and are considered simultaneously. The bestcombinationof decisions fora givengoal ismade automaticallyasa result ofthemathematicaloptimization.

1.2. SymbolicLayoutSymbolic layout is one of the approaches taken for computer aided design. In this

approach, the designerisallowed toenter a topologicalspecification ofthe integratedcircuit ina symbolic form. The actual geometric layout isgeneratedautomatically.Thus, the designer isrelieved from themost tediousand error-proneprocessofmask levelspecification.Thereare twotypesof symbolic layout methods. Theywere termed thefixed grid method and the rel tive gridmethod by Min-Yu Hsueh [HsP79,Hsu79]. The former isalsocalled as a co rse grid method[GiN76,GiN77].

1.2.1. FixedGridMethodIn the fixedgrid method, the largest ofminimumwire width and separation requirementofall layers istreatedasa unit length. The layout planeisslicedintounit squares.The designerdefines a layer configuration in terms of unit squares (coarse grids). He maps it into apredefined set ofcharacters and entersit into the system. The system automatically transforms


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1.3. Stick CompilersAlthough stick diagrams themselves have been very successful in assistmg human

designers in producing layouts, an automatic conversion of the stick diagrams to the geometriclayouts is very attractive and useful. Automatic mask generation can guarantee a layout freefrom design rule violations and relieve the human designer from the most tedious aspect ofintegrated circuit design. In order to exploit the concept of deformable cells in the context of thehierarchical design system, an efficient algorithm for generating layouts from stick diagrams isnecessary. In addition the algorithm must e able to incorporate goals or recommendations itreceives from a higher level composition or a planning process. Useful forms of therecommendation are the aspect ratio for cells and position for connection points.

1.3.1. Existing SystemsAfter stick diagrams were introduced by Williams [Wil77l, several research efforts for an

automatic transformation of a stick diagram to a geometrical layout were carried out. Theexisting systems are: STICKS compiler by Williams [Wil77, Wil78l, SLIP and SLIM byDunlop [Dun78,Dun79,Dun80l, CABBAGE by Hsueh [HsP79,Hsu79l and REST by Mosteller[Mos80. Mos8 l l. All of them perform layout compaction. These systems and their algorithm oflayout generation and compaction are described briefly.1.3.1.1. STICKS Compiler

The STICKS compiler is historically the first of these systems. t performs compaction bydividing a two-dimensional problem to two one-dimensional problems. The algorithm considersonly the horizontal or the vertical direction at anyone time. The compaction is accomplished byplacing the bottom most or left most elements on the base line origin). Then elements on asecond horizontal or vertical) coordinates are placed as close as possible to the elementsalready placed without violation of design rules. Therefore, the compaction is accomplished byplacing elements tightly. The direction of compaction alternates. The spacing and placingalgorithm does not look at the global picture. Therefore, the compression in the horizontaldirection may block subsequent compression in the vertical direction and vice versa. The systemdoes not create jog points automatically. The designer is required to specify fracture points apossible place for a jog) in order to insert the jog in the interconnections. The system is heavilydependent on user interaction to accomplish global compaction of the layout. The algorithmitself does not have any provision to incorporate the global goal.

1.3.1.2. SLIP nd SLIMSLIP and SLIM, developed by Dunlop, use compression ridges. Compression ridges are

excess area that can e taken out across a chip layout Figure 1.I . This technique is originallydescribed by Akers [AGR70l for a coarse grid layout. The algorithm considers one direction ata time and the direction of compaction alternates. The symbolic description of layout consists ofnodes and lines. The nodes represent circuit elements and the lines represent interconnections.The symbolic layout is transformed to the geometric layout without violating any masktolerance rules. The transformation is done without any attempt at the compaction. The rowsand columns of the symbolic layout remain as rows and columns in the generated geometriclayout. Then the compression ridges are formed from the unused area. They should run fromone side of the layout to the other side. The compression ridges are not necessarily a single stripbut can be the group of strips of excess area connected with shear lines. The shear lines runperpendicular with the compression ridges. At a time of removal of the compression ridge.


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an innovative method. The compaction algorithm used is similar to the one used byCABBAGE. t is directed graph based and iterates in the vertical and horizontal directions.REST has a facility to incorporate user defined constraints. Typically, they are related withpositioning of connection points to the outside of the layout. The system does handle jog pointinsertion.

1.3.1.5. MULGAMULGA is a complete symbolic layout system running under UNIX [Wes8Ia Wes8Ibl.

A stick input is mapped into a virtual grid plane. The virtual grid is similar to the coarse gridfixed grid). In the virtual grid method, the spacing between coarse lines is determined by the

interference of neighboring grid locations. The compaction algorithm is not graph based. Thecompaction is one dimensional and the horizontal and vertical compactions are performedseparately. An adjacency information between elements is readily available through the matrixof grid, since each element is associated with grids. This is an advantage of this system. Thedesign rule checking required for compaction can be done locally and therefore rapidly. Graphconstruction in other graph based algorithms requires substantial portion of computing time.The disadvantage of the grid based system is that it can not compact as tight as the graphbased algorithm. The larger the size of symbolic elements compared to the width of wireelements, the larger the wasted space could be.

1.3.2. Problems witb tbe Existing SystemsHere we overview the deficiency of the existing systems and investigate opportunities for

further research and development.All the existing algorithms perform compaction as two one-dimensional problems. The

horizontal and vertical compactions alternate. Therefore, there is always the possibility that acompaction in one direction blocks a subsequent compaction in the other direction. Moregenerally, since the algorithms are performed iteratively, an arbitrary sequence of decisions isimposed. Thus, a previous decision restricts the possibility of subsequent decisions. The optimallayout within the restricted domain, defined by a given model, may not be achieved. The modeldefines the representation of symbolic layout, the translation scheme to the geometric layout,and the possible geometric and topological transformations allowed for compaction, and thecriterion for layout efficiency.

Another problem is that the compaction operation is performed only with localinformation. This is the case for the STICKS compiler and SLIP. In SLIM and especially inCABBAGE, the compaction is guided by a global view which is gained using a longest path ofthe graph model. However, the compaction operation itself is still basically a local operation.The global guidance is used only to select the place where the operation is applied. Assumethere are two or more operations whose combined application improves the layout. f theseparate application of any of them can not achieve improvement, then no existing systemperforms the operations. The global guidance schemes of the existing systems are insufficienteven for this moderately sophisticated decision.

There is very weak control over the final layout produced by the compaction operation.None of the operations performed is goal-directed. In goal-directed compaction, the goals givento a system guide the compaction process and the final shape of the cell. Each operation isapplied blindly to decrease the overall layout area. However, if a circuit is a sub-block of alarger system, then there is likely be a preferable shape of the layout even though the layoutmay not be the minimal obtainable. By laying out the sub-block in a certain shape, we can


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eliminate a possible dead space between sub-blocks and achieve a smaller layout for the globalsystem. The other goal that has to be considered is the position of connection points. Theexisting systems simply try to minimize the layout area without considering these factors.Among the existing systems only C BB GE has weak control over the direction ofcompaction.

In order to utilize the layout genera tor in the context of hierarchical design methods thesystem should have a provision to incorporate those goals. The fully hierarchical layoutgenerator not only incorporates the goals given but also arranges the generation process in ahierarchical manner. The system should adjust the goals for each sub-block from theinformation of their placement and the connection among them. Other important information isthe current possibilities of each sub-block to be conformed with the curren t goals. Therefore thelocal goals for each sub-block should be dynamically adjusted in the process of compaction inorder to achieve the global goal at the top level of the hierarchy.

1.4. Research ObjectivesThis section outlines our research objectives which are generally to overcome the

deficiencies of the existing compaction systems described in the previous section.The first and most important objective is to accomplish true two dimensional compaction.

Both directions of compaction horizontal and vertical directions should be consideredsimultaneously. Also an arbi trary order of decisions should not be imposed in a compactionoperation. The compaction operation therefore should not be iterative.

The compaction should be guided by global information rather than local information.Operations should be deployed which together can improve the overall layout although theymay not accomplish any local improvement.

Goal directed compaction is another purpose of this research. The compaction methodshould be able to incorporate objectives or goals given by a user or a higher level process. Thegoals that should be incorporated are concerned with the shapes of the cell and the positions ofthe connection points. t should be done elegantly with minimum overhead. These goals give auser a strong control over the compaction process and the final layout. In case goals are notsatisfiable the method should try to comply with them as much as possible. Then it shouldreport the failure to satisfy the goals.

We should not treat these objectives individually with ad hoc methods. Instead toaccomplish these objectives uniformly we need to formula te a general algorithm to solve thecompaction problem.


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12 Xl. y}) X2 Y2)

-W

Figure 2.1. Constraints between SymbolsX2 -X I ~ H I 2 W I w2

By representing all of the constants by d 12,2.1)X 2 X I ~ d I 2

Similar inequalities can be formulated for all circuit elements that might be visible to eachother during the process of compaction. f all of the inequalities are satisfied, the layout will befree from design rule violations. The objective function to be optimized under these constraintsis the area of the resulting layout, A W H. H is the coordinate of the highest segment and Wis the coordinate of the right most segment in the layout. The area A is not linear butquadratic. We can use the approximation, W H, as suggested by Otten [Otv75]. Then, we canformulate the linear programming problem:

minimize W HA x ~ b x ~ O

where A is a coefficient matrix obtained from the left hand side of inequalities such as 2.1),and x is a vector whose value represents the layout, and b is the vector obtained from the righthand side of inequali ties such as 2.1). This linear programming problem appears to generatethe optimum layout under these constraints. However, linear programming is not general enoughto handle the following situations related to the two-dimensionality of the compaction operation.Case :

In the situation depicted in Figure 2.2, the symbol B can slide either in the horizontal orvertical direction relative to the symbol A. Depending on the surrounding conditions, one of themovements may contribute more for the overall compaction of the layout than the other. Thedesign rule requirements for this case are represented as the following:

horizontal constraintsor

vertical constraints.The requirement is that at least one of the above two conditions should be met. However, this isnot linear. The legal region for the central point for B, (Xb Yb), is not convex as shown in


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IA iI

Xa,Ya) IIViti_ _ _ _ _ ----l--+_....f'o '-

Figure 2.2. Non Linearity of Compaction Operation

Ir A : 4 ~ H a ~ bI

Xa,Ya) III

- 4 _ _ _ -

Figure 2.3. Linearized but Over Constrained


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figure 2.2 as the shaded area. f the above conditions are treated as regular linear constraints,the legal region for the symbol B is as shown in figur 2.3. t is over constrained and isinadequate for the compaction. At best, we have to choose the direction of movement sliding)of the symbol B at the formulation time of the inequalities. hat is, only one of the twoconditions is generated. In figure 2.4, only the vertical constraint is generated and the symbol Bis able to move in the horizontal direction only.

A eb IIx Y.) III

V b

figure 2.4. Only Horizontal Direction Is ChosenThe linearity is preserved but the compaction operation is still severly restricted by the arbitrarydecision made at the problem formulation time.Case 2:

he second problem arises when the horizontal and vertical directions have to beconsidered simultaneously. The situation is depicted in figure 2.5. he horizontal constraint forsymbol C is different according to the relative vertical position of symbol C to symbols A and B.Only one of the constraints from symbol A or symbol B is active at a time. he condition isexpressed as follows:

if Y c Y b ~ V b c h b h c then x c x Q ~ H Q c w Q w c else x c x b ~ H b c W b W c

he above set of inequalities is not linear and the legal region for the central point of symbol Cis not convex. t is shown as the shaded area in figure 2.5. f these two horizontal constraintsare taken simultaneously regardless of the vertical relation. the condition becomes linear. hesituation is shown in figure 2.6. t is not adequate for compaction. f there are two or moreconstraints from same direction, the severest one is always taken as the constraint for allpositions, regardless of the actual design rule requirement. A similar situation arises between


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programming, it is possible to make only one of a set of constra ints hold. Consider the followingproblem:

minimiz j x), x ES - { x I A x ~ b , x ~ O } and one of the constraints

g ; x ~ 0, i - I ... mmust hold. The above condition can be replaced by the constraint set

g ; x ) ~ o ; K g i - I ... mm1:o ; -m- I

i I0;-0 1 i - I ... m

where Kg is a known lower bound of gj.I f there are m alternative layouts for a single circuit element, then we can generate msets of constraints. Each set corresponds to one layout of the circuit element. Using the above

technique, we can make only one set of constraints active. The best layout is chosen by solvingthe formulated mixed integer programming. For the rotation of a circuit element, two or moresets of constraints can be generated. Each corresponds to the rotational orientation of a singlecircuit layout.

2.5. Difficulty witb Mixed Integer Linear ProgrammingThe model based on mixed integer linear programming is very general as described in the

previous sections. The problem with this formulation is that solving a general form of mixedinteger linear program is very costly. We expect a fairly large number of 0-1 variables, possiblyin the hundreds or even thousands.Mixed integer programming problems can be solved by a separation method(Partitioning). The method is called the Benders s decomposition algorithm [Ben62l. Thedecomposition algorithm separates the mixed integer programming problem into an integerprogramming part and a linear programming part. The method was successfully used in adistribution problem [GeG7Il. The implicit enumeration method [BaI65, Geo69 l was used tosolve the integer part of the problem. However, the decomposition method is very sensitive toproblem formulation, and slight changes in formulation can effect its efficiency [GeG71 l.

A more common class of methods for solving mixed integer programming problems is thebranch and bound method. One branch and bound algorithm uses a linear relaxation method ateach step of the branching operation [LaP73]. In this method the integer condition is relaxed.At each node of the branch and bound search tree, the method solves the linear programmingproblem where the integer variables, o s, are allowed to take on real values between 0 and 1.According to the solution of the relaxed linear programming problem, one integer variable, 0;is chosen as a branching variable. Each branch after separation represents smaller mixedinteger programming problems where 0; is eliminated from the problem; one branch correspondsto the problem where O is set to 1, and the other corresponds to the problem where 0; is set toO Leaf nodes correspond to problems where all 0 variables are fixed. The simplex method canbe used to solve the linear programming problem. Though the simplex method is empiricallyknown to be fairly fast algorithm, it is still an expensive operation if used repeatedly. t isimportant to reduce the required amount of computation at each stage of the branch and boundmethod.


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Because we have a large problem th t has a special structure we did not pursue thesegeneral methods of solution. Rather we imposed some restrictions on the problem formulationand constructed a special purpose algorithm based on heuristics and branch and bound methods.n the next chapter we will develop a refined model which sacrifices some generali ty to achievefaster computation.


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CHAPTER 3

Graph Optimization

3.1. IntroductionIn this chapter, we formulate the branch and bound method using graph optimization

concepts. t is a direct refinement of the formulation given in the previous chapter. The newformulation uses the branch and bound method for deciding values of integer variables, and ituses the longest path algorithm instead of linear programming at each stage of the branch andbound method. t also takes advantage of the special structure of our problem. A similar graphtheoretic model and the longest path algorithm is used for digital circuit optimization byLeiserson, Rose and Saxe [LRS83] in context of retiming.

3.2. Input Conl'entionLet us quickly review the assumptions about symbolic input. The input consists of

symbols and their interconnections. These symbols are enhancement transistors, pull-uptransistors, and poly-metal contacts, etc.. The symbols are represented by their minimumenclosing rectangles of their layouts. A single interconnecting wire (or line) must be a straightline without any bend. A wire must be in either the horizontal or vertical direction, anddiagonal wires are not allowed. A wire segment must connect to other elements at both ends.These terminating elements can be symbols, wires in other directions, or the surrounding bordersof the layout. The length of a wire segment is decided by the coordinates of these terminatingelements. t behaves as if it were a rubber band.

3.3. Grapb NodesTwo related graphs are constructed whose nodes represent the x and y coordinates of

symbols and connecting wires of the layout. The correspondence between the input layout andthe nodes of the generated graphs is as follows. For each symbol, we assign two variables; onefor the x-coordinate and the other for the y-coordinate. These variables correspond to the nodesof the graphs on which the compaction algorithm operates. A connecting wire between symbolsis assigned only one variable. f a wire is vertical then it has an x-coordinate variable and if it ishorizontal then it has a y-coordinate variable. The relation is depicted in Figure 3.1. Twoseparate but interrelated graphs are constructed. All x-coordinate variables have correspondingnodes in a horizontal graph, and y-coordinate variables in a vertical graph. ur compactionalgorithm is based on the inter-relation of the two graphs.

Even though these two graphs are directed graphs (digraphs), they are designated by theterm gr ph in this thesis. There are four special nodes which correspond to the four borders ofthe whole layout. Left and right borders have x-coordinates, therefore they have correspondingnodes in a horizontal graph. They represent the source and the sink of the graph. Top andbottom borders have corresponding nodes in a vertical graph and they represent the source andthe sink of that graph.

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dl

0( X2 -Xl> dldlXl X2

a. symbol- symbol

d2

d2 X4 -X3 >d2X3 X4 b. wire - symbol

d

d3 X6 -X5 >d3X5 X6

c. wire - wireFigure 3.5. Simple Arcs

3.4.2. Distance Requirements Imposed by Design RulesA separation arc in the graph corresponds to the minimum distance requirement between

two elements. The head node and the tail node of the arc represent the two elements involved,and the distance is represented as the weight of the arc. Minimum distance requirements aredefined so that an arc points from a node in a predecessor group to a node in a successor group


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according to the group ordering. Arcs usually point from left to right and bottom to top.We make the graphs enforce the design rules. f all requirements represented by arcs

have been met, then the resulting layout is free of design rule violations. The graph generationalgorithm has to create an arc between any pair of symbols for which there is a chance thatthey can violate a design rule by being too close.If two symbols are directly connected by a single straight wire, the distance requirement isonly in one direction as shown in Figure 3.5a. This is an example of a simple arc generated

xl, yl) dl'

d2,

-,.

12. y2)

Horizontal Graph Vertical Graphx xl >dl y y2 >d2

dl

d2

Figure 3.6a. Dual Arcs: Symbol-Symbol


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from design rules. Simple arcs are also generated between a wire and a symbol Figure 3.5b)and between wires Figure 3.5c).

When two symbols are not connected by a single straight wire but are located close toeach other, there is a pair of constraints as shown in Figure 3.6a. One of them is in the verticaldirection and the other in the horizontal direction. A pair of arcs must be constructed; one in avertical graph and another in a horizontal graph. These pairs of arcs are called dual arcs. For

13 d3

y -Id415. yS)

Horizontal Graph Vertical GraphxS -13 d3 y4-yS d4

d4

Figure 3.6b. Dual Arcs: Symbol-Wire


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he important point is that both the vertical and horizontal graphs consisting ofseparat ion arcs (i.e. simple and dual arcs) are acyclic. This is because the direction of arcs isdecided according to the ordering of the groups. he tail node of an arc always belongs to agroup preceding its head node in the ordering.

3.4.3. Connection Constraints between Symbols and WiresIn the course of compaction, it is necessary to maintain connections between symbols and

their connecting wires and among wires that are connected. A pair of constraints is used torepresent a single connection requirement. This method also allows a wire and its connectedsymbol to shift relative to each other if the symbol s connection node is wide enough.

We explain the representation of the connection requirement between wires and symbolsusing an example shown in Figure 3.7.

3 x2I c II symbolI

connection node

I III . nII I I II I I I

I I wir I I

I\\\I 1 III I II d d I1 + +,

xl

Figure 3.7. Connection ConstraintsLet Xh X2 X3 be the center coordinate of a wire, a symbol and a connection node of the symbolrespectively, and let w , WI be the width of the connection node of the symbol and the wire.Now define w,,-wl)/2. Then the connection requirement is I X I X 3 1 ~ d which is equivalentto


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X 2 - X l ~ - d c x - x 2 ~ - d - c .

The resulting arcs form a cycle between nodes which represent the wire and the symbol Figure3.9).

-d c -d c

Figure 3.9. Connection Arcs in Horizontal Graph

A BL2rIIIX

IIXu

rI

Ll II

Figure 3.10. Connection between Wires

he connection requirement among wires is slightly different. Figure 3.10 shows a verticalwire L connected to a horizontal wire L 2 The horizontal wire is connected to symbols A andB he central coordinate of the vertical wire L has to be between the terminating elements ofline L 2 to maintain the connection. Therefore, the connection requirements between L and L 2are represented by the following two inequalities:


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X/.-X Q X b X / ~ d b

where d Q and db are distance requirement between symbol A and wire and between symbolB and wire L respectively. They not only secure a connection between two lines but alsoseparate the vertical wire and two terminating symbols. Therefore, these arcs are treated asseparation arcs rather than connection arcs. No special arc is necessary at a connectionbetween a wire and a border.

Since the connection arcs destroy the acyclic character of the graphs, they need specialhandling in the longest path part of our compaction algorithm.

3.4.4. Arcs and GroupsThe arcs representing a connection requirement of a vertical wire with its terminating

elements are present in the horizontal graph because they constrain a horizontal movement ofconnected elements. A layout and its horizontal graph are shown in Figure 3.11 and in Figure3.12. he vertical groups appear as the alternating nodes and arcs, and they form a chain ofpairwise cycles in the horizontal graph. The horizontal groups appear in the vertical graph.Note that connection arcs connect nodes in the same group, whereas separation arcs, whichrepresent the design rule requirement, connect nodes in different groups. Within the samegroup it is only necessary to generate arcs among closely neighboring elements. For example,consider a vertical group which appears in a horizontal graph and not in a vertical graph. Forelements within the same vertical group, it is necessary to generate only the following: simplearcs among neighboring symbols in the vertical graph


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3

5

2

-

-

4

6

7

Figure 3 11 Single Vertical Group Figure 3.12 Vertical Groupin Horizontal Graph

horizontal parts of dual arcs. For each element of x there is a corresponding vertical arc as adual pair. R is a set of connection arcs for the vertical groups.

Wx-{Wi/ I EEx, wi ER}is a set of weights. Here R is the set of real numbers. A weight is attached to each arc and itrepresents either a horizontal distance requirement or an amount of freedom of movement at aconnection point.

The vertical graph Gy is defined similarly:G {Ny. e; Wy}

where Ny, Ey-AyU DyU Ry, Wy are defined analogously for the vertical direction.


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3.5.2. Decision VariablesLet I be an index set into D, and Dy- I f iEI then e /EDx' e/EDy, and is a

pair of dual arcs. By construction, Dx and Dy have the same number of arcs.For i-th pair of dual arcs, let us introduce decision variables b;. Each decision variablecan take a value from to l]. We denote a vector of decision variable by b.

3.5.3. The Optimization ProblemWe now formulate the optimization problem. For each node X EGx and Y; EGy , we assigna value Xi, Yi' representing positions of symbols and wires in a layout. We use the node name

and its value interchangably in this section.The vector z- is said to be feasible if the following three conditions are

satisfied:(I) For each arc e EAx U Rx ; e-X} Wi/'(2) Similarly for each arc e EAy U Ry ; e-

Y j Y ; ~ w;/0) For each iE/, let i-th pair of dual arcs be where e;x- and

e / - ThenXk - Xj Wjk x if b;-OYk - Y} Wjk Y if b;- l .

Let n- {zIz-; z is feasible} be the set of feasible points. Our optimizationproblem is:

min f(x,y) 0.))zEOwhere f(x, y) is the objective function. Ordinarily the objective function is the area occupied bythe layout. That is f x ,y) - (tx - sxHty - Sy). Without loss of generality, we will assumeSx - Sy-O. therefore, f (x, y) - tx ty .

The graphs G, and Gy encode systems of inequalities. They are related to each other bythe dual arc pair and corresponding decision variables b; for each iE/. Thecompaction algorithm of the layout is to find the 0 1 vector with which vectors x and y takevalues minimizing f(x,y) . We use a branch and bound method to decide the values of and alongest path algorithm to find the values of x and y. The method for compaction is described inChapter 5.

3.6. Restriction of The FormulationThe ordering of the groups and generation of separation arcs according to this ordering is

a restriction we imposed on our method. Because of this restriction, there is no positive cycle inthe graphs G, and Gy A positive cycle is a cycle of arcs whose weights sum up to a positivenumber. Furthermore, their subgraph, and without connection arcs, are acyclic graphs.G , and are defined as


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G x-{Nx Ax U o.. Wx}G ~ - { N y , AyU Dy Wy} .

he only cycles in the graphs Gx and Gy are pairwise loops consisting of arcs in the set R, andRy and for all of them the sums of weights of arcs in each loop is non-positive. Therefore it ispossible to use a method which is a slight modification of a longest path algorithm on acyclicgraphs.

What we sacrificed to gain this advantage is the ability to formulate the three waydecision or four way decision of relative positioning of two symbols. We can only have onechoice in each direction horizontal and vertical. he example in Figure 3.13 represents twosymbols A and B.

Idx

IIB

yI ~

r .L J -Figure 3.13. Two Symbols A and B

heir possible relative positions are also indicated. he dual constraints generated are asfollows:

Y b - Y Q ~ d . With these cons traints symbol A is not allowed to move up to the right side of symbol B.Therefore the positioning shown in Figure 3.14 never occurs.

BD AFigure 3.14. Impossible Position for Symbols A and B

Now assume two symbols are connected to wires as shown in Figure 3.15. Obviously the abovedual cons traints are less than desirable. he better constraints which are likely to give twosymbols more freedom to move relative to each other are the following:


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B

A

Figure 3.15. Two Symbols and Their Connected Wires

Xa Xb Y b Y a

The direction of the horizontal arc is reversed. However the first constraints can not simplyreplaced by the second. In order to change the direction of the horizontal arc between symbolsA and B t is necessary to reverse the direction of all arcs between the two groups to whichsymbols A and B belong. Otherwise a positive cycle may be generated. t is possible to designan algorithm to reorder the groups considering not only relative positions but also connectionsamong symbols and wires. This overcomes the problem with this particular example. Howeverthe basic restriction the fact that we can formulate only two way choices remains. A possibleremedy using an iterative approach is presented in hapter 6.


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Figure 4.2 shows an example of an enhancement mode transistor whose length/width ratiois 112. The data structure that represents this symbolic element is shown in Figure 4.3. Itconsists of two rectangles; one polysilicon rectangle and one diffusion rectangle. Theserectangles directly correspond to the Box commands of Clf', By applying the node extractionprocess, the graph generation algorithm creates the data structure shown in Figure 4.4. Here,one diffusion rectangle is separated into two smaller rectangles and they form two independentelectrical nodes. Also, one rectangle in the channel layer is created. he numbers in the figureindicate electrical node numbers assigned. Three electrical nodes are extracted.,: : ; ; . : : : : : :.

'::::': ::.:.

Figure 4.2. Enhancement Mode Transistor

::::,: '::::;,: .:::::.:: ,::::::::, ::.:: :;

Diffusion PolysiliconFigure 4.3. Representation of the Transistor

11 /dkLd

Diffusion Polysilicon ChannelFigure 4.4. Representation of Electrical Nodes

Once the electrical node extraction is completed for each symbolic library element, therest of the node extraction operation is fairly simple. It is only necessary to take care ofconnection wires and individual instances of the library symbols. For each instance of a symbol,a separate set of electrical nodes is generated according to the previously extracted electricalnode information. In the above example of the enhancement transistor, three electrical nodesare generated for each instance of this symbol. Then, an equivalence relation is constructedamong electrical nodes of symbol instances. Two electrical nodes are electrically equivalent if


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, ,II I I I< >:< >:: 2> : 2> : 3> :I ,

Figure 4.6. Two Polysilicon Rectangles

extension of the polysilicon rectangle in symbol B from symbol s center toward the left isWb - 3).. The design rule requires at least 2A separation between polysilicon layers, assumingthey belong to different electrical nodes. t is represented by Sob- 2).. he distancerequi rement between the central points of symbol A and B, considering only two polysiliconrectangles, is the sum of the above three numbers, Wo Wb+Sob, which is 7), in our example.

he relation between two polysilicon rectangles is represented in Figure 4.6. In this case, thecenters of the rectangles coincide with the centers of the symbols to which they belong, but it isnot always true. he distance requirement between the centers of two symbols, not the centersof two rectangles, is computed. In order to calculate the minimum distance requirement betweensymbol A and symbol B, we have to perform a similar computation for every combination oftheir constituent rectangles. For example, considering a polysilicon rectangle of symbol A and adiffusion rectangle {there are two rectangles but either one is fine} of symbol B, we haveW 3) Wb-l ., and Sob-lAo Therefore we have a 5), separation requirement. f there is noseparation requirement rule between the two layers involved, for example between metal anddiffusion layer, or they belong to the same electrical node, we do not produce any separationrequirement. We take the maximum of these separation requirements calculated between everypossible pair of const ituent rectangles of the two symbols. In the above example, the finaldesign rule requirement is 7>

4.4.2. Connected Elements without Freedom of Mo\ ementIn the previous section, we described the general method of computing a mimmurn

distance requirement between two symbols. This method produces an over-constraining value incertain cases. Consider the situation illustra ted in Figure 4.7. Here, a horizontal wire Lconnects a symbol A and a symbol B. Since two elements are connected by a single wire, wegenerate a simple arc between corresponding nodes in the horizontal graph Gx . The arc ispointing from a node corresponding to A to a node corresponding to B. f the weight of the arcis calculated by the method described, it will be 7).. he half width of the polysilicon rectangleof symbol A is 3) the half width of the diffusion rectangle of symbol B is 3) and the minimumspace requirement between polysilicon and diffusion layers is I) , yielding 7> as the minimumdistance requirement . However, this is overly restrictive. Figure 4.8 depicts a situat ion that theabove minimum distance does not allow, even though the layout is perfectly legal. heconstraint between the polysilicon rectangle and the diffusion rectangle is erroneous in this case.Figure 4.9 shows the positional relation of these two rectangles. They have I). of verticalclearance {separation}. Because these two elements are directly connected by a single wire L,and because there is no freedom of movement at the connection nodes {diffusion rectangles} of


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IIIIIIII1

Figure 4 7 Two Connected Symbols

IIII II 1

:I I6>.Figure 4 8 Legal Layout


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Figure 4.9. Fixed Vertical Clearance

both symbols and wire L this clearance is always guaranteed. Therefore as far as thepolysilicon layer of symbol A and diffusion layer of symbol B are concerned we should notgenerate a minimum distance requirement. The proper minimum distance requirement betweensymbols A and B is 6> , resulting from polysilicon-polysilicon considerations.f we are to generate a minimum distance requirement between two directly connectedelements whose relative position in the orthogonal direction is fixed then we should take intoaccount the separation in the orthogonal direction. For each pair of constituent rectangles theirorthogonal separation is compared to the minimum distance requirement of the design rules. ftheir separation is greater than or equal to the amount required then the minimum separationrequirement in the original direction is not necessary for that pair of rectangles.

As a special case of this situation consider the case drawn in Figure 4.10. Here ahorizontal wire L connects a symbol A and a vertical wire L 2 f we do not consider a fixedvertical separation between the diffusion rectangle of symbol A and the polysilicon layer of wireL 2 the resulting minimum distance requirement between two elements is 4> . This is of courseover constraining. In this particular case we do not need to generate any distance requirementbetween these two elements. Therefore we do not have any simple arc between thecorresponding nodes. This allows much freedom and all the positionings shown in Figure 4.11are possible.

4.4.3. Choosing Between a Simple Arc and Dual ArcsAs described in Chapter 3 a simple arc is produced if two elements are connected directlyby a single wire. Otherwise a pair of dual arcs is usually generated. A pair of dual arcsintroduces one decision variable. A pair of dual arcs is therefore much more expensive than asimple arc in terms of computation.There are certain cases where two elements are not directly connected but we mustgenerate simple arcs in order to maintain non-circularity in the following subgraphs:


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A

IIIIIIII

I I

4 .Figure 4.10. Connection between Butting Contact and Poly Wire

Figure 4.11. Legal Connections

o - {Nx Ax U o. Wx}o {Ny Ay U o; Wy}.This restriction prevents generation of positive cycles in the graph G and Gy We presentmethods for generating either a simple arc or a pair of dual arcs for the following three cases;symbol-symbol, symbol-wire, wire-wire.

Let s introduce some notation. For a given symbol or a wire A, vg(A) represents thevertical group number to which it belongs, and hg(A) represents the horizontal group number.For a horizontal wire segment L , vg(L,,) is null, and for a vertical wire segment 4 hg 4) isnull.

4.4.3.1. Symbol-SymbolAssume two symbols A and B are given and they are not directly connected. We need to

generate a pair of dual arcs between them if they belong to different horizontal and verticalgroups. f they belong to the same group in one of the directions, we should not generate a pairof dual arcs. Moreover in that case, we do not need to generate a simple arc between themunless they are connected to each other by a single wire.


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Figure 4.12 represents symbols A and B belonging to the same vertical group but notdirectly connected.

A

B

Figure 4.12. Two Symbols in the ame Vertical GroupIn this case, the central points of A are located to the left of the central points of B. Eventhough symbol A is located to the left of symbol B, we should not generate any arc from nodeo to node Xb f we do, it can form a positive cycle with other connection arcs in thehorizontal graph Gx Furthermore, we do not need any arc from node Yo to node Yb SymbolsA and B being in the same vertical group implies that they are connected by a series of verticalwires without any horizontal wires. We do generate a simple arc between two symbols directly

connected by a single wire. Therefore we have a series of simple arcs from node Yb to o whichguarantees their separation.

f two symbols belong to different vertical groups and different horizontal groups, wegenerate a pair of dual arcs between them. We generate each arc considering their groupnumbers, so that the resulting arc points form a node with smaller group number to a node withlarger group number.

4.4.3.2. Symbol-LineGiven a symbol A and a wire segment L that are not directly connected, we have to

decide whether we should generate a pair of dual arcs or a simple arc. Assume the wiresegment L is horizontal without loss of generality. The situat ion is depicted in Figure 4.13 withtwo terminating symbols of the wire L


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ADFigure 4.13. Symbol A and Wire L

By the definition of the wire segment, a horizontal wire L does not have an x-coordinateand it is not represented in the horizontal graph Gx . In order to express a situation wheresymbol A is located entirely on the right side of wire L, we need to use x-coordinate variable Xcof symbol C. That is

which represents an arc from node x to node XQ This guarantees that symbol A and wire Lwill not interfere each other. A similar argument holds for the case where symbol A is locatedentirely to the left of wire L We have:

4.2)which represents an arc from node X Q to node Xb Both constraints, 4.n and 4.2), should notexist simultaneously. Since there is a simple arc from node Xb to node Xc a positive cycle isgenerated if both constraints 4.1) and 4.2) exist. The situation is shown in Figure 4.14.

Figure 4.14. Positive CycleThis positive cycle corresponds to physically impossible conditions. The arc in the verticaldirection is straightforward. t points from node y to node Y and represents the inequality:


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(4.3)The method considers the vertical group numbers of the three symbols involved, A, BandC, for choosing a simple constraint or dual constraints. There are three possible cases; one fora simple constraint and two cases for dual constraints.

(I) vg(B) vg(A) vg(C). n this case, a simple arc is generated. It is in the verticalgraph Gy and corresponds to (4.3).(2) vg(A) vg(B). Here, A pair of dual arcs is generated. One of them is the arccorresponding to (4. I) and the other corresponding to (4.3).(3) vg(A) > vg(C). n this case, A pair of dual arcs is generated. One of them is the arccorresponding to (4.2) and the other corresponding to (4.3),Since vg(B) vg(C), the above three cases cover all possibilities.

4.4.3.3. Line LineGiven two wire segments, L) and L 2, it is necessary to generate constraints only if theyare in the same direction. f one of them is vertical and the other is horizontal, no constraint isnecessary between them. The conditions checked are similar to the previous case. Assumingboth wires are horizontal, as in Figure 4.15, which shows four symbols directly connected to thewires L and L 2 A vertical component of the dual arc between two wires L 1 and L 2 isstraightforward, and it points from node YI, to node YI, in the vertical graph Gr This arc is alsoshown in Figure 4.15.

Figure 4.15. Two Wires L and L2

The method considers the group numbers of symbols A, B, C and D for choice of a singleconstraint or dual constraints. n the latter case, a proper horizontal arc is also chosen accordingto their group numbers. The following three cases exist; starting with a case for dualconstraints:(I) vg(B) vg(C). n this case wire L) may be located entirely on the left side of wire L 2A pair of dual arcs is generated. Its horizontal component corresponds to the followingconstraint:


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other but they can become visible to each other. On the other hand, there is a pair of elementsth t never become visible to each other. No constraint should be generated between them. Onettempt to capture this locality of interaction is the following idea of compartmentsConsidering symbols, wires and boundaries as walls, we can regard an empty areasurrounded by these walls as a compartment. In constructing compartments, two separate

planes re distinguished in our nomos layout. They are a metal plane and a poly-diffusion planeconsisting of other layers diffusion, polysilicon, implant, cut, buried cut). Figure 4.16 showsthe compartment in the poly-diffusion plane for the T-ftipflop example. For the entire stick


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The compartments are constructed by a scan line method (a pond and island algorithm).The technique is used in computer vision lBaB82, p l Sl ] and is also applied for node extractionfrom mask layout of integrated circuits lBak80, BaT80). The layout is represented by a twodimensional bit array, each bit representing a lambda square. f a bit is one, there is somecircuit located on the corresponding position of the layout. f it is zero, there is no element inthat position. These algori thms process a single bit (picture element> at a time, and theydistinguish each empty space, which is a group of connected zero bits, as a compartment. Thedata structure used for representing a layout is not a bit array but a set of rectangles.Therefore, to speed up the procedure, the idea of an event list lBHH8 ] is used. Each eventrepresents a start ing edge and a trail ing edge of each rectangle of concerning layers. tidentifies isolated empty spaces separa ted by symbols and wires. This operation is performedtwice; once considering only metal rectangles and a second time considering all other rectangles.

4.6.2. Reduction by Transitive ClosureEven though compartments are used to reduce unnecessary arcs, a fair number ofredundant arcs may still remain. The another group of redundant arcs results because

constraints between elements propagate through more than one arc. Consider constraintsrepresented by a graph shown in Figure 4.17.

4

Figure 4.17. Transitivity of ArcsThere are three horizontal coordinates of three elements represented by Xa b and x. Assumethat there are three separate constraints as represented by three arcs in Figure 4.17. Alsoassume that arcs and belong to Ax R; and not to Dx. The weights ofthe three arcs and are 2X 3X and 4X respectively, as shownin figure 4.17.

The sum of weights of arcs and is 5X. Therefore, the elements Aand C are required to be separated by 5X. Since these two arcs belong to Ax Rx they arealways present. Therefore, 5X separation is always required. This requirement of 5X is largerthan the weight of arc which is 4X. The minimum separation requirement betweenelements A and B, calculated directly, is 4X but they are forced to be separated by 5X by twoother arcs. The arc therefore, becomes redundant in this case, and it can be


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eliminated.Now, we consider a case where arc belongs to Dx . Let ejX and thei-th dual pair be . Since e/ is redundant and its requirement is always satisfied, wedo not need to consider a requirement represented by e/ at all. Therefore, the i-th pair of dualarcs can be eliminated altogether. Since each dual pair introduces a 0-1 variable and ispotentially costly in computation, it is very helpful to eliminate one.No arc belonging to R; is eliminated by this transitivity. This follows directly from the

construction of graph Gx Remember all arcs in R; connect two nodes in the same verticalgroup and adjacent to each other. However each arc in Ax Dx connects two nodes thatbelong to different vertical groups, and always points toward groups with larger groupordering) number. Therefore there is no alternate path from a tail node of an arc in R; to itshead node. Similar arguments hold for vertical graph Gy

Let us summarize the above discussion. Let u and v be two nodes in a graph. Assumethat there is an arc < u, v>. Assume further that there is a path from u to v consisting of twoor more arcs in set A R An arc < u, v> can be eliminated if its weight is smaller than orequal to the sum of weights of all arcs in the path. Moreover, if arc is a part of dualarcs, then one can eliminate its counterpart in the graph for the other direction. No arc of setR is eliminated by this operation because of the rules governing its construction.


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Forgiven vectors 011 and IJ.II, thelower subgraphsaredefined as:gi o\ IJ. II) - {Nx , Ei(OIl, IJ.II , Wx }

andg;(OIl, IJ.II) - {Ny , E; o\ IJ.II , Wy }

gi(OIl, IJ.II is a subgraph of G, andg; o\ IJ.II is a subgraphof Gy Thearcs in gi(OIl, IJ.II areall of thearcs in Ax U R and thesubset of Dx whose decision values arepermanentlydecidedto be O. Moreformally,Ei(OIl,IJ.II) - A x UR x UDi OIl,IJ.II)Di(oll,IJ.II)-{e;le;EDx , o f- 0 andIJ.f- I} .

Similarly for thevertical direction,D;(oll,IJ.II)-{e;le;EDy of 1 andIJ.f- I }

In the lower subgraphs, not all of the dual arcs are represented. Only a permanentlydecided pair has its members represented either in gi 011, IJ.II or in gJ011, IJ.II . Therefore, evenif all of the inequalities associated with thearcs in 011 IJ.II and g; 0\ IJ.II are satisfied, theresultingz - maynot be feasible.

There are two special nodes, a source and a sink, in each of these subgraphs. They aredenoted by s; and ; for the upper subgraph g;(oO). Similar notation is used for othersubgraphs. 1;- s; represents an upper bound of the width of the layout and I i - sDrepresents its lower bound.

5.3. Mechanism of the Branch and Bound MethodHere, we describe the overall mechanism of the branch and bound algorithm. Thepurpose of the branch and bound is to remove a dual arc from a longest path of the upper

graphsandenter its counterpart in theotherdirection. At each stepof a branchand bound, thealgorithm constructs a longest path spanning tree rooted at a source node for each of the foursubgraphs. From the spanning trees of the upper subgraph, the following two kinds ofinformation are obtained. The first is coordinates of symbols and lines of a layout. In thislayoutall of theelementsarepacked to the left and to thebottomas muchas possible satisfyingcurrentlyactive constraints. Thesecond is sets of arcs which make up the longest paths in thislayout. The spanning trees of the lower subgraph are used to calculate lower bounds on thewidth andheightof thelayout.

In order to explain a branchingoperation at some node in the branch and bound searchtree, we assume thefollowing condi tions withoutloss of generality(J) IJ.;-O, i.e., a decision madeon i-th dualpair is temporary.(2) 0;-0 i.e., an active arcin the i-th pair,


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ej is on the longestpath ofgraph gxU(a )

Correction Endorsement

Figure 5.1. Single Branching

0;: ... 0;It;:- I

The correction operation modifies three subgraphs; two upper graphs and one lower graph. Theother branch is called an endorsement branch. An operation associated with this branch is to setIt to one. This endorses the initial temporary decision on i-th pair of dual arcs. Theendorsement operation modifies only one subgraph one lower graph. Since the purpose ofbranching is removal of a dual arc from a longest path a correction branch is always exploredfirst. An endorsement branch is explored only aft er the corresponding correction branch iscompletely searched.

After a branching is made some of the longest paths must be reconstructed. In thecorrection branch it is necessary to update three spanning trees. he arc e/ is removed fromthe graph g;


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5.4. Pruning ConditionsHere, we consider the conditions under which one can prune a certain subtree in the

branch and bound search tree.At each node in the branch and bound search tree, two functions are evaluated; and LLet us denote an arb itrary current node by. . Then the situation is shown in Figure 5.2.

r t

Figure 5.2. Branch and Bound Search TreeThese two functions represent a local upper bound and a lower bound of an area occupied by alayout.1 t: s:Ht; s; upper bound

i - t ~ - sJ lower bound.The value of i increases monotonically as a search process goes deeper into the search tree.This is because the number of l's in the vector t is equal to the depth of the node. from theroot, and its components are never reset from 1 to 0 by going down.

The global best upper b o u n ~ f of f(x,y) is maintained. This upper bound is updated ateach time the local upper bound f becomes smaller than the value of f*. This value representsthe currently known best solution. t is also necessary to maintain vectors x, y associated withthe global upper bound f*. They represent actual coordinates of the symbols and lines of thecurrently known best layout.

An ~ t i m a l area, f , obtainable in the subtree rooted at the node. is bounded by thefunctions f and i calculated at node n


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i ~ ~Note that the bounds calculated at the node T hold for the whole subtree under T/

We now present the following two pruning conditions:i : 5.0i-f

Condition (5.1) indicates that any solution which could be found in the subtree rooted at node Tis greater than or equal to the currently known best solution. Therefore, we can cut this subtreefrom the search tree.Condition (5.2) shows tha t the values of the upper bound and the lower bound equal eachother. There will be no further improvement in the subtree under this node T/ Actually,condition (5.2) is absorbed in condition 5.0, since, as soo as an local upper bound f isevaluated, it is compared with the global upper bound [ , f f -c], the global upper bound isupdated to a value f. Therefore, it is only necessary to check condition (5.t>.

5.5. Construction of Longest Path Spanning TreeThe graphs do not have a positive cycle because of their construction. Therefore, theBellman-Ford successive approximation method [Law76] can be used for determination of thelongest path. Its run time is O n 3) where n is the number of nodes in the graph. In order tofind the longest path, a longest path spanning tree is constructed. The spanning tree alsoprovides the coordinates of all elements in the layout.Since our graphs are in very restricted form, the Bellman-Ford successive method is notused in its most general form. Our graphs are almost acyclic. The cycles appear as pairwiseloops, which represent connection between symbols and lines. Therefore, one can use analgorithm which is a slight modification of the longest path algorithm on an acyclic graph. Theruntime of the acyclic graph algorithm is linear in the number of arcs. First, the acyclicalgorithm is outlined. In this algorithm, a topological sort is performed to order the nodes,

so that there is no arc from node z, to Zj, if i j Then, the following computation isperformed:Zl 0zJ max{zk+wkJ']' j- 2, ..., n.k is an arc in the graph.It is necessary to modify this algorithm so that it takes care of pairwise loops created byarcs belonging to the set R, and Ry The nodes in our graphs cannot be ordered as in the caseof an acyclic graph. There is not a part ial ordering among nodes in our graph. However,there is a total ordering among groups of nodes. Within these groups, nodes are connected byarcs in the set R; and Ry .The modified algorithm is explained in the following. Let the i-th group be denoted byQj. Construct the following ordering of nodes, which is based on a total ordering of groups:QIo Q2' ..., Qj Qn

where


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Q;- Qj+l-

Qn- Within a group order the nodes according to the positioning in the input layout. Node Z I is asource node sx or sy); node Zn is a sink node Ix or 1y) . They form a group by themselves.Perform the acyclic algorithm for each node from left to right in the above ordering untilencountering the end of the group. In this step consider only arcs in set Ax UD, or A y UDy After having computed values of all nodes in one group traverse all nodes in this group fromleft to right checking whether conditions represented by arcs in set R are satisfied or not. Thatis done by checking if the following two inequalities:

Zj +wijZ; +Wj;

are satisfied or not. I f there is an inequality that is not satisfied satisfy it by updating a valueof the appropriate node. It is only allowed to increase a value not to decrease it. Thenbacktrack from the updated node to the left to take care of the ripple through of the newincrease. Backtracking terminates upon finding a pair of satisfied inequalities. Then resume theoriginal process from the node which originally caused the backtracking. Reaching the lastnode in a group implies that the positioning of elements within tha t groups is consistent. Thenproceed to the next group to perform the acyclic algori thm and the whole process repeats.

5.6. Heuristic Metbod for tbe Initial EstimateThe method for finding an initial estimate is basically iterative. Initially all of the dualarcs in Dx and Dy are activated. At each step of the iteration longest paths in the horizontalgraph and in the vertical graph are constructed. Then the dual arcs that contribute to one of

the longest path but not the other are removed by setting components of vector b properly. Assoon as some dual arcs are removed their counterparts in the other direction will never beremoved. The algorithm iterates until no more arcs are removed from either graphs. Attermination there are still some dual arcs whose components are represented in both graphs.They consist of two groups of arcs. The first group is the dual arcs that contribute to thelongest path of both directions. The second group is the dual arcs that do not contribute toeither of the longest paths. For each pair of dual arcs in both groups compare weightsassociated with a vertical arc and a horizontal arc. Then choose the arc with smaller weightand remove the arc with larger weight.

We present the algorithm more formally using an algorithmic language. In the followingpresentation we introduce two subgraphs g; b) and g; b), and assume b;E -l , 0 l] b ; lmeans that the i-th dual arcs are represented in both subgraphs g;W and g; b) Initiallyb; I for all i. Then

g;W- Nx E;W, Wx }E;W-Rx U Ax UD;(b)D;W-fe; le E x b - I or b } .

Similarly for the vertical direction:


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t:.f-t;t:.y +t;-t:.x +t:.x.t:.y.Then, the arc that minimizes the value of the above function t:.f is chosen as the next branchingarc.

One possible method of estimating the values of t:.x and t:.y is as the following. In order toavoid confusion, notation Xi is used to represent the value of node Xi in this section. Let arc e/be Yk then the estimate of the increase of a height of a layout is


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- Yk - Yk.Actually this is an upper bound on the possible increases in the height of the layout.

f one is willing to perform further computation it can be checked if the increase at thenode Yk propagates or not. For this purpose for each outgoing arc from node ko the followingis calculated:

Yz - Yk + Wk/where Yz is a head node of such an outgoing arc. f Yz then the increase of ~ y Yk atnode Yk is absorbed by slack space associated with arc . f this is true for alloutgoing arcs then the increase of is completely absorbed by slack space and the resultingincrease in layout area is zero. f Yz Yz at any node Yz, then at least part of the increasepropagates along an arc The amount of propagation is Yz- Yz. Let the largest ofYz- Yz over all such arcs be Let be defined as

- max {Yz- Yz}zThen ~ ~ y Therefore is possibly a tighter and better bound than for an increase

of height of a layout. In this method of computation the propagation of increases may result ina tree structure. f this tree structure actually reaches the sink of the graph we know the exactamount of increase. However this is a fairly involved and inefficient computation and we haveto make a trade off between an accuracy of estimation of true value of and the amount ofcomputation. In the following section we will present a more elegant and efficient method toobtain exact value of

5.7.2. Maximum Non-increasing CoordinateThe above method should not be used for computing an exact value of because it

repeatedly computes the same information for each candidate arc for branching. Instead themaximum non-increasing coordinate is calculated for each node. The maximum non-increasingcoordinate is defined as the maximum value that a node can take without increasing the value ofa sink node. This calculation is performed only once for each step of branching. The algorithmis basically the same as the one used for construction of a longest spanning tree rooted at asource node. Let us denote the maximum non-increasing coordinate associated with node z, tobe Z; For all nodes in the longest path form a source node to a sink node:

j Zj .Specifically for sink node z, which forms a root node:

Z ZOne performs the algorithm described in section 5.5 in descending ordering of the groups. Theoperation performed at the acyclic part of the algorithm is replaced byz,:- z,

Z;:- min] j wijl, i -n - l ... I .J>'Also the updating operation performed within the group is done by decreasing the value Z andnot by increasing it. A difference z . - Zj is the number that can be called cumulative slackspace. A value of node z, can be increased by this amount or less withou t increas ing a layoutdimension. Now it is possible to calculate the exact amount of increase in the dimensions of alayout. Using the example of the previous section:


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otherwise.5.7.3. erit of the lgorithm

Evaluating function t: .f is done only for arcs that are located on the longest path from asource to a sink in either graph Removal of one of them may decrease the layout area.Removal of arcs that are off the longest path does not decrease the overall dimensions of thelayout. f some pairs of arcs never appear on either of the longest paths, then the abovecalculat ion is never done for these arcs. Moreover , they are never part of the branch and boundoperation . This is an important advantage of the branch and bound algorithm presented here.Redundant arcs ones not eliminated) and non-critical dual arcs are never considered in thebranch and bound operation. The problems solved usually have a large number of integervariables but the majority of their values are set once by the initial heuristic routine and arenever reset again, because they never participate in the branch and bound operation.


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CHAPTER 6

Application and Extension of the Method

6.1. IntroductionIn this chapter, the concepts and the algorithms developed in the previous chapters are

examined for further generalities and possibilities. Especially, the goal directed compaction isdescribed.

6.2. User Supplied GoalsOne of the strong points of the compaction algorithm is that it can incorporate certain

user supplied goals and requirements as constraints. In most cases, the algorithm does not needany modification. The ability to incorporate user supplied goals is also important if thealgorithm is consolidated into a system for automatic IC layout or a silicon compiler. In thatcase, goals can be supplied by not only a human but also a higher level routine in anhierarchical layout system. In this section, we discuss two kinds of user supplied goals andconstraints which can be incorporated into the compaction algori thm elegantly. The first isrelated to the positions of connection points of the cell to the outside. The second is related tothe final shape of a compacted cell.

6.2.1; Connection PointsLaying out a single basic cell and duplicating it to create a final unit is common practicein the design of integrated circuits. A dynamic shift cell is a good example. A single basic cellis shown in Figure 6.1.

Figure 6.1. A Shift Cell

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To create an eight bit dynamic shift register, the designer duplicates the cell sixteen times in thehorizontal direction. This style of design reduces the designer s work and helps to produce amore regular structure in an IC layout. For the cell to be useful, positions of the input andoutput of the shift cell must agree with each other. This const raint can be expressed in ourscheme easily. Let node Yi represent a vertical position of the input wire and node Yj representth t of the output wire as shown in Figure 6.1. The constraint can be incorporated byintroducing a pair of connection arcs between node Yi and node Yj t is depicted in Figure 6.2.By introducing the pair, we are merging two horizontal groups to which node Yi and Yj belong.There may be certain constraint arcs th t should not be generated because of this merging.

Figure 6.2. Arcs for Connection Points

f a connection point is fixed, the algorithm should simply fix the value of that node. Letnode Yk represent a vertical position of some connection point that is fixed at a fixed position cas shown in Figure 6.3.

Figure 6.3. Fixed Height PointsThen the value of Yk must be initialized to c. At a longest path spanning tree construction step,we do not update the value of Yk However, all the calculations of values of nodes re performednormally. f the newly calculated value of r exceeds c, th t branch of the search tree isimmediately fathomed. Also, there is a possibility tha t the longest path th t determines thedimensions of layout extends from node Yk to the sink node, rather than from the source node tothe sink node. Another slight modification must be made to the heuristic algorithm for aninitial solution. The algori thm must generate a feasible solution for an initial estimate. f thevalue of Yk is greater than c, it removes the arcs th t are on the longest p th from the sourcenode to node Yk f the value of r is smaller than or equal to c, it executes as described in


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section 5.6. f the algorithm fails to achieve a value smaller than c the goal given by a user isinconsistent.

It is possible to incorporate the fixed constraints in a more general form. he longest pathalgorithm used for constructing a spanning tree must be replaced by a more general algorithm.So far all the constraints except connection constraints are constraints of the lower-bound type,that is

j xi 6.)}It is very useful if the compaction algorithm can handle the spacing requirements expressed bythe equality or the upper-bound type constra ints between two mask elements. An example ofthese constraints is as the following:

x >: xi c 6.2)x.>: xi c. 6.3)

This allows the user more control over the compaction process. Liao and Wong developed thealgorithm that can handle these constraints in the context of one-dimensionsal compaction[LiW83l. In their method, the upper-bound constraints can be represented by the graph by

cx,x c1

a b

Figure 6.4. Upper and Lower Bound Constraints

Figure 6.5. Equality Constraints


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introducing an arc pointing from the successor node to the predecessor node in their ordering.The graph representation of 6.I ) is shown in Figure 6.4a, and that of 6.2) is shown in Figure6.4b. The equality constraints are represented by using the lower-bound and upper-boundconstraints simultaneously. The graph representation of 6.3) is shown in Figure 6.5. The arcfrom node j to i is a regular arc which represents a lower-bound type constraint. The arcfrom node i to j is an arc whose direction is reversed. Let us term these arcs as left-directedarc and bottom-directed arc in the horizontal graph and the vertical graph, respectively. Theycreate a non-positive cycle in the graphs G x Their algorithm repeats the acyclic graphalgorithm up to a number of left-directed or bottom-directed) arcs. This algorithm requiresiteration of the acyclic algorithm but, it is more efficient than the most general Ford-Bellmanalgorithm. The algorithm detects the inconsistent constraints. In order to handle the equalityand upper-bound type constraints, their algorithm can be used for constructing the longest pathspanning tree in our compaction method.

11\

hkII

Figure 6.6. Height of Data Path

6.2.2. Minimum Objective DimensionIn designing a VLSI circuit, the whole layout is subdivided into blocks, which are designed

independently and placed together. In this circumstance, it is quite likely that certain blocksdo not need to be compacted less than some height or width. Fur ther compaction more than agiven goal only increases dead area between blocks. Let us call this kind of goal minimumobjective dimension. f a minimum objective dimension is given only in one direction, thealgorithm should take advantage of resulting loose space to compact tighter in the otherdirection. We describe the design method using a data path as an example.

Design of an integrated circuit as a data path is an approach of the structural designmethod described by Mead and Conway [MeC80]. The OM 2 chip is an example of a chipdesigned using this approach. One possible approach for designing a data path is as follows. Asingle bit data path is sub-divided into sections and each section can be designed separately as abasic cel\. Then, they can be placed side by side to construct a single bit data path. Finally, itis duplicated to the width of the data path. Let us assume there are n basic cells for a datapath. We denote them as CJ, ..., Cn We can design and compact them independently. Assumethat the data path runs in the horizontal direction, and let the height of each cell be representedby h for 1, ..., n. Let hp be defined as:


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Then hp is the height of the single bit data path, assuming we do not need an extra expansionrelated to connection points. Assume that hp hk as shown in Figure 6.6. Then we shouldrecompact all the cells but cell Ck with the minimum objective height of hp All we need toincorporate this goal into our algorithm is the introduction of a simple constraint arc. The arcpoints from the source node Ys to the sink node Yr and its weight is hp Figure 6.7 representscell C;, where k along with cell Ck and a simple arc introduced in the vertical graph of cellc

II hp- r

hp

Vertical Graph of ell C

Figure 6.7. Minimum Objective HeightNo modification of any algorithm is necessary to take advantage of this goal and to attempt tocompact more tightly in the horizontal direction. A goal of minimum required width isincorporated similarly.

Simple examples of the minimum required dimension are shown in Figure 6.8 and Figure6.9. They are two layouts for an inverting supper buffer. The layout of Figure 6.8 is producedwith no minimum objective dimension. The layout of Figure 6.9 is compacted with theminimum objective height of 51).. Thei r stick diagram inputs are identical, but the graphcorresponding to the layout of Figure 6.9 has one extra arc from its source node to sink node.As a result of the minimum objective height, the width of the latter layout is narrower than theformer. This results from the two dimensionality of our compaction algorithm. The dimensionsof the two layouts are shown in Table 6.1.Height ).) Width ).) Area ).2)

Layout of Figure 6.8 38 22 836Layout of Figure 6.9 51 18 918Table 6.1. Dimensions of Super-buffers


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igure 6.) O Longest Path long Vertical Group

D

C

B

Figure 6. 1. Layout Example


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The second condition is that the longest path enter a vertical group in one node and leaveit from the same node. f the node represents a symbolic element there is no place where onecan enter a jog point in this vertical group. However if the node represents a wire segment itmay be advantageous to enter a jog point in that wire. The graph representing this condition isshown in Figure 6.12 in which nodes are named as XQ Xb and Xc and node Xb represents thex-coordinate of wire B. This is the case in which we need a further check similar to the onedescribed by Hsueh. t is necessary to distinguish an interval of wire B that is directlyconstrained by existence of the element A and a similar interval related to the element C. fthese two intervals do not overlap then wire B is a possible location for a jog point insertion.These intervals can be computed from current y-coordinates of involved symbols their verticalsizes and the design rules. Figure 6.13 represents layouts corresponding to the graph of Figure6.12. Figure 6.13a shows the layout in which two intervals overlap and wire B is not acandidate for jog point insertion. Figure 6.13b shows the situation where the two intervals donot overlap.

From all possible wires for jog point insertion one should choose the wire with the longestinterval for jog insertion. In the first case the interval for jog insertion is the length of theentire wire. In the second case the interval for jog insertion is the distance between the twoconstraining intervals because the jog point must be inserted between these intervals.

a Straight Line b Jogged ineFigure 6.14. Jog Point

The jog point insertion is done by separating a vertical wire into two wires and inserting asingle horizontal wire as shown in Figure 6.14. This separates a single vertical group into twoseparate vertical groups and an entirely new h

IC Layout Generation and Compaction Module by Watanabe

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