More Than Moore

Antonio L. P. Rotondaro CTI Renato Archer

R&D Total Personnel

PhD

MS

BS

Tech

Centro de Tecnologia da Informação Renato Archer

Figures: – Total area = 320.000 m2 – Built area= 14.000 m2 – Personnel = 600

2010 Budget: – OGU: R$ 12M – Projects: R$ 22M – Total: R$ 34M

Microelectronics Software Applications

R&D Areas

HW and IC Design

Microsystems

Packaging

Qualification of Electronic Products

Surface Interaction and Displays

Software Quality and Process Improvement

Information System Security

Software Development

Robotics and Computer Vision

Decision Support Systems

3D Technologies

MISSION: Create, apply and disseminate knowledge in Information Technology, in

articulation with other social and economic agents, promoting innovations according to

society demands.

Final Commercial Product

Digital, Analog and RF 0,18 µm Technology

1st batch from Foundry Engineering Phase

Test on Protoboard

Backend & Final Tests

Geometrical Description

Functional blocs

Symbolic language description Simulation

Design House

Main Tools: Mask Fabrication Wet bench Mask aligner MJB3 Magnetron sputtering Balzers BAS 450 Optical profilemeter Zygo Pattern Generator Heidelberg DWL66 Clean rooms: 400 m2, Class 1000 & 100 w. tunnel class 10

Microfabrication and Microsystems Infrastructure

Optical

Microscope

SEM w. EDX/WDS

Teradyne MicroFlex tester

Wafer prober – Micromanipulator 6400

Logic analyzer-HP16500B

FIB/SEM dual beam (@UNICAMP)

Characterization and Failure Analysis

Focused-Ion-Beam Scanning Electron Microscope

Burn-in

Climatic chamber – Vötsch 7033

Sample preparation

Thermal cycling chamber Vötsch 7012

Reliability and Certification Lab

IC Packaging Group

Prototypes; Components 01005; Printer, Pick&Place, Reflow;

Project

Failure Analysis

Multi Chip Modules (MCM)

SMT Asembly

PCB, Hybrid Circuits, Multi-Chip-Modules;

Chip-on-board (COB); Wire Bonding of Au or Al; Custom Capsules;

X-Ray & Ersascope; BGA & µBGA reballing; Wire-bonding;

Alumina or Silicon substrates; 3 Metal Levels; Embedded Components: Resistors, Capacitors e Inductors;

Available IC Packaging Technologies

Technologies Bump Deposition Stud Bump Wire Bonding Flip Chip Wafer Thinning Stacked Dies IR Sensors

RFID MEMS &

BioMEMS Memories

Aplications

IC Packaging Techniques

Wire Bonding

BGA assembly

Chip-on-board Assembly

Customized Capsules and Connectors

Technologies

Hermetic Sealing Metal/Ceramic Joint

IR Sensors RFID MEMS & BioMEMS Memories

Aplications

Organic Electronics

Flexible Solar Cells

Bulk-heterojuction Solar Cells PET ITO PEDOT P3MET/

CdSe QD Al/Ag

Nanomaterials

Nanostructures Fabricated by Sputtering

Applications: Electrodes; Sensors; Memories; Surface Functionalization

[1] R. R. Tummala, MOORE'S LAW MEETS ITS MATCH, IEEE Spectrum, p. 44, June 2006.

IC Packaging: More-than-Moore

14

DSL CO Linecards

1996 1st Gen Single Channel

1998 2nd Gen Dual Ch

1999 3rd Gen Dual Ch

2000 4th Gen Quad Ch

2001 5th Gen Octal Ch

2002 6th Gen Octal Ch

IC Packaging: SOC – Saving Space

15

AR5

BOM

Manufacturing Process Technology

2000 5 chips 740 discretes

u CMOS u Analog u Flash u SDRAM

2005 – AR5 3 chips 415 discretes

u CMOS u Analog u Flash u SDRAM

1 chip <50 discretes

u CMOS u Analog u Flash u SDRAM

Memory

Comms Processor

Digital PHY

Analog Codec

Line Driver

Line Receiver

740 Discretes

Memory

Comms Processor

Digital PHY

415 Discretes

AFE

Memory

<50 Discretes

Single-Chip DSL Modem

IC Packaging: SOC Integration

16

IC Packaging: 3D SoP

[1] R. R. Tummala, MOORE'S LAW MEETS ITS MATCH, IEEE Spectrum, p. 44, June 2006.

17

IC Packaging: Mobile Requirements

18

• Decreasing Thickness

• Decreasing Weight

• Increasing Functionality

• Increasing Complexity

• Increasing I/O ports

1971 – First Microprocessor 4004

2.3x103 transistors, 108Khz, 10μm, pMOS, 12V, 0.3W, 4 Bits, 16DIP

2006 – Dual-Core Intel Itanium “Montecito”

1.7x109 transistors, 2GHz, 65nm, CMOS, 1.2V, 130W, 64 Bits, 775 Flipchip MCM

IC Packaging: MCM Evolution

19

IC Packaging: 3D Packaging

• Achieves Packaging Efficiency greater than 1.0

20 J.U. Knickerbocker et al., ECTC2012, pg.1068 (2012)

5 years Goal: Chip Embedding

Technologies Multi Chip Module (MCM) Flip Chip Through Silicon Vias (TSV)

Conclusions

• Packaging integration – RFID IC – Antenna – Energy Harvesting – Battery – Sensors

• Flexible substrate – Organic Electronics

Antonio L. Pacheco Rotondaro Head IC Packaging Division

antonio.rotondaro@cti.gov.br Tel.: +55 19 3746-6195 - Fax: +55 19 3746-6028

www.cti.gov.br