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1, RISC vs CISC

RISC CISCShorten execution time by reducing theclock cycles per instruction

Shorten execution time by reducing thenumber of instruction per program

Simple instructions, few in number Many complex instructionsFixed length instructions Variable length instructionsComplexity in compiler Complexity in microcodeOnly LOA!S"O#$ instructions accessmemory

Many instructions can access memory

Few addressing modes Many addressing modes$C Alpha, AM %&', A#C, A#M, AtmelAV#, (lac')n, *ntel i+-, M*.S, Motorola++---, .A/#*SC, .ower.C, Super0,S.A#C, *pad, Android1

System 2-, 3!Architecture, .. 44, VA5,Motorola +', x+

$xample6

#*SC6 mo7 ax, - mo7 bx, 4- mo7 cx, 8begin add ax, bx loop begin

C*SC6mo7 ax, 4-mo7 bx, 8mul bx, ax

"he total cloc' cycles for C*SC 7ersion might be6

9% mo7s x 4 cycle: ; 94 mul x 2- cycles:

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">p l?nh A#M 9c@ li 7E hi?u sut:/ ng_i l>p trnh c@ thX sI dJng 4 general/purpose register t

#-/#48, _c chia thNnh 2 nh@m6 Ynban'ed #egister 9#-/#:,(an'ed #egister 9#+/#4:, .rogram Counter 9#48:

">p l?nh "humb 9c@ li 7E m>t G mH:

/ "0YM( State #egister Set lN t>p con c]a A#M State Set1 g_il>p trnh c@ thX truy c>p Wn + general/purpose register 9#-/#:,.rogram Counter 9.C:, stac' pointer register 9S.:, lin' register9L#: 7N C.S# trong "0YM( State1

/ ">p l?nh Thumb-2lN s pha trGn gi\a t>p l?nh 4 7N 2% bit, Rt_c hi?u sut c]a cUc l?nh A#M 2% bit, Kng thi ph hp 7im>t G mH cng nh_ t_Dng thch ng_c 7i t>p l?nh gc "humb4 bit1

">p l?nh "0YM( cho giU trP 'Wt Tu thp hDn t>p l?nh A#M nh_ng mNcUc 'Wt Tu nNy chiWm mGt tj l? ln hDn1

">p l?nh "0YM( tiWt 'i?m _c 'h^ng gian nh 2-k 7N chRy nhanhhDn -k so 7i t>p l?nh A#M1

">p l?nh "0YM( 'h^ng c@ iEu 'i?n thc thi tr` cUc l?nh rQ nhUnh1

#, $i%n trc 'on(neumann & arvar)

'on(*eumann arvar)(ao gKm ALY, Memory9#AM:, Von eumannControl Ynit, *nput and Output de7ices1

ng trong S.

(G nh d\ li?u 7N bG nh ch_Dng trnh chung .hn bi?t r rNng bG nh d\ li?u 7N bG nhch_Dng trnh1C@ nh\ng _ng truyEn 9bus: ring X truyc>p 7No bG nh d\ li?u 7N bG nh ch_Dngtrnh1

Zh^ng thX 7`a c mGt l?nh, 7`a truy c>p d\li?u t` bG nh cng lc

C@ thX 7`a c mGt l?nh, 7`a truy c>p d\li?u t` bG nh cng lc

"hiWt 'W nNy c]a Von eumann H gii hRntc G thc thi c]a ch_Dng trnh do tRi mqithi iXm ch thc thi _c mGt l?nh1

"c G nhanh

.h hp 7i cUc thiWt 'W tun t .hn cng phc tRp, chi ph cao

h\ng nm gn y, tc G C.Y tng ln rt nhiEu ln so 7i tc G truy c>p 7No bGnh chnh1 g_i ta cn Tuan tm Wn 7i?c gim s ln truy c>p 7No bG nh X mbo tc G hoRt Gng c]a C.Y1 Wu, trong cng mGt lc, mqi l?nh c]a C.Y cn phitruy c>p 7No bG nh 4 ln, 7>y th 7i?c tng tc G C.Y chvng cn ngha g n\a,bi 7 n@ lu^n lu^n bP gii hRn bi 7i?c truy c>p 7No bG nh1

(G nh c@ thX _c thiWt 'W X c@ tc G truy c>p cao, nh_ng n@ Kng ngha 7i 7i?cgiU sn xut sQ cao1 zii phUp lN cung cp mGt dung l_ng nh{ bG nh ?m, 7i tc

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0ardware Layer9reTuired:

4 System Software Layer 9OS, de7ice dri7er:% Application Software Layer2

G truy c>p rt cao, 7N chng ta gi @ lN cache 9bG nh ?m:1 Zhi bG nh C.Y cnt_Dng tUc ang n|m trong cache, 7 7i?c t_Dng tUc 7No @ tn t thi gian hDn rtnhiEu ln so 7i 'hi cache phi thay [i 7N ly d\ li?u t` bG nh chnh _a 7No1 Vi?ciEu chnh cache lN mGt 7n E Tuan trng trong 7i?c thiWt 'W mUy tnh1

h\ng thiWt 'W chip C.Y tc G cao ngNy nNy th_ng 'Wt hp hai 'iWn trc 0ar7ard7N 7on eumann1 (G nh cache trn chip _c phn thNnh cache ch_Dng trnh 7Ncache d\ li?u1 ZiWn trc 0ar7ard _c dng 'hi C.Y truy c>p 7No cache1 "uy nhin,trong tr_ng hp 'h^ng c@ cache, d\ li?u _c ly t` bG nh chnh, mN bG nh chnh'h^ng _c chia thNnh 7ng nh ch_Dng trnh 7N 7ng nh d\ li?u1 h_ 7>y, 'iWntrc 7on eumann _c dng tm 7c truy c>p bG nh chnh1

+, C b-n v. c/u k0 ln/ v 345ng )6n ln/

zing cu 4-

7, 8i9i t/iu c/ung v. t/:ng n/ng

LN mGt h? thng chuyn dJng, th_ng c@ 'h nng t hNnh 7N _c thiWt 'W tchhp 7No 4 h? thng ln hDn X thc hi?n mGt chc nng ring bi?t nNo @1

ZiWn trc t[ng thX c]a mGt 0"6

;, Cn/ T* & ?@c 3im T*

}c iXm c]a 0"6

a1 #eliablei1 #eliability6 h? thng 'h^ng gp s cii1 Maintainability6 xUc sut mN mGt h? thng ang bP s c c@ thX

sIa _c trong mGt 'hong thi gian nht Pnh1iii1 A7ailability6 xUc sut mN h? thng tnh trRng s~n sNng phJc 7J1i71 Safety6 mG th? thng bP s c sQ 'h^ng gy thi?t hRi171 Security6 d\ li?u m>t 'h^ng bP lG 7N cUc lin lRc Eu c@ cUc

chng thc _c m bo1b1 "nh hi?u Tu

i1 $nergy ecientii1 Code/si3e ecientiii1 #un/time ecienti71 =eight ecient71 Cost ecient

c1 CUc h? thng nhng ch dNnh cho 4 ng dJng nht Pnh1

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d1 CUc h? thng nhng c@ 4 giao di?n nht Pnhe1 0ydrid systemf1 hiEu h? thng nhng phi th{a mHn nh\ng rNng buGc thi gian thc

9real/time constraint:1g1 "h^ng th_ng 4h? thng nhng th_ng 'Wt ni 7i m^i tr_ng 7>t l

bn ngoNi th^ng Tua cUc cm biWn,bG thc thi1h1 "h^ng th_ng, cUch? thng nhngcng lN cUc h? phn ng 9reacti7e

system:1

B, *g=n ng v m= />n/ k/p trnh nh_ 9C, C;;, a7a:

hiEu ng^n ng\ 'hUc nhau c@ thX capture 4 m^ hnh1 Vd6 seTuential programmodel / C, C;;, a7a

MGt ng^n ng\ c@ thX capture nhiEu m^ hnh1 Vd6 C;; / seTuential programmodel, obect/oriented model, state machine model

E, F/Gn bit HSM Moore & Mealy

Moore6 "he FSM uses only entry actions, i1e1, output depends only on the state1 "head7antage of the Moore model is a simpli)cation of the beha7ior1

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Mealy6 "he FSM uses only input actions, i1e1, output depends on input and state1 "heuse of a Mealy FSM leads often to a reduction of the number of states1

, F/Gn bit c

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Katapat/ QperationsLgKm 2 b_c

; Load6 c giU trP t` memory ghi 7No#egister

; ALY6 ALY xI l 7N tr ra 'Wt Tu 7No

#egister

; Store6 zhi lRi 'Wt Tu sau php tnh VNomemory

Instruction CycleL4 chu ' l?nh _cxI l sau 8 b_c

(4/Fetch6 }c instruction tiWp theo 7Nothanh ghi *#

(%/ecode6 5Uc Pnh ngha c]ainstruction

(2/Fetch operands6 }c d\ li?u t`memory ghi 7No datapath register

(/$xecute6 ALY xI l 7N tr 'Wt Tu raregister

(8/Store results6 =rite data result fromregister to memory

11, C

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ZhUi ni?m6 Slide "un 2 9'h@ hiXu 7Hi ch_ng:1 "hu>n li6

- LoRi b{ hu hWt nhiu1- "hay [i mc i?n thW mN 'h^ng c@ nh h_ng1- zim _c s Tuan trng c]a nh\ng dy t1-

"c G nhanh hDn1 (t li6- u cu i?n thW m1- "ng s l_ng dy 7N s 'Wt ni1

ng dJng6- "n hi?u audio cht l_ng cao1- YS(, *S1- $thernet1

%1%1 Mc hNnh 7i thi gian thc 9#eal time beha7ior: CSMA!C 9carrier sense multiple access! collision detection: 'h^ng

c@ thi gian Up ng m bo1

h\ng s thay [i6o "o'en rings, to'en buseso CSMA!CA 9carrier sense multiple access! collision a7oidance:1

%121 Fault tolerance6 .hUt hi?n 7N sIa ch\a lqi c]a nh\ng giao thc (us1%11 .ri7acy6 MH h@a, nh\ng mRng ring o

12, Memory, c

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.#OM 'h^ng Mt ln, cn thitbchuyn dng

9electrical signal:

Zh^ng x@a _c hanh Va phi

1#, C

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T/5i gianYuZt /in ai [arrival time\'hon thi gian t` lc s 'i?n xy ra Wn lcnhi?m 7J t_Dng ng _c 'ch hoRt1T/5i 3im b]t 3Vu t/^c t/i [release) time\ thi iXm sm nht tas' c@thX s~n sNng bt u1T/5i 3im b]t 3Vu t/^c /in [starting time\thi iXm mN tRi @ tas' btu thc hi?n1T/5i gian t_n/ to

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Roun) Robin [RR\L"as' lun phin thc hi?n trong mGt 'hon thi giannht1

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