HPPS 2007 Projects Presentation
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Transcript of HPPS 2007 Projects Presentation
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POLITECNICO DI MILANO
High Performance Processors and
Systems PdM – UIC joint master 2007PdM – UIC joint master 2007
Instructor: Prof. Donatella SciutoInstructor: Prof. Donatella Sciuto
HPPS @ PdM – March 2007HPPS @ PdM – March 2007
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OutlineOutline
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
DDynamicynamic Re Reconfigurabilityconfigurability AAppliedpplied toto M Multi-FPGAulti-FPGA
SSystemsystems
DReAMS
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DReAMSDReAMS
Dynamic ReconfigurabilityApplied to Multi-
FPGA SystemsBranch of DRESD projectInherits architectures and tools
Automatic workflow from VHDL system description to FPGA implementation
VHDL parsing and system simulationSystem creation over a specific architectureBitstream creation and download onto FPGAs
DReAMS
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Multi-FPGA Theoretical and Multi-FPGA Theoretical and Simulation Model Simulation Model 1/21/2
Project’s goals:Produce a multi-FPGA theoretical model
Architecture-independentMust capture all relevant features
Model Validation using several benchmarks
Definition/Identification of the set of benchmarksDO
VHDL description analysisPartitioningWriting a SystemC/VHDL modelSimulation
WHILE(No more improvement)
DReAMS
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Multi-FPGA Theoretical and Multi-FPGA Theoretical and Simulation Model Simulation Model 2/22/2
Project schedulingDetect relevant parameters of Multi-FPGA systemsAnalyze objective (cost) functions and architecture constraints
DimensionConnections bandwidthPower consumption…
Create a valid theoretical modelBenchmarks identification/definition Iterating process (analysis + partitioning + simulation)System implementation on Spartan-3 Multi-FPGA architecture
DReAMS
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Architecture DefinitionArchitecture Definition 1/31/3
Three Layers:Overall Multi-FPGA System
Net Topology Definition: mesh, ring, …
Single FPGADivision between fix and reconfigurable partsIP-Core selectionInternal Communication Infrastructure
Communication InfrastructurePhysical connections among FPGAsCommunication protocol
Development Environment: Digilent Spartan-3 boards
Final goal: distribuited dynamic reconfigurability
DReAMS
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Architecture Definition Architecture Definition 2/32/3DReA
MS
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Architecture DefinitionArchitecture Definition 3/33/3
Project ScheduleStudy how to use Digilent Spartan-3 boardsStudy its external interfaces and find a way to connect two or more boards togetherDesign the architecture of a single FPGA including the correct communication infrastructureDevelop the communication protocolConnect two boards togetherDevelop a simple distribuited application to test the validity of the proposed approach
DReAMS
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
REREconfigurableconfigurable CCommunicationommunication
IInfrastructurenfrastructure F Foror EEmbedded-systemsmbedded-systems
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Project's objectivesProject's objectives
Communication infrastructure explorationTechnologies and paradigmsState of the art
Advantages and pitfallsComparison
Communication infrastructure for reconfigurable systems
CI requirements tailored for reconfigurable systems
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Schedule – Project OrganizationSchedule – Project Organization
Literature analysis
Reconfigurable devices and systems
Contextualization
Communication needs
Communication infrastructure state of the art
Paradigms
– analysis
– (potential) improvements
Communication infrastructure for
reconfigurable systems
Implementation
Subject to the De Micheli VHDL description
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
RReconfigurationeconfiguration O Orientedriented MeMetricstrics
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Motivations and GoalsMotivations and Goals
RationaleRequirements-driven Reconfigurable SoC Communication Infrastructure design
e.g. QoS w.r.t. Load Balancing
ObjectivesDefinition and Validation of a set of Metrics tailored to identification and definition of the more effective Communication Infrastructure for Multi Processing Elements SoC architectureValidation framework definition
Simulator implementation
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Schedule - Project Schedule - Project OrganizationOrganization
Study and analysis of well-known metricsTCP/IP ProtocolsSystems migration between different Tier
Evaluation of different configurations of communication infrastructures
Topology (bus, point-to-point, cross-bar, NoC, …)Communication (connection-less, package-switching, circuit-switching, …)
Definition of metrics considering:Reconfigurable SystemDynamic changing of communication infrastructure elementsQuality of Service
Definition of a light framework Metrics Validation
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
PProcessingrocessing E Elementslements REREconfigurationconfiguration I Inn
RReconfigurableeconfigurable A Architecturesrchitectures
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Project EnvironmentProject Environment
Multi Processing Elements SoC ArchitectureSupport Dynamic Partial ReconfigurabilityDeployable on FPGAs
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GoalsGoals
Implement and test a single Processing ElementBased on Harvard ArchitectureSoftcore Processor: MicroBlazeIt can be dynamically reconfigured on the device
Main ProblemsOn chip memory (BRAM) inizialization: current softwares (provided by FPGA’s vendors) support only total configuration bitstreams
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Schedule - Project Schedule - Project OrganizationOrganization
Bitstream’s structure analysisCheck differences between total configuration bitstreams and partial bitstreamsFind position of embedded memory information within the bitstream
Write bitstream memory initializator
Perform tests on physical devices
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
![Page 25: HPPS 2007 Projects Presentation](https://reader038.fdocuments.us/reader038/viewer/2022110308/557c2088d8b42a65268b4d7a/html5/thumbnails/25.jpg)
POLITECNICO DI MILANO
Development of an OS Development of an OS architecture-independent architecture-independent
layer for dynamic layer for dynamic reconfigurationreconfiguration
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Scenario and GoalsScenario and GoalsCurrent scenario
Operating system support for dynamic reconfigurable architectures:
Architecture specific (e.g. Caronte)
Processor specific (e.g. PowerPC)
Tied to a particular distribution (e.g. MontaVista Linux)
Project objective
Definition of a new intermediate layer for an operating system which is:
Able to support dynamic reconfiguration
Architecture independent
High-level Linux distro independent
Implementation and validation using different FPGAs
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Schedule – Project OrganizationSchedule – Project Organization
Feasibility study
Study of the existing operating systems developed on the dynamic reconfigurable architectures defined in the DRESD Project
Definition of the new layer
Application
Integration of the new layer in an existing framework
Integration of the new layer in a different distribution executed on a different architecture
Implementation using Xilinx FPGAs: vp7, vp20 and vp30
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
Effects of 2D Reconfiguration Effects of 2D Reconfiguration in a Reconfigurable Systemin a Reconfigurable System
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Effects of 2D ReconfigurationEffects of 2D Reconfiguration
New Generation of FPGAsVirtex-4 and Virtex-5Allow bi-dimensional reconfiguration
Improvements:Possibility for area and performance optimizations
Increased complexity:In fragmentation managementIn Placement In Communication infrastructure creationIn the Bitstream generation phase
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Project GoalsProject Goals
Project goals:Analyse effects of the new approachExamine possible remedies to the new problemsEvaluate those solutions in various scenario
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Schedule – Project Schedule – Project OrganizationOrganization
First Phase:General analysis of 2D reconfiguration
Second Phase:Detailed description of the new problems
Third Phase:Analysis of possible solutions to those problems
Fourth Phase:Evaluation of examined alternatives
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
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POLITECNICO DI MILANO
Relocation for 2D Relocation for 2D Reconfigurable SystemsReconfigurable Systems
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2D Relocation2D Relocation
Self dynamical run-time 2D reconfigurationVirtex-4 and Virtex-5Relocation
HW/SW solutions: advantages and disadvantagesBiRF
Project goals:Study of the new FPGA familiesAnalysis of the new bitstream structure
New version of BiRF (BiRF2)
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Schedule – Project Schedule – Project OrganizationOrganization
First Phase:Examine Xilinx documentation on Virtex-4 and 5
Second Phase:Generate Virtex-4 bitstreams to examine their structure
Third Phase:Implement the new version of BiRF
Fourth Phase:Validation of the results
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What’s nextWhat’s next
DReAMSMatteo MurgidaAlessandro Panella
CITiESSimone CorbettaAlessandro MeroniAlessio Montone
Operating SystemIvan Beretta
PolarisMassimo MorandiMarco Novati
HLRMarco Maggioni
![Page 38: HPPS 2007 Projects Presentation](https://reader038.fdocuments.us/reader038/viewer/2022110308/557c2088d8b42a65268b4d7a/html5/thumbnails/38.jpg)
POLITECNICO DI MILANO
HHighigh L Levelevel RReconfigurationeconfiguration
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GoalsGoals
General Join isomorphic reconfigurable partitioning theory with reconfigurable scheduling performed by Salomone and area occupancy metricEvaluate quality of the given schedule result and optimize architecture exploiting Provide a common interface to represent TDG and scheduling output
SpecificAutomatize benchmarks productionRe-implementing Salomone to adopt the new defined interface Provide a graphical representation for the schedules
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Salomone++ workflowSalomone++ workflow
From specification to optimized scheduling…
TreeStructure
Graph
Analysis
Isomorphic
Partitioning
Specification
Area Occupation
Metrics
Salomone
SchedulingAllocationPolicies
OptimizedSchedule
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Schedule optimizationSchedule optimization
Evaluates a scheduling for a target architecture…
Based on simply considerationEach SCoNo portion depends of
its biggest node
We must modify schedule if exceeds area limit
If possible, we can save area and time anticipating loading of small different nodes of same SCoNo
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Project organizationProject organization
First phase: Development of the workflow
Isomorph partitioningSalomoneArea occupation metrics + optimization
Benchmarks
Second phase:Definition of the scheduler interfacesRe-implementation of SalomoneGraphical representation
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QuestionsQuestions