HOW tO Build Your Own working 16-Bit · 2016. 12. 17. · 1 Introduction to Microprocessors ... The...

HOW tOBuild Your Ownworking 16-BitMicrocomputer

Other TAB books by the author;

No. 771

No. 861

No. 960

No. 1000

No. 1055

No. 1085

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Integrated Circuits GuidebookDisplay ElectronicsIC Function Locator

57 Practical Programs & Games in BASICThe BASIC Cookbook

24 Tested, Ready-to-Run GamePrograms in BASICPrograms in BASIC for Electronic Engineers, Technicians & Experimenters

HOW tOBuild Your Ownworking 16-BitMicrocomputerBy Ken Tracton

TAB BOOKSBLUE RIDGE SUMMIT, PA. 17214

FIRST EDITION

FIRST PRINTING—APRIL 1979

Copyright © 1979 by TAB BOOKS

Printed in the United States of America

Reproduction or publication of the content in any manner, without expresspermission ofthe publisher, is prohibited. Noliability isassumed with respectto the use of the information herein.

Library of Congress Cataloging in Publication Data

Tracton, Ken.How to build yourown working 16-bit microcomputer.

Includes index.1. Microcomputers—Design and construction—Amateurs'

manuals. I. Title.TK9969.T7 621.3819'5 78-10353

ISBN 0-8306-9813-2 pbk.

Cover photo courtesy of Electronic Technician/Dealer magazine.

Preface

Microprocessors, those tiny slices ofprocessing power, are rapidlygrowing more potent. The first microprocessor was suitable only forsimple controller operations (such as thecontrol unit ofamicrowaveoven). Its immediate successors had a greatly increased instructionset, butwere limited to4-bit data chunks. Thesechips remain withus, asthe processors in calculators. Within ayear, both 8-and 12-bitunitsreached the market, and the microcomputeras we knowit wasborn. Now, we are able to build 16-bitprocessors that can competeon equal terms with mini computers, both inspeed and incapability.

One such device, the 9900 CPU by Texas Instruments, iswidely considered to bethemostadvanced single-chip processoryetbuilt. This text describes how to design a working micro-computerwith the 9900 and its support family.

It begins with a minimum unit, usetul for machine language andcontrol functions, and progresses to an information processingsystem that can include time-sharing, a variety of languages, floppy-discs, disc-drives, cassette tapeunits, anda host ofdifferent terminals. En route, it discusses each type of interface required, howtouse it, andhow, on occasion, to circumvent its necessity.

Theappendices include 9900 instruction codes, pinouts of the9900 support chips asdescribed inthetext,and alisting oftheASCIIcode in near-universal use.

Iwould liketo thankMr. AlecGrynspan, whocompiled the vastamount of data required for this text and assisted me in manydifferent capacities. I must also give special thanks to Mr. DaveCampbell, representative of Texas Instruments for his cheerful andunderstanding help which made this book possible, and of courseTexas Instruments whocreated the 9900 family of micro-processordevices and peripherals, who graciously supplied the materials thatallowed me to evaluate the information.

Ken Tracton

Contents

1 Introduction to MicroprocessorsThe 12-Bit Microprocessor—The 16-Bit Machines—Why the9900?—What Is In This Book

The TMS9900 Processor Chip 15Data and Address Organization—Internal Organization—ContextSwitching—Interrupts—Input/Output Techniques—CRU Interfacing—Memory Bank Selection—External Instructions andStatus Display

3TMS9900 Family Support Chips 4°TMS9901 Programmable System Interface—TMS9902Architecture—TMS9903 Synchronous CommunicationController—TIM9904 Clock Generator

4 9900 System Design ..-••• 57Upgrading the Minimum System—What Have We Got Now?—The Maximum System?

5 Hints About Peripherals 73Disc Systems—Other Peripherals

Appendix 80

Index 95

2

9

Introduction to

Microprocessors

The first microprocessors were 4-bit types which handled data as4-bit nybbles. The earliest of this new breed of machines, the Intel4004, was a majorbreakthrough. It was quicklyfollowedby the Intel4040, and the National Semiconductor IMP-4.

The 4-bit microprocessors are, for the most part, consideredobsolete. The exceptions are the one-chip microcomputers, withstorage and interfaces, as well as control on a single chip. These areexcellent controllers and have been used in such devices as sewingmachines, CRT controllers, and TV games.

An example is the TMSlOOO-series microprocessor, made byTexas Instruments (TV), consisting of the TMS1000, TMS1100,TMS1200, and TMS1300 processors. These consist of one-chipmicroprocessors containing from 1024 to 2048 bytes of read onlymemory (ROM), a central processing unit (CPU), 32 to 64 bytes(addressed as 64 to 128 nybbles) of random access memory (RAM)for a scratch pad, and simple input/output (I/O) logic.

These chips are incredibly low in cost when one considers theirpower and versatility; with their various kin, they have completelychanged the electronics and controller fields.

Although the Intel 4004 set the world on its ear, the first 8-bitunits, of which the Intel 8008 is the most famous, turned it upsidedown.

The smallest minicomputer being taken seriously were 8-bit (1byte) processors, and suddenly there was a complete computer on achip.

In actuality these first 8-bit machines were bigger versions ofthe 4-bit types and meant to be used as controllers, not as comput-.ers. Their instruction set and interfacing requirements wereoriented towards process control. Even so, the hobbyists startedusing them for other purposes and quickly started up that class ofsystems called microcomputers.

Microcomputers are now used in such sophisticated devices as(a) pocket computers, more powerful than the early monsters in thecomputer industry; (b) desk-top computers, capable of serving such,diverse users as car dealers and small motels and hotels; (c) officecomputers, for the accountant and business man; (d) TV games, ofsuch sophistication that one of these units can play hundreds ofdifferentgames, controlled by the insertionofa smalltape cartridge,and (e) robots, capableof such far-ranging feats as controlling MarsandJupiterprobes to as mundanefeats as delivering the office mail.

The number of 8-bit machines has grown enormously, and isalwaysinflux, with newer modelsavailable almost daily. The following is a list of some of the better known 8-bit microprocessors;

• F8 by Fairchild• 3870 by Mostek• SC/MP by National Semiconductor• 8080 family by Intel• Z80 by Zilog• 6800 family by Motorola• 6500 family by MOS Technology• 2650 family by Signetics• COSMAC 1802 family by RCA

THE 12-BIT MICROPROCESSOR

This microprocessor is a lonely creature, standing by itself interms of the number of variations available. The IM-6100 from

Intersil duplicates the Digital EquipmentCorp. (DEC) PDP-8almostperfectly.

The PDP-8 has one enormous feature goingfor it that makesthe soft-ware-compatible IM-6100 very popularand tempting, thatis, the software of the PDP-8. It is this colossal amount of material

10

that almost compensates for the primitive instruction set capabilityof the IM-6100.

In languages alone it outstrips any other microprocessor (aswell as some much larger machines), having;

A) DIBOL DEC business languageB) ALGOL-60 the subroutine definition languageC) FORTRAN the most famous scientific languageD) SNOBOL string manipulation languageE) APL the mathematical languageF) LISP the artificial intelligence languageG)BASIC the most popular language of allH) FOCAL a supercalculator languageI) LIBRA time-sharing FOCALJ) MACRO a macro-assemblerfor machine language usersK)LINK-EDITOR for hooking everything togetherL) DOS for developing systemsM)TSS time-sharing system

If the PDP-8 or IM6100 has all this power, then why, you mayask, isn't this book written solely on the construction of thismachine? The main reason is that I feel that the TI TMS9900microprocessor is fresh ground for the microcomputer user, witheven more potential than the PDP-8.

Other reasons include the most advanced architecture of anytrue microprocessor is currently within the TMS9900; theTMS9900 has the greatest flexibility of any microprocessor yetdeveloped; the TMS9900 has thebestinstruction set ofany microprocessor, exceeding many minicomputers; and the software development pace for the TMS9900 is increasing exponentially.

While there are so-called microprocessors with power just asgreatas theTMS9900 (theDECLSI-11 includes floating point asanoption) they are eithernotas cost-effective or notas flexible (e.g.,the LSI-11 couldnever be used as economically to control a CRT orother smart devices). The LSI-11/2 now consists of separate CPU,memory, andinterface cards, but the CPUis notavailable as a chipor chip group without the card.

THE 16-BIT MACHINES

Just as the 8-bit microprocessors absorbed and expanded thelowendofthe minicomputer industry, the 16-bitversions are begin-

11

ning to make themselves felt in the main stomping grounds of theminicomputer field.

The 16-bit unit, unlike its cousin the 8-bit type, is not really amicroprocessor, but is in reality a minicomputer using large-scaleintegration (LSI) technology. The main 16-bit machines are;

9440 by FairchildMicroNOVA by Data GeneralCP1600 by General InstrumentsPace by National SemiconductorTMS9900 family by Texas InstrumentsMC2 by Hewlett-PackardLSI-11 by DEC

The Fairchild 9440is an exact duplicate, in terms ofinstructionset, of the Data General NOVA, while the Data General microNOVAis an extended version of the same machine, with built-in stack andhardware multiplyand divide.

The DEC LSI-11 is an LSI version of their PDP-11 minicomputers.

The NOVA was designed as a 16-bit version of the 12-bitPDP-8withadded capabilities that eliminatedsome of the limitationsinherent in the PDP-8. This does not mean that the instructions

were simply expanded, but that the concept was expanded.From this we can see that the IM6100, the 9440, the mic

roNOVA, and the LSI-11 are all minicomputers in the guise ofmicroprocessors.

Although the other 16-bitmachines may have much to recommend them, they are not felt by myself to be as desirable.

Thisbook isorientedtowards the personwishing to constructamachine and not simply buy a completed unit. For instance,Hewlett-Packard MC2 isused byHewlett-Packard andis not, at thistime, available to anyone else.

The LSI-11 is a multichip system, already designed, andis notavailable as a separate chip set. This makes sense if we rememberthat it is meant to duplicate a PDP-11 as a whole and variations woulddefeat the original design purposes.

Although the 9440 and the microNOVA are available as separate chips and chip sets, they are meant to exactly duplicate theNOVA system by Data General.

12

WHY THE 9900?

The TI 9900 was chosen for this book for several reasons; it isan LSI minicomputer rather than a microcomputer chip (microprocessor) in the usual sense of the word. This means that, for the

hobbyist or professional, the instruction set and architecture aresimple and clean, with little to interfere with designing hardware orsoftware.

The minimum system (see Chapter 4 for a block diagram) is notsignificantly more expensive than a minimum system using otherprocessors, and may even be less expensive, particularly whencompared to other 16-bit processors.

The 9900 is a 16-bit machine with byte addressing and a generalregister bank (16 registers); it is a 64-pin chip with separate lines fordata and addresses, making complex interfaces unnecessary; and itdoes not require the use of complex memory systems to operate,allowing easy mixing of different memories.

The family of 9900 chips is complete, allowing powerful systems to be designed with ease. There exists currently a version ofthe TMS9900, called the TMS9980, which can use 8-bit modules andis totally software compatible with the 9900.

The 9900, while stillyoung in terms of software, has most of thekey software already available, such as:

1) COBAL-full ANSI COBOL compiler2) FORTRAN—a re-entrant, full ANSI/ISO compiler3) A real-time multiprogramming, time-sharing operating

system with all the bells and whistles.4) BASIC—A time-sharing BASIC

The 9900 is available as a one-card computer called the 990/4,as a one-card computer with on-board RAM and ROM called the990-100M, a TTL version with memory mapping to two-millionbytes, called the 990/10. There also exists an PL version, withhigher speed and pin compatibility termed the IBP-9900. There isthe 9980 (8-bit compatible) version of the 990-100M called the990-180M. And of course the TMS9900, TMS9980, and the

IBP9900 are allavailableas separate chips, along with the rest of thefamily chips.

AllinallI feel that the TMS9900 (or the IBP9900), as a personalcomputer, is an excellent choice.

13

WHAT IS IN THIS BOOK

The 9900 chipitself is obviouslycovered in detail, since this isthe central processing unit, the very nucleus of the computer system.

The 9901is a programmable systems interface, whichprovidesthe 9900with anintervaltimer, anevent timer, up to 16 I/O ports,and up to 15 interrupt input lines.

The 9902is anasynchronous communication controller(ACC),whichallows interfacing the 9900 to such devices as teletypewritersof all kinds, CRT terminals, hard-copy terminals, papertape readers, and punches and cassette tape interfaces.

The 9904 is a clock generator which generates all the synchronization signals for the 9900, the 9901, etc.

The 9903 is a synchronous communication controller whicheliminates the need for software for the protocols, such as binarysynchronous (often called bi-synch), synchronous data link control(usually SDLC), and almost all other synchronous protocols, withthe linksynchronization andcontrol handled by this chip, the 9903.

14

The TMS9900

Processor Chip

The TMS9900 is a single IC in a 64-pin dual inline package. Thispackage (Fig.2-1)is larger than the more familiar 8-bitmicroprocessor chips. The 9900is 3.2 incheslong, and the two rows ofpinsare0.900 inch apart rather than the 0.600 inch spacing used in 40-pinpackages. Adjacent pinspacing is the familiar 0.010inch. Pinnumber1 is identified by an index dot between Pins 1 and 2.

The chip is produced by N-channel silicon-gate MOS technology, and requires three power supplies for its operation. The recommended levels for these supplies are -5, +5, and +12 VDC.Under typical conditions, the chip draws 50 ma from the +5 VDCsupply 75ma is ratedmaximum), 100 microamps from the - 5VDCrail 1 ma maximum), and 25 ma from the +12 VDC source (45 mamaximum).

All signal levels (exceptfor the four clock signals), both inputandoutput, are compatible with TTL logic. The clocksignalsmustnot be lower than +3 Vat their positive points, and TTL guaranteesonly a +2.4-volt levelfora HIsignal. If the recommended TIM9904clock chip is used to provide the clock signals you will have noproblem; TTL normally provides adequate drive, but this is notguaranteed.

Maximum clock frequency is 3 MHz, and four non-overlappingphasesmust be supplied. The 9904circuituses a 48-MHzcrystal, ora 12-MHz external oscillator, to provide these requirements. Fig.

15

r:HKHHiMJHHwm?yyft^^

*^^HHHHHHHH}tfiH}O^LH}g^{HHHHHHH>WM

JJOO- 0030-

.125.

NOTE: A Each pin centerline Islocated within 0.010 of itstrue longitudinal position.

Fig. 2-1. The64-pin dual inline package oftheTMS9900 islarger than themorefamiliar 40-pin DIP configuration used by8-bit microprocessors. Added 24 pinsmake possible more system interconnections. (Courtesy ofTexas Instruments)

2-2 shows clock signal timing requirements. The times shown arefor maximum-frequency operation. For operation at slower speeds,the duration ofindividual phases may be extended but the 5-ns guardtimes between signals should remain unchanged.

Input lines totheTMS9900 all have high impedance tominimizeloading on signal sources. Outputs are all capable of driving two

I

15 nsJi

d>2

i

U 83 ns JH

t/i-48 nsnA !'! l\ .

I 1bns-H r— '

L i ' i J—1i i i i /

i1^ \<A3

5ns*l r*-

/ \M

1/ \A0001163

Fig. 2-2. Clock waveforms required by TMS9900 when operating at maximum3-MHz frequency are shown here. Dead space of 5 ns between phases isessential to proper operation of processor. (Courtesy of Texas Instruments)

16

standard TTL inputs each, and no pull-up resistors are necessary.Most standard memory devices can be connected directly to the9900withoutinterveningbuffers. Ifan external circuitimposes morethantheequivalent oftwoTTLloads (thatis, requires morethan3.2ma of driving signal), buffering is required.

VBB 1

vcc 2

WAIT 3

LOAD 4

HOLDA 5

RESET 6

IAQ 7

01 8

02 9

A14 10

A13 11

A12 12

A11 13

A10 14

A9 15

A8 16

A7 17

A6 18

AS 19

A4 20

A3 21

A2 22

A1 23

AO 24

04 25

vss 26

VDD 27

03 28

DBIN 29

CRUOUT 30

CRUIN 31

INTREQ 32

TMS 9900 PIN ASSIGNMENTS

64 HOLD

63 MEMEN

62 READY

61 We

60 CRUCLK

59 vcc58 NC

57 NC

56 D15

55 D14

54 D13

S3 D12

52 D11

51 D10

50 D9

49 D8

48 D7

47 D6

46 D5

45 D4

44 D3

43 D2

42 D1

41 DO

40 Vss39 NC

38 NC

37 NC

36 ICO

135 IC1

134 IC2

133 IC3

Fig. 2-3. Pin connections for processor chip are grouped byfunction to simplifyPWA card layout. (Courtesy of Texas Instruments)

17

Pin assignments of the TMS9900 (Fig. 2-3) were made tosimplify thelayout ofacircuit board, bygrouping related signals intosets andassigning each set to adjacent pins. Thus all signals of thedatabusare together, andso forth. Thispermitsshorter conductorruns and more compact circuit board layout.

Payclose attention to these critical points in layout:The clock inputs must be located as close as possible to the

clock driver circuit, because these signals have fast rise and falltimes while driving relatively high capacitance through a wide voltage swing.

The 12-volt supply to the clock drivers should be decoupledwith both large (15-uf minimum) and small (0.05-uf maximum)capacitors in order to remove both low-frequency and high-frequency transients from the supply lines.

All power inputs must be decoupled as close to the chip aspossible. The+5 VDC power drain can vary bynearly 100 maovera20-ns interval, ifall data and address lines simultaneously switch tolow level, and theresulting spike can interfere with system operation unless decoupled at the 9900 socket.

DATAAND ADDRESS ORGANIZATION

The TMS9900 uses a 16-bitmemoryword and 16-bitaddresses. The 16bitsofthe memoryword(Fig.2-4)are referred to as DOthrough D15, with DO being the most significant (leftmost) bit andD15being the least significant. Similarly, the 16 bits of an addressarereferred toasA0 through A15, with A0 being mostsignificant.

Each memory word canbe considered as being made upoftwo8-bit bytes. In this case, DO through D7 form one byte, and D8through D15 form theother.Mostdataoperations canbeperformedoneitherwords or bytes, depending upon a flag bit in the operationcommand code.

The 16-bit memory addresses actually refer to bytes ratherthan to words. Only 15 of the 16 address bits are brought out toexternal addresslines; A15 isusedonly inside thechip, tosignify toabyte operationwhichof the two bytes is to be affected. WhenA15is0, the bytecomposed ofDO throughD7isaddressed; whenA15is 1,the affected byte is D8 through D15.

Since only 15address bitsare available externally, all memoryaddresses involve full 16-bit words, and are on even-byte boundaries. That is, memory location 0001 does not exist; the system

18

MSB LSB

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

3E

vffi.

VMEMORY WORD (EVEN ADDRESS)

LSB MSB

6 8 10 11 12

v—EVEN BYTE

JL—V/ODD BYTE

LSB

13 14 15

Rg. 2-4. Bit designations which memory word are asshown at top here. Bytes ofword are as shown below. (Courtesy of Texas Instruments)

steps from 0000 to 0002, then to 0004, and so forth. Thus thememory space directly addressible is 32,768 words, and any memory transfer moves a full 16-bit word regardless of whether one orboth its bytes are to be modified.

INTERNAL ORGANIZATION

The advanced memory-to-memory architecture of theTMS9900isbestdescribed bycomparing itto themoreconventionalregister-oriented design exemplified by the popular 8080 microprocessor. Such a chip (Fig. 2-5) contains a number of registers, aprogram counter, an arithmetic and logic unit (ALU), and a set ofstatus flags. Data may be transferred from register to register, orbetween register and memory. Most arithmetic and logic operationsinvolve aspecial register (the accumulator) and either another register, immediate data, or a memory byte.

For controller applications, this is adequate. The controlparameters may be kept in the internal registers, and little communication with memory is required for data transfer.

However, when interrupt-driven input-output techniques areemployed (which means most ofthe time, in information processingapplications), all oftheinternal registers must besaved each time aninterrupt occurs. Subsequently, at the end ofthe interrupt serviceroutine, the registers must be restored. This continual saving andrestoration oftheregistersmay occupy as much processor time andprogram space as the interrupt service routine itself.

19

C

CPU

REGISTERS

PC

ALU

Ia

FLAGS

PROGRAM AND DATAREGISTERS IN CPUPACKAGE

CPU

PC

WP

ALU ISTATUS

ti

TMS8080A

MEMORY

PROGRAMDATA

MEMORY

REGISTERSPROGRAM

DATA

TMS9900

oKl9Q5ftM AND dataREGISTERS IN MEMORY • PROVIDES FAST CONTEXT SWITCHING

NUMBER OF WORKSPACE REGISTERSLIMITED ONLY BY MEMORY SIZE

Fig. 2-5. Difference between TMS9900 organization (right) and more conventional approach of8080 (left) iskeyto9900's capability for rapid context switching. (Courtesy of Texas Instruments)

20

TheTMS9900's memory-to-memory design differs inthatonlythree registers are actually contained within the chip, and all three ofthese are automatically saved or restored as required by singleprogram instructions or interrupt responses. Thesaving or restoringis called a "context switch."

The three actual registers in the TMS9900 (Fig. 2-5) are theprogram counter, the status register, and theworkspace pointer.Thefirst twoofthese correspond to their counterparts in the moreconventional design; the third is the key to the advantages of theTMS9900.

Inaddition to the three actualregisters, the TMS9900 employs16additional "workspace registers." These registers, identified asWRO through WR15, may beused for the same purposes asany ofthe additional data registers of the more conventional architecture(with several exceptions). That is, any oftheregisters may beusedas an accumulator or as an address pointer.

The 16 workspace registers (Fig. 2-6) may be located anywhere in memory, and you can have as many sets of themas youlike. Theonly requirements arethatthe 16registerwords inonesetbe in consecutively addressed locations, and that they not be inread-only memory.

The workspace pointer register points to WRO inthecurrentlyactive set ofworkspace registers; thisgivesthe processor accesstoall 16 of the registers in the set.

MEMORY

AOORESS

KP.00

HP* 02

MP.04

WP.OS

WP«OS

WP»0A

W?«OC

*P»0E

HP* 10

WP* 12

HP* 14

WP«tS

IMP. IS

VHP. 1A

HP« 1C

HP. IE

REGISTER

- OPTIONAL SHIFT

COUNT

- BL RETURN AOORESS

- CRU BASE AOORESS

- SAVED HP

- SAVEO PC

- SAVED ST

1 REGISTER USE I

| WORKSPACE POINTER | Q 0

1

2

2

4

5

S

7 0ATA IKL8

9 ADDRESSES

10

11

12

11

14

IS

Fig. 2-6. The16registers ofthe9900 are organized as shown here. All addresses arerelative to the workspace pointer. As manysets of registers as desiredcan be defined. (Courtesy of Texas Instruments)

21

Ofthe 16 workspace registers, 10 are available for any application. Three are dedicated to thecontext-switching operations, buttheir content maybeusedorchanged bythesame commands whichapply to the 10 general-usage registers. The reinaining three havespecial uses in certain commands, butagain can bechanged orusedlike any other workspace register (with one exception).

Registers WR1 through WR10 are thegeneral-usage registers.Each can beused as an accumulator, amemory pointer, oran indexregister, depending upon specific bits in the command used toaddress the register.

The other registers can also beused as accumulators, memorypointers, and (except for WRO) as index registers. Indexing involving WRO is not allowed.

The registers dedicated to context switching are WR13,WR14, and WR15. When acontext switch occurs, theold content ofthe workspace pointer isstored in WR13 ofthe new workspace, theold program counterinWR14, and the currentcontentofthe statusregister in WR15. If these three registers are not modified bytheprogram, thecontext switch can bereversed byreloading WP, PC,and STfrom WR13, WR14, and WR15 respectively. This is done bya single command, Return Workspace (RTWP).

Special uses of the remaining registers are as follows: WROcontains an optional shift count used by all four shift instructions.WR11 contains the return address stored automatically by theBranch and Link (BL) command, which can be used to call a subroutine without performing a context switch. To return from thesubroutine aBranch usingWR11(B11) is executed. WR12containsthe bit base address for communication-register unit (CRU) operations.

In addition to the workspace-register feature, the memory-to-memory organization of the 9900 has another unusual result.Arithmetic and logical operations are not limited to actions involvingtheregisters; anymemorylocation can bealtered, without the needfor moving its content into a register to make the change, thenmoving it back after the change is complete. That is to say, anymemorylocation—not justtheworkspace registers—can beusedasanaccumulator, merely by addressing it appropriately in the command.

At first glance, it might appear that this architecture wouldresult in an inordinate number of memory accesses in order to

22

accomplish any program action. In fact, the number of accesses isnot significantly larger than with the more conventional register-oriented microprocessor designs, since they too must perform atleast one memory access per program instruction in order to fetchthe instruction for execution. By reducing the number of programsteps which must be accessed, the 9900's design permits more dataaccesses without penalty.

CONTEXT SWITCHING

The process of switching from one set of registers to another,by switching the pointer to the workspace, is known as contextswitching. Acontext switch is performed when the LOAD signalgoes low, immediately after the RESET signal returns to high levelafter being low, when any of the 15 maskable interrupts is recognized and allowed, whenever one of the 16 possible ExtendedOperation (XOP) commands is executed, whenever aBranch andLoad Workspace Pointer (BLWP) command is executed, or whenthe Return Workspace (RTWP) is executed.

All of these context switches, except that resulting fromexecuting RTWP, are performed in the same manner once thenecessity for the context switch is established. External signal linesLOAD and RESET establish the need for their context switches. Anallowable interrupt similarly establishes its need. Context switchesrequired by command execution are established by fetching anddecoding the command.

Once the need for a context switch is known, the existingworkspace pointer and status register are temporarily saved and anew workspace pointer value is obtained from an appropriate memory location. For all context switches except BLWP and RTWP, thelocationofthe new workspace pointervalue is built into the 9900 chip(Fig. 2-7). For LOAD the new value is at memory location FFFC(16). For RESET, itis at 0000. For Interrupt 1, itis at 0004, and soforth for the higher-numbered interrupts up to Interrupt 15, at003C(60 decimal, or 4times 15). The values for XOP immediately followthose for the interrupts, at memory locations 0040 (XOP 0) through007C (XOP 15). The value, once obtained, is loaded into the workspace pointer register, which instantly changes the entire programcontext to reflect the new workspace.

With the new workspace established, the saved value ofthestatus register is stored in new WR15. The content ofthe program

23

counterregister, which has notyetchanged, isstored innewWR14.The savedvalue ofthe old workspace pointer isstored in WR13, andfinally the new value of the program counter is read from thememory location immediately following that from which the newworkspace pointer was obtained (FFFE for LOAD, 0002 for RESET, and so forth). Program execution then continues, using thenew value of the program counter and the new workspace.

After any ofthese context switches isaccomplished, the firstinstruction (that addressed by the new program counter) will beexecuted before any interrupt will berecognized. This permits theinterrupt facility to be locked out when desired.

Because the old WP, PC, and ST are pushed into WR13,WR14, and WR15 ofthe new workspace, it is possible to restorethem and thus torestore theexact internal system conditions whichexisted at the instant the context switch was performed. This isfunctionally the equivalent of the stack push and pop (or pull) sequences employed by many 8-bit microprocessors. The 9900, however, does everything by asingle instruction, rather than requiringaninstruction sequence.

Restoring the previously used workspace, PC, and status isaccomplished by the RTWP instruction. Its action may also beconsidered a context switch, but in the reverse direction. TheRTWP action is never performed automatically; it always resultsfrom the program's fetching and decoding the RTWP command.

When the RTWP command isdecoded, the processor fetchesthe old status from WR15 and stores itin the status register. Next, itrestores the program counter from WR14. Then it restores theworkspace pointer from WR13. Note that the values ofST, PC, andWP which existed when the command was decoded have been lost;none ofthem are necessary any longer. Finally, the restored program countercontent isloaded ontothememoryaddress lines and thenext instruction is taken from the location thus addressed. Unlikethe other context switches, the interrupt facility remains activewhen RTWP is executed (unless disabled by the restored interruptmask in the status register).

INTERRUPTS

The TMS9900 provides 16 interrupts, together with LOADand RESET pins. Interrupt 0 and RESET accomplish the sameactions.

24

AREA DEFINITION

INTERRUPT VECTORS

XOP SOFTWARE TRAP VECTORS

GENERAL MEMORY FOR

PROGRAM. DATA. AND

WORKSPACE REGISTERS

LOAD SIGNAL VECTOR

MEMORY

A0ORESS16 MEMORY CONTENT

0 IS

<

<

<

's.

0000

0002

0004

0006

003C

003E

0040

0042

007C

007E

0080

FFFC

FFFE

WP LEVEL 0 INTERRUPT

*

PC LEVEL 0 INTERRUPT

WP LEVEL 1 INTERRUPT


<

WP LEVEL IS INTERRUPT


WP XOP0

PC XOPO

'

WP XOP 15

PC XOP 15

•

•

•

GENERAL MEMORY AREA

MAY BE ANY

COMBINATION OF

PROGRAM SPACE

OR WORKSPACE

•

•

{WP LOAD FUNCTION

PC LOAD FUNCTION

Fig. 2-7. Memory locations 0000 through 007E, plus FFFC and FFFE, arededicated to special uses as shown in this memory map. Allother addresses arefree for general use. (Courtesy of Tl)

Interrupt priority is established by the number of the interrupt.Interrupt 15 has lowest priority, and Interrupt 0 or RESET thehighest. Interrupt 0 cannot be masked; the remaining 15 are automaticallymasked in such a way that no interrupt of lower prioritywill be accepted while any interrupt is being serviced.

The interrupt system uses five lines. One, INTREQ, signalsthe TMS9900 that an interrupt is requested. This line is normally

25

high, and goes lowtosignal an interruptrequest Theotherfour, ICOthrough IC3, forma4-bitbinary codewhichindicates the levelof theinterrupt request ICO is the most significant, and IC3 the leastsignificant, bitof the code, and ahigh levelindicates a"1"bit Thus,LLLH onIC0-IC3 (in that seauence) indicates 0001, orInterrupt 1.

When aninterrupt requestis recognized on the INTREQ line,the TMS9900 compares the interrupt code on IC0-IC3 with theinterruptmask contained instatus-registerbits ST12 through ST15.Ifthe interrupt code is less than orequal to the mask (indicating ahigher or equal priority interrupt), the interrupt is allowed and acontextswitch isperformed afterthecurrentlyexecutinginstructionhas been completed. After thecontext switch, theinterrupt mask isautomatically reduced by one so thatno other interrupt of equal orlower priority can be allowed.

When the interrupt mask is equal to zero (bits ST12 throughST15 all zero), norequested interrupt can beofhigher priority, andonly theRESET interrupt can be equal. Thus all interrupts exceptInterrupt0(RESET) can bedisabled byforcing theinterruptmasktozero. One command, Load Interrupt Mask Immediate (LEVO), permitstheinterruptmasktobe set to anyvalue, and the first commandafter any context switch will be executed before interrupts will beexamined again. Thus by making the first command of a criticalroutine aLIM 0, thatroutine can turnoffinterrupt action. When theroutine is finished and control passes back to the interrupted actionvia the RTWP command, the previous interrupt mask is restoredalongwith theother 12 bitsofthestatus register, and interrupts areonce again enabled.

This approach tointerrupt control makes priority determinationalmost automatic. Each external circuit which can produce an interrupt request must also provide its interrupt code on lines ICOthrough IC3. If each device has a separate code, no additionalhardware is necessary to determine which device requires serviceor if response is permissible. Most systems can operate with nomorethan 15different interrupts. Should more prove necessary,several devices can be assigned the same code and the interruptserviceroutinecanthen interrogate all of them to determinewhichrequires service. Alternatively, external hardware can be addedtosortoutpriorities sothatthe 9900 sees only oneof 15requests, buteach request could have originated from any of several differentcircuits.

26

INPUT/OUTPUT TECHNIQUES

Any orall ofthree widely different techniques may beused forinput/output data transfers between theTMS9900 processor andmemory onone side, and theexternal world ontheother. Thethreetechniques (Fig. 2-8) are direct memory access (DMA), memory-mapped I/O, and the communications-register unit (CRU) capabili

ty-DMA provides direct transfer of data between the peripheral

devices and memory, without involving the processor at all (excepttoguarantee thatthe processor does not attempt to accessmemoryat the sametime). Withmany processors, this is the cleanestway totransfer data, but it always requires some external hardware tocontrol the DMA activity and to assure thatboth the processor andthe peripheral device wait their proper turns for memory access.Because of its complexity, DMA I/O is outside the scope of thisvolume.

Memory-mapped I/O assigns memory addresses tothevariousperipheral ports, and "reads" from or"writes" totheperipheral portjust as though itwere actual memory. This approach makes atleastone memory location per peripheral device unavailable for actualdata storage, but nevertheless isapopular technique. Several 8-bitmicroprocessors (notably, the 6500 and 6800 families) usememory-mapped I/O to meet all their requirements. Again,memory-mapped I/O is outside the scope of this volume, because

Aoonioem iz:

ii

=7udma m*

__nfMEMORY t I \. CONIROt JJ.

,/ 17

I/O

OMA COWTHOl

. COMMUKICAIKM* REGISTER UNII CRU

• memory iumD no• OIRECT MEMORY ACCEti DMA

Fig. 2-8. These three types of input/output techniques may be used with the9900. Only the CRU capability is unique to the 9900. (Courtesy of TexasInstruments)

27

the technique used depends entirely upon the specific peripheralinvolved.

The final technique, the CRU capability, is unique to theTMS9900 family and is an extension of the idea used for directaccumulator I/O in such processors as the 8080.

A communications registerunitis defined inthe 9900 system asanyexternalunitmakinguse of the processor's CRUcapability. Thiscapability takes the form of three dedicated I/O pins (CRUIN,CRUOUT, andCRUCLK), 12bits (A3 through A13)of the addressbus, and five processor instructions which permit the program toset, reset, or test any of 4096 addressable bits in the externaldevice, and to move data between memory and CRU data fields.

While the capability provides 12bitsof CRUaddress, making itpossible to uniquely address upto 4096bitsinthe CRU, anyspecificdevice used as a CRU need not have all these bits present. Asingle-bit device such asa flip-flop couldbe used asa CRU. In amorepractical vein, the TMS9901, 9902, and 9903 peripherals are allintended to be usedas CRU's. If youprefer, any type of peripheralcontroller canbe turnedintoaCRUby providing the properinterfaceto make it compatiblewith the 9900's CRU-oriented commands andbit addressing.

CRU INTERFACING

The CRU interface is a dedicated serial I/O capability whichpermits transfer of from 1 to 16 bits at a time. Since bits areindividually addressed, nomasking instructions are necessary inI/Oservice programs, and I/O fields need not be identicalin size to thememory word (but must be no longer than 16 bits).

CRU interface signals from the TMS9900 consist of (1) theCRU clock(CRUCLK, pin60)which, when high, means that the 15address linescontain eitheranexternally decoded operation (ifA0,Al, orA2 is high) orabitaddress inthe CRU(ifA0, Al, and A2 areall low); (2) CRUOUT (pin 30)which contains the bitbeing output;and (3) CRUIN (pin 31) which contains the bit beinginput.

The CRU can be considered to be a pair of addressablememories of 4096 bits each (one memory for input, and one foroutput). Five instructions access the CRU. They are:

• Test Bit (TB), which allows reading any single bit in theCRU;

28

• Set Bit to One (SBO) and• Set Bit to Zero (SBZ), which allow altering one bit in the

CRU; and• Load Communications Register (LDCR) and• Store Communications Register (STCR), which allow alter

ing orreading up to 16 bits ata time via amulti-bit CRU datatransfer.

Each of these five instructions first causes the address of asinglebit in the CRU address space tobeformed asshownin Fig. 2-9byadding a displacement value (contained in theinstruction) to theCRU baseaddress(containedinWR12), then placesthe resulting bitaddress on address lines A3throughA14 while forcing AO, Al, andA2 to 000. The bitappears on either CRUIN (forTB or STCR) orCRUOUT (for SBO, SBZ, or LDCR), strobed by CRUCLK.

The three single-bit commands operate explicitly; TB placesthe received bit value into ST2, where it may be tested by asubsequent JEQ or JNE command. If the bit value was 1, theEQUAL condition is set. SBO and SBZ set the CRU bitto 1 and 0,respectively.

Only one bit permachine cycle isprocessed by any oftheCRUcommands. Multi-bitcommands LDCR and STCR perform as manycycles asnecessary totransfer thespecified number ofbits, chang-

O 1 2 3 4 S 6 7 8 9 10 11 12 13 14 IS

X X X 1 1 1 X W12

DON'T CARE

+

WWBIT 8 SIGN

EXTENDED

B 9 10 11 12 13 14 IS

1 1 SIGNED

DISPLACEMENT•

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 0 0 1 1 1 ADDRESS BUS

_Jf

SET

FOH

OPE

TOZ

ALL

RATI

ERO

CRU

DNS

VEFFECTIVE CRU Bl TAD ORES.5

Fig. 2-9.The CRU address placedon the address bus (bottom) is developed byadding an8-bitsigneddisplacementcontainedinthe I/O command itself (center)to the CRU base address held in workspace register 12 (top). This operation )srepeated for each addressed bit. (Courtesy of Texas Instruments)

29

CRU

INPUT

BITS

N

N*1

N+14

N*15

INPUT (STCR)

0 1 EFFECTIVE MEMORY ADDRESS 14 IS

OUTPUT (LDCR)

N - BIT SPECIFIED BY CRU BASE REGISTER

CRU

OUTPUT

BITS

N

N+1

N+14

N+15

Fig. 2-10. Multi-bit CRU data transfers by the LDCR and STCR commandsoperateasshown here. Oninput (STCR), thebithaving the lowest CRU addressmoves Into therightmost bit oftheaddressed memory word. Onoutput (LDCR),similarly, therightmost bit goestothelowest CRU address. (Courtesy ofTexasInstruments)

ing the bit address after each cycle. Each bit is moved betweenprocessor and CRU as shownin Fig. 2-10.

The 16-bit CRU shown in Fig. 2-11 illustrates thebasic principles involved in CRU interfacing. Note that address lines AO throughAlO are ignored by this circuit; it will interpret any of the externalcommands asaCRU action, and each ofits 16 input and output bitshas 256 possible addresses. That is, input bit INO and output bitOUT0 can be addressed as CRU bit 0, bit 16, bit 32, and so forth upto bit4080. Whenever address lines All through A14 contain the0000 pattern, INO and OUT0 are addressed.

The TMS9901, 9902, and 9903 support chips (discussed indetail in Chapter 3) are designed for use with the CRUinterface.Each ofthem has only5address-line inputs, so each chip occupies 32bits ofthe4096-bit CRU memory space. Each ofthese chips also hasa ChipEnable (CE) inputto permit the other seven address lines toselect one of several chips in a system.

If only one CRU device is to be used, the multiple-addressapproach (simply grounding the CE line) would be enough. However, let us suppose that we wish to connect 8 devices on the CRU

30

interface. We can divide the CRU address signal as follows;

1) 9901 for interrupts and interval timer, addressesd asbits0-31

2) 9902 for master terminal, addresses 32-633) Four 9902s for remote terminals, modems, addresses

64-95

96-127

128-159

160-191

4) 9903 for a BI-SYNC terminal addresses 192-2235) 9903 for anSDLC terminal addresses 224-255

Thecircuit asshown inFig. 2-12 would beused. This circuit usesan74LS138 3-to-8 decoder. Line Z comes from the CRU clock.

Shouldwewish tofurther expand thesystem, wecould useFig.2-13 to increase the number of circuits to 64. This requires 974LS138 decoders. Figure 2-14 shows decoding foryoursystem upto128devices, allowing up to127 terminals tobe connected tosuchasystem. This circuit requires 36 74LS138 decoders and some TTLcircuitry.

SN74LS2S1AITIM9 TO

MUX

LSZ51A »-.

M06IB «-V1 C +->

,SN74LSS«A'ITIM8 TO

MUX

LSStA «-^.M06IB <-V1 5 f~L

0SN74LS290(TIM 99081OSSIT *LATCH B-

"nwiwoei0B-BIT ALATCH £r

JfrH/4>l»WU

<3

T MS 9900

cruclk cpu

-/ »

Rg 2-11 This 16-bit CRU can be constructed with only 5 IC chips, sinceone-quarterof a74LS00 can be used instead of the 74LS04. It may be adequatefor small systems. (Courtesy of Texas Instruments)

31

A7-

A8-

A9-

Z»-

/tT+5V«-

SN74LS138

G2A

G2B

G1

-TMS9901 CE

-9902 CE (MASTER)

>9902 CE

:} 9903 CE

Fig. 2-12. This 3-to-8 decoder canbe usedtoselectoneofeight CRU devices.

Should achip require theuse ofmore than 32bitsofthe CRU,Fig. 2-15 shows atechnique totie two select lines together. Bytyingtwolines togetherwe allow up to 64 CRUbits to be addressed as agroup. To split a32bitgroup into two 16bitgroups, use Fig. 2-16.

So far we have seen howto split the CRUaddress lines into:A) 8 32-bit lines (Fig. 2-12)B) 16 32-bitlines (Figs. 2-12 and 2-14)C) 64 32-bit lines (Fig. 2-13)D) 128 32-bit lines (Figs. 2-13 and 2-14)E) recombined 64-bit lines (Fig. 2-15)F) split-pair 16-bit lines (Fig. 2-16)

There are, of course, other ways to achieve some of theseresults. One way is to use a 4-to-16 decoder. This would allowthecombination of Fig. 2-14 plus two circuits from Fig. 2-12 to bereplaced by one circuit.

MEMORY BANK SELECTION

Memory system design presents the same address-mappingproblem asthe CRU. Should youwishto selecta section ofmemoryyou wouldhave several choices open to you:

• Select logic as shown in Fig. 2-17 will allow selecting anygroup of 4K words of storage, up to the maximum of 32Kwords.

32

•DEVICE 0(0-31)

— DEVICE 7 (224-255)

A7 A I

A8 — B

A9 C

G2A

A4

As

A

B G2A

CA7 A

Ae B

A9 C

1

— DEVICE 8 (256-287)

~ DEVICE 15(480-511)

A7 A

As B

A9 C

G2A— DEVICE 63

Fig. 2-13. By increasing the number ofdecoders to 9, wecan handle upto64different devices.

Z (FIG. 8 CRU-CLOCK)

7400 •BANK 2 (Z INPUT)

A3« *

7400 •BANK 1 (Z INPUT)

Fig. 2-14. Fora maximum systemwe can use this circuit with 36 decodersandassociated logic to select one of 128 CRU devices.

33

SELECT LINE N• o

SELECT LINE N + 1• o

A9»-

-•TO DEVICE CE

-• EXTENDED ADDRESS

Fig. 2-15. Two selectlinescanbetiedtogetherwith thiscircuit iftheneedarises.

• The useofa4-to-16 decoder will allow using address linesAO through A3 todecode in groups of2K words (4K bytes),up to a maximum of 32Kwords (64K bytes).

Several problems immediately arise from the use of thistechnique.

• What happens ifwerequire an address boundary ofIK for a4K range?

• The number of lines can get very cumbersome indeed.• Therearetimeswhenwe wishtoaddress as fewas2words

on the memory line (or memory mapped I/O).

These problems can be solved by circuits such as shown in Fig. 2-18.This circuit can be set to select any 2K word boundary. Adding anextra section would allow us toselect any Ikword boundary. Asanexample: closing switches A01, A12, A21 and A31 would causeselection of addresses in the range 22528 thru 24575 inclusive.

LINE N©-♦DEVICE 2

P-^DEVICE 1

Fig. 2-16. This circuit can split a 32-bit group into two 16-bit groups.

34

WORDS

A 0

B 1

C 2

3

4

G2A 5

G2B 6

G1 7

,__# n. iinos

Ai - —• <inifi.ni oi

_.._ ...A 0100 1*V?fl7

# i'??nn.iRift'^

m 1ft1R/1.0n/17Cl

MLMfclN •

.a '?4e;7ft,'?flfi71

,4./// •

+5V

74LS138

Fig. 2-17. A3-to-8 decoder allows selection of any single 4K-word block ofmemory, up to the maximum 32K of a 9900 system.

Fig.2-18.Thiscircuit can be used to select memoryon any 2Kboundaryratherthan the 4K boundaries offered by Fig. 2-17.

35

Sucha circuit canbe implemented withstandardlogic, with theswitches replaced by jumpers or plugs.

The circuit can be expanded to almost any level and requiresaccess only to the address lines and the memen line.

Using this approach, we can build modules ofmemory, selecting the addresses when connecting these modules together. Notethatwe havejust started the first sectionof the DMA requirement.The modules would nolongerdependon the 9900foraddresses, butwould depend only on the contents of the address (and data) lines,which could be generated by other devices.

Infact, exceptforthe IK boundary with 4Kmemory problems,we havesolvedthe addressingproblems. The IK boundaryproblemandothers of that nature can be solved withmore complexversionsof Fig. 2-18.

For CRU utilization it is recommended that the multiline de

coderapproach be used, since these devicesare more closelytied tothe processor.

EXTERNAL INSTRUCTIONS AND STATUS DISPLAY

From the discussion of the CRU, we learned that when any ofaddress linesAO through A2was active together with the CRUCLKsignal, an operationcode has been detected which requires externaldecoding and processing. Figure 2-19 shows a circuit which willdecode the address lines (see Fig. 2-20) and CRUCLK line. Notethat the IDLE instruction is the only one of these operations toactually be processed by the 9900 itself.

The other instructionsare used in the 990, but mightbe used inyour system for such purposes as control of interval timers, controlof a floating point processor, control of an array processor, or aFast-Fourier Transform processor. They can be used to control amemory mapping circuit to extend the capacity of the 9900, toaddress storage, or for interprocessor communication whenbuildinga multiprocessor system.

Pin 7 on the 9900 is also useful in the detection of instructions

being executed, since when it is active the address lines contain theaddress from which an instruction is being fetched and the data linescontain the instruction itself. The data lines can be checked, andspecial instructions could be externally executed or the instructioncould force an interrupt.

36

TO MEMORY AND CRU

CRU CLOCK SIGNAL

G1 G2A GIB

TT

INTERNALLY DEFINED

TO USER OEFINED EXTERNALINSTRUCTION LOGIC

INTERNALLY DEFINED

AO Al Al

CKOF H H L

CKON H L H

Fig. 2-19. The external instruction decode logic shown here makes it possible touse customized instructions, and also offers insurance against faulty CRUoperation. (Courtesy of Texas Instruments)

The designer could force new instructions (such as floatingpoint ordecimal instructions) into the machine by theuseofmemorywaits and external execution. Designing suchanextension isoutsidethe scope of this book. However I can show you an excellent use forthese signals as indicators of the processor state at any time. Thefollowing pins are probed on the processor and related circuits:

• The IDLE and RESET signals from Fig. 2-19 as well as theoutput CRU clock signal. These are pins Y2, Y3, and YOrespectively on the SN74LS138.

• Pins 7, 61 (write enable), and 63 (memory enable) on the9900.

The resultant pinout ofFig. 2-21 can beconnected to an LEDreadout to produce a front panel showing processor status. Notethat pins 32, 5,and 3of the 9900 arealso shown. The basic reasonsfor connecting these additional pins to an indicator are:

Pin 32. This output Fig. 2-9, under typical conditions, wouldusually result in avery brief, almost invisible flash oflight. However,it is possible for a more visible indication to occur as follows:

1. Looping in aninterrupt routine would mean thatthelowerpriority interrupts are being held, and the light wouldremain on. See Fig. 2-22 for a list ofinterruptpriorities.

2. Heavy interrupt rates can cause stacking ofthe interruptsand result in a visual indication of the interrupt rate. Thebrighter the light, the higher the rate.

37

EXTERNAL INSTRUCTION AO Al A2

LREX H H H

CKOF H H L

CKON H L H

RSET L H H

IDLE L H L

Fig. 2-20. Bit patterns on address lines AO, A1, and A2 for the five externalinstructions areshown here. (Courtesy of Texas Instruments)

Pin5 means that the 9900 has lifted off the address and-data,buses and is allowing another device to access memory. A visualindicator would show how much of the time (by brightness) is beingused by external devices on the line.

Pin3would have meaning, ifprobed with alamp indicator, onlyifmixed speed memories were used. Whenever this pin is active, theTMS9900 must wait for memory. The brightness of the lamp wouldindicate when aslow section of storage was being accessed.

(9900)

YO^-

Y2^>-

Y3^>-

32^>-

63^-

>>{>

o

-CRU ACTIVE

•RUN

♦WAIT

♦ RESET

♦ INT PENDING

♦ DMA

♦INST FETCH

♦ DATA

♦STORE

'SLOW MEMORY

Rg.2-21. Connecting indicators as shown here provides an informative front-panel displayfor a9900 system. Seetext for full useoftheinformation displayed.

38

00

CO

Inte

rru

pt

Lev

el

(Hig

hest

prio

rity

)0 1 2 3 4 5 6 7 8 9

10

11

12

13

14

(Low

est

prio

rity

)15

'Level

0ca

nn

ot

be

dis

ab

led

.

Vecto

rL

oca

tio

n

(Mem

ory

Ad

dre

ss

InH

ex)

00

04

08

0C

10

14

18

1C

20

24

28

2C

30

34

38

3C

Dev

ice

Ass

ign

men

t

Reset

Ex

tern

al

dev

ice

Ex

tern

al

dev

ice

Inte

rrup

tM

ask

Val

ues

To

En

ab

leR

esp

ecti

veIn

terr

up

ts

(ST

12

thru

ST

15

)

0th

rou

gh

F*

1th

rou

gh

F

2th

rou

gh

F

3th

rou

gh

F

4th

rou

gh

F

5th

rou

gh

F

6th

rou

gh

F

7th

rou

gh

F

8th

rou

gh

F

9th

rou

gh

F

Ath

rou

gh

F

Bth

rou

gh

F

Cth

rou

gh

F

Dth

rou

gh

F

Ean

dF

Fo

nly

Fig.

2-22

.Int

erru

ptpr

ioriti

esan

dm

aski

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elis

tedhe

re.(

Cour

tesy

ofTe

xas

Instr

umen

ts)

Inte

rru

pt

Co

des

ICO

thru

IC3

00

00

00

01

00

10

00

11

01

00

01

01

01

10

01

11

10

00

10

01

10

10

10

11

11

00

11

01

11

10

11

11

TMS9900

Family Support Chips

To support the TMS9900 processor, the manufacturer offers afamily of devices.

At this writing, the familyincludes seven chips in addition to theTMS9900, numbered as 9901 through 9907. The first three areprefixed "TMS" (TMS9901 through TMS9903) and the other fourbear a "TIM" prefix.

The four TIM devices are also numbered in the 74000 series,

and (with the exception of the TIM9904) are referred to in this

volume by their 74000-series identities. These are the devices, their74000-series numbers, and their functions:

• TMS9901 (no other identity) Programmable SystemInterface—provides up to 15 single-line interrupt codingand up to 16-bit I/O interfacing.

• TMS9902 (no other identity) Asynchronous Communication Controller—interfaces start-stop serial peripherals.

• TMS9903 (no other identity) Synchronous CommunicationController—interfaces serial peripherals which do not usestart-stop protocol.

• TM9904 (74LS362) Clock Generator—provides requiredfour-phase clock signals for entire system.

• TIM9905 (74LS251) 3-State Octal Multiplexer—acceptssignal from one of eight addressed input lines and directs itto single output line.

40

• TM9906 (74LS259) Octal Addressable Latch—Latches

single-line input signal into one of eight addressed outputstores.

• TIM9907 (74148) Priority Encoder—produces 3-bit code toindicate highest-priority input signal which is active.

For the purposes of this volume, only the 9901 through 9904are discussed, since the TMS9901 includes the functions providedby the remaining three chips. The 9901, in fact, is the functionalequivalent of two each of the other three chips, although not all thiscapability can be used at the same time.

TMS9901 PROGRAMMABLE SYSTEM INTERFACE

The TMS9901 is a standard 40-pin DIP device (Fig. 3-1) whichhas 9 CRU-interface lines which communicate with the 9900, 5

interrupt-interface lines which also communicate with the 9900, 22system-directed lines, a reset pin, two power pins, and a clock input.

The CRU-interface lines are CRUOUT (pin 2), CRUCLK (pin3), CRUIN (pin4), Address Select lines SO through S4, (pins 39, 36,35, 25, and 24), and Chip Enable (pin 5). The interrupt-interfacelines are INTREQ (pin 11) and ICOthrough IC3 (pins 15, 14,13, and12). The 22 system-directed lines are divided into three buffer

vccso

RSTl 1 [CRUOUT 2 [

u ] 40J 39

CRUCLK 3 [ J 38 PO

CRUIN 4 [ J 37 PI

CE 5 [ ] 38 SI

INT6 6 [ ]3S S2

INT5 7 [ ] 34 INT7/P15

7NT4 8 [ J 33 fiJTff/PM

INT3 9 C ] 32 INT9/P13

0* 10 [ ] 31 INT10/P12

INTREQ 11 [ ]30 INT11/P11

IC3 12 [ ]29 INT12/P10

IC2 13 [ ]» INT13/P9

IC1 14 C 3 27 INT14/P8

ICO 15 [ ]» P2

Vss 18 CINT1 17 [ ]24

S3

S4

TOTS" 18 [ ]23 INT1S/P7

P6 19 [ ] 22 P3

P5 20 [ ]21 P4

Fig. 3-1. The TMS9901 is supplied in a 40-pin DIP. These are the pin assignments. (Courtesy of Texas Instruments)

41

TIM

WOO

FIGURE 6 - TMS 9900-TMS 9901 INTERFACE

CKOUT

TMg IC0-IC2

M*0

— ICMCJTMS

M01

AV

AV

AV >

C=^>'

I

Fig. 3-2. Interconnection between TMS9901 andTMS9900 canbeas simple asthis. Note that 9904 can be replaced by discrete logic. (Courtesy of TexasInstruments)

groups. One primarily serves interrupts, one serves only as I/O,andonecan have itsbits set individually tobeeitherinterrupt orI/Ofunctions.

Ascan be seen from Fig. 3-2, the 9901 directly couples to the9900; it uses only a decodercircuit to enablethe CRU interface (thedecoder circuit consists of the circuit shown in Fig. 2-19, to obtainthe CRU clocking pulse and a comparator circuit to generate a Chip

42

Enable when address lines A3 through A9 inclusive contain thecorrectvalue). This chip-enable circuit must be active low andwillresult inmaking the9901 relocatable from the zeroposition, aswellas allowing multiple 9901 chips to be used.

The 9901 consists of three buffer groups: buffer group one(normally used for interrupts) consists of six input-output buffers(pins 9, through 17, and 18). They can also beused asinput buffers,allowing up to 22 lines to be used as input.

Buffer group two, (pins 23 and 27through 34) consists ofninebidirectional bufferswhich can be individually set to behave as eitherI/O ports or interrupt ports. Ifa portis predisabled as aninterruptport, then it can be usedas an I/O port in safety.

Buffer group threebehaves as a series of1-bit I/O ports (pins19 through 22, 26, 37, and 38).

Also included in the 9901 are a real-time clock, which can becontrolled andread through the use of CRU commands; a registermask, holding theinterrupt masks; a prioritizer and encoder, whichconverts 15-line code to 4 with latching to generate the interruptcodes; and CRU logic to control the above devices.

The 9901 allowsthe 9900 to have additionalfeatures. One is atrue real-time clock, which has an interrupt priority of 3 (see Fig.3-3). This clock, using the master clock that is usually crystalcontrolled, can behave eitheras aninterval timer, generating inter-

na CLOCK RtOtlTfB

•<=^>1 i£

CLOCK OfCKEMtNTM

lz«iAO ntaaTER

Fig. 3-3. Here is thereal-time clock portion ofthe9901 in block diagram form.Clock can be set or read via CRU interface, and produces interrupt whencountdown reaches zero. (Courtesy of Texas Instruments)

43

PRIORITIZE!!

ANO

INCOOCR

<iKf

o£>

<

7

u

C«U LOGIC

Fig. 3-4.Thiscircuitry insidethe 9901chipconvertsup to 15 individual interruptinput lines into the 5-line code required bythe 9900. (Courtesy ofTexas Instruments)

rupts at controlled intervals, or as an event timer (the count isaccessible). The clock can be set withan LDCR instruction, bit0 on(set to 1). Clock mode canbe entered without altering thecontentsofthe clock register, byusing the 1-bit instruction SBO, followed byan STCR instruction.

Another feature is a masked interrupt capability, which issomewhat more powerful than the simple priority interrupt of the9900 itself. Asanexample, it might be desirable to disable interrupt10 and allow interrupts 12 and 13 to remain enabled. With the 9900alone, disabling 10 means disabling 12 and 13 as well. Rememberthat interrupt priorities sequence the interrupts. If more than oneinterruptisactive at a time" the 9900 will processthe highest priorityfirst. Figure3-4showsthe basic logic ofthe 9901 interrupt circuits.

Stillanother feature provides latchedinput-outputlines for useby the 9900 and external devices. These lines may be alteredwithoutfear ofan indeterminatestate onoutput. Eachlineremainsinits previous state until specifically changed. Figure 3-5 shows this9901 feature. The linecanbe altered (ifinput) by an external device.

44

The importance of this unit lies in thefact that the CRU logic,including addressing, is already incorporated into the 9901. Notethat7 lines are dedicated to the I/O function andthata maximum of16 lines may be so used.

TMS9902 ARCHITECTURE

The TMS9902 ACC device (Fig. 3-6) provides the ability toconnect to the9900 anasynchronous device, such as teletypewritersof any kind; ASCII compatible CRTs; keyboard-printer devicessuch as the TI Silent 700 series or any device using Start-Stopprotocol, with a character length of 5 to 8 bits.

The9902 will further generate any lateral parity option (even,odd, or none) and detect incorrect parity conditions. Even paritymeansthe numberofon bitsis always kept even by turninganextrabiton and off. Odd parity means the number ofbits is always keptodd. No parity means a parity bit is not added.

The transmit and receive rates are independently programmable from approximately 62 bits per second toapproximately 76,000

I/O

CONTROL

DATA

LATCH

"--•J.y

s^

CRU

LOOIC

1

11

I/O

CONTROL

DATA

LATCH

-<

•C=^>

Fig. 3-5. Up to 15 I/O ports configured like this are available to the CRU interfacein the 9901 chip. (Courtesy of Texas Instruments)

45

TMS 9902

18-PIN PACKAGE

INT

X0UT

RIN

CRUIN

RTS

CTS

OSR

CRUOUT

VSS

—*. 1 18

—"*2

3

4

5

17

16

TMS 9902

15— —

14*

6 13

—*7

8

9

12

11

10

-

vcc

CE

?

CRUCLK

SO

SI

S2

S3

S4

Fig. 3-6. Basingof the 18-pin TMS9902packageis shownhere. Notethatonly5address lines are available. (Courtesy of Texas Instruments)

bits per second. An interval timer is also provided within the 9902,giving a resolution of64//.sec andaninterval ofupto 16,320/usee.

If usedwithin a combination system (see Fig. 3-7)containing a9901, the 9902 provides an extra interval timer. This extra timercould be used for purposes other than that of the one in the 9901.

The 9902 providesfour differentinterrupts, which are outputas oneinterrupt level(Fig.3-8).The actualcauseofthe interrupt canbe deciphered through the CRU interface.

Figure 3-9 shows how the 9900 and the 9902 (or the 9980 andthe 9902)are connected together. The decode logic consists of thatshown in Fig. 2-19 combined with a hardwired (or plug-alterable)comparator for address lines A3 through A9.

The two chips communicate over the CRU, using 32 bits ascommand words (see Figs. 3-10, 3-11, and 3-12). There are sixregisters in the 9902 which are available to the 9900. One is thecontrol register, which is used to set the stop bit length (one, oneand a half or two); the parity (none, even or odd); the master clockrate (dividethe inputclockby either 3 or 4); and the character length(5, 6, 7 or 8 bits). The others are the interval timer, and the receivedata rate, transmit data rate, transmit buffer, and receive bufferregisters.

46

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^£>M>TRT OUTPUT GENERATION

CRU

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OUTPUT

Fig. 3-8. Relationship between.the 9902status conditions and itsgeneration ofan interrupt request is shown bythis logic. (Courtesy ofTexas Instruments)

TMS 9902

0

CRUCLK

CRUOUT

CRUIN

SO

S1

S2

S3

S4

CE O

03TTL FROM TIM 9904

DECODE <C

TMS 9900

CRUCLK

CRUOUT

CRUIN

A10

A11

A12

A13

A14

A0-A9

Fig. 3-9. Direct connections between a 9902 and the 9900 can be made asshown inthis diagram. Note that the chip enable decode is not shown; see textfor details. (Courtesy of Texas Instruments)

48

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31 30 29 28 27 26 25 24

RESET NOT USED

TSTMD LDCTRL LOIR LROR LXDR

10 9 8

CONTROL, INTERVAL. RECEIVE

| RDV8 | ROR9 | ROR8

^

| XDV8 | X0R9 | XDR8

V

Rg.3-11. This chart shows in greater detail how the9902 issetupbywriting tospecific output bit addresses. The *STCR command is used to set bits intoaddresses 0 through 10, afterappropriate values are written intoaddresses 14through 11. (Courtesy of Texas Instruments)

Further data available to the 9900 (and the programmer) includesstatus flags anderror flags. The 9902interfacesto the outsideworld through TTL compatible circuits. There are times when an

50

DSCENB | TIMENB XBIENB RIENB BRKON RTSONJ

6

DATA RATE, TRANSMIT OATA RATE, AND TRANSMIT BUFFER REGISTERS

CONTROL REGISTER

| SBS1 | SBS2 | PENB | PQDD | CLK4M | - | RCL1 | RCLO |

yStop Bits

00 M/2

01 2

IX 1

I Party

OX none

10 even

11 odd

f*/(3+CLK4MI

INTERVAL REGISTER

Character Length

00 5

01 6

10 7

11 8

TMR7 | TMR6 | TMRS | TMR4 | TMR3 | TMR2 | TMR1 | TMRO |

I ITlTVL " «int X 64 X TMR

I I IRECEIVE DATA RATE REGISTER

~"V—TMR

RDR7 | RDR6 | RDRS | RDR4 | RDR3 | RDR2 | ROR1 | RDRO

" RDR '

frcv - lint -rJB RDV8 -j- RDR * 2

I I ITRANSMIT DATA RATE REGISTER

XDR7 | XDR6 | XOR5 | XDR4 | XOR3 | XOR2 | XDR1 | XDRO |

i i ™ ifxmt - tint - 8XDV8 * XDR •=- 2

I I I ITRANSMIT BUFFER REGISTER

I XBR7 1 XBR6 [ XBRS | XBR4 | X8R3 | XBR2 | XBR1 | XBRO [

NOTE 1: LOADING OFTHEBIT INDICATED BY| | CAUSES THELOADCONTROL

FLAG FOR THAT REGISTER TO BEAUTOMATICALLY RESET.

J

RS232 compatible interface is desired. This canbe accomplished bythe two circuits in Fig. 3-13.

TMS9903 SYNCHRONOUS COMMUNICATION CONTROLLER

Very little will be said about this integrated circuit, since it israther doubtful that the typical user would be interested in actually

51

AOORESSa

SO S1 S2 S3 84AODRESS10 NAME DESCRIPTION

1 1 1 t 1 31 INT Interrupt

1 1 t 1 0 30 FLAG Regiiter Load Control Flag Set1 1 1 0 1 29 OSCH Dun Set Stotut Change1 1 t 0 0 28 CTS Clear to Send

1 1 0 t 1 27 DSfl Deta Set Reedy

1 1 0 1 0 26 HTS Requett to Send

1 1 0 0 1 25 TIMELP Timer Elepted1 1 0 0 0 24 TIMERR Timer Error

1 0 1 1 1 23 XSRE Trentmit Shift Regiiter Empty1 0 1 1 0 22 XBRE Transmit Buffer Regiiter Empty1 0 1 0 1 21 RBRL Receive Buffer Regiiter Loadedt 0 1 0 0 20 DSCINT Data Set Statui Charge Interrupt (OSCH * OSCENBI1 0 0 1 1 19 TIMINT Timer Interrupt (TIMELP • TIMENB)1 0 0 1 0 18

— Not uied (elwayt • 0)1 0 0 0 1 1? XBINT Transmitter Interrupt (XBRE ' XBIENB)

1 0 0 0 0 16 RBINT Receiver Interrupt (RBRL ' RIENB)0 1 1 t 1 15 RIN Receive Input

0 1 1 1 0 14 RSBD Receive Start Bit Detect

0 1 1 0 1 13 RFBD Receive Full Bit Delect

0 1 1 0 0 12 RFER Receive Framing Error

0 1 0 1 1 11 ROVER Receive Overrun Error

0 1 0 1 0 10 RPER Receive Parity Error

0 1 0 0 1 9 RCVERR Rocolvo Error

0 1 0 0 0 8— Not uied lalwayl - 0)

7-0 RBR7-RBR0 Receive Buffer Regiiter (Received Datal

Fig. 3-12. These are the input bitaddress assignments used to recoverstatusand data information from the 9902. The listed status conditions are true ifthe bitat the corresponding address is a "1". (Courtesy of Texas Instruments)

usingsucha unit. Mostofthe functions performedby thischip wouldbe beyond the needs of that user.

Basically the interfacing is identical with the 9902, alreadydiscussed (see Fig. 3-14). The devices to which a 9903 are interfaced are usually of a class outside the scope of this book.

Features of the 9903 include DC to 250,000 bits per secondprocessing rates; dynamic (programmable) character length selec-

W-RS232

OUT«-RS232

330pF

f

SN75189

SN75188

+5V

WV

(TTL)••OUT

+t>V

(TTL)-•IN

Fig. 3-13. These two circuits can be used to interface RS232 signal levels withthe TTL signal levels of the 9902 chip.

52

[NTCMturTS

IMIU

1VNCH LEVELrtONOut SHIFTERS

l/F-

INTtRIIUFTS

SERIAL

SYNCH

HONOUS

l/F

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SHIFTERS

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Fig. 3-14. The TMS9903 interfaces much like the 9902. (Courtesy of TexasInstruments)

53

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OWHI A ION

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Fig. 3-15.ClockgeneratorTIM9904 pinout and internal circuits are shown here.Device is ina 20-pin DIP. (Courtesy ofTexas Instruments)

tionfrom 5 to 9 bits inlength; automatic zero plugging forSDLC orHDLC protocols; provision for four different typesofcyclic redundancy checks; twosyncregisters; interfacing forunclocked or NRZIdata; and a built-in interval timer.

TIM9904 CLOCK GENERATOR

The 9904(Fig. 3-15)generates all required clock signals for a9900 system. It is not limited to the 9900 processorfamily, but maybe used withother processors which require multiphase clocking,such as the 8080 chip family.

54

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Fig. 3-17. If9904 isnotto be used, specialMOS-level clockdrivercircuits likethisarerequired oneachofthe four clock phases. All components canvary by 10%.(Courtesy of Texas Instruments)

The 9904 is actually a MSI (medium scale integration) circuitcomposed ofseveralcircuit blocks, at lowercost thanthe separate-unit total cost.

The 9904 can of course be replaced by discrete parts by thehardy. SeeFigs. 3-16 and 3-17 fordiscrete circuit implementation.

56

9900 System Design

The minimum 9900 system resembles the typical micro-processorevaluation system, usually expected of 8-bit processors. Figure 4-1shows such a system, which contains the following;

256 words (512 bytes) of RAM;

1024 words of ROM or EPROM;

8 output lines, using CRUOUT;8 input lines, using CRUIN;

a 4-phase clock, using the 9904;one interrupt line (level 8);a reset switch, to generate the RESET interrupt externally;and

an External Load signal to generate the LOAD interrupt.

Note that this entire system requires only 13 IC's, and 6 ofthese are memories. Besides the memories, the 9904, the 9900

itself, and the CRU devices (74LS151 and 74LS259) only threediscrete logic chips are used. Two of these (the 74LS74's) generatethe load pulse. The other provides inversion for three control signals(inverters A, B, and C). The simplicity of this design attests to thecompatibility of the 9900 system circuits.

UPGRADING THE MINIMUM SYSTEM

Let us see how we can upgrade this minimal system:A first step could be improving the CRU clocking system. A

problem with the CRU interface shown is that the CRU clock signal

57

EXTERNAL

INTERRUPT '

ALV ABC

S SN74LS1S1

00 07

t-.—;—r~r8 INPUTS

_c-

rO

V.G D ABC

SN74LS259 CLEAR

00 Q7_

' ' 8 INPUTS

INTREO WE

ICO MEMFTi

ICI

IC2

IC3

CRUIN

CIRCLK

CRUOUT

ADDRESS

C 0015

Fig. 4-1. A "minimum" system using the 9900 can be built by following thisdiagram. Referto Fig. 2-3 for pinassignments ofthe 9900and to Rg. 3-15forpinassignments of the 9904. Basing of the memory chips and support logiccan beobtained from Tl data sheets available with the devices. Take special care toobserve decoupling requirements on all power lines and prevent noise andcrosstalkon signal lines. (Courtesy of Texas Instruments)

is also generated by the specialinstructions: IDLE; RESET; CKOF(CLOCKOFF); CKON(CLOCK ON); and LREX (LOAD OR RESTART EXECUTION). Thiscould causethe CRU to operate incorrectly, so let us replace the inverter C by the circuit in Fig. 2-19.This gives us a properly decoded CRU clock, as well as decodedinstructions.

58

10ARWCEI

7VAI0ARWCE1

7V~K

V0 A OE1 OE2

TMS4700

IOARWCE1

±L0 A 0E1 OE2

TMS4700

TMS4042 2

0ECE2

lO A R W CE1

A A I

Another improvement would be expanding the RAM capacity.Thelimit of256wordsofRAM isobviously lowformostuses; highercapacities might be desirable. The first choice, which requires theminimum change, is to replacethe 4042-2RAMS by 4047-45RAMSand usingaddress lines A5 and A6. An alternate choice, involvingmore chips, is to use the 4046-45 chipsandaddress linesA3throughA6. The first choice gives a maximum of 1024 words, while thealternative gives 4096 words, or 8K bytes.

Similarly, we can expand the ROM capacity. Use of the 4908EPROM will allow the user to expand the capacity ofhis read-only-

59

memory to 1024 words, while allowing both field-programming andalterability. The 74S472 PPOM allows field programming and 512words.

For more I/O capability we could expand the system with the9901. See Fig. 3-2 for basic couplinginformation. If combined withthe CRU-clock modification, this new modification would result in

dropping the 74LS151 and 74LS259. The I/O ports would replacethe chips (including programmable ports). The interrupt vectorstructure would be usable by the system. A real-time-clock wouldalso be now available.

Another step would be to add the 9902; if we already have the9901 in the circuit, we need some form of chip select to distinguishbetween the two.units. Address line A9 will do this job well with oneinverter; see Fig. 4-2. Adding the 9902 has now increased ourcapacity to handle a teletype or other terminal.

What do these changes buy us? We have, in our up-gradedsystem: external instruction decoding, 8K bytes of RAM, 2K bytesof ROM, 6 masked interrupts (with up to 15 available, as separatelines), 6 input/output ports with stable outputs to configure asneeded, a real-time-clock, and a programmable asynchronous interface.

Let us now start with the heavy-duty changes:First, replace the circuit of Fig. 4-2 with that of Fig. 2-12. This

increases our CRU selection capacity to 8 devices.Then, let us increase our storage capacity. Unfortunately, our

poor 9900 was not meant to handle more than two standard TTL

loads per line, so buffering is needed to boost the capacity further.We use the circuit in Fig. 4-3 as a sample buffering technique. Thiscircuit has been designed for a maximum capacity of 1024 words.However the 74LS139 has 4 more selector lines available, so we can

double the number of chip-selects. We can also boost capacity byusing the same technique we used in our original explanation of theRAM. This gives us a total capacity, in RAM or ROM, of 32,768words (or, if you wish, 65,536 bytes).

We can further subdivide any 4K word section into subsections,using our chip-select techniques.

Any section of our storage can contain ROM or EPROM.With memory size increased, let us now expand our I/O capac

ity by adding a second 9902 to handle a serial device, such as a

60

A9 •- TO PIN 17 OF 9902

PIN 15 OF 9900

TO PIN 5 OF 9901

Fig.4-2. This single-inverter circuit permits use of address line A9 to switch thechip-enable signal from a 9901 to a 9902 when your system includesone ofeach.

cassette drive. We can use one of our I/O ports from the 9901 as anon-off generator for the cassette deck.

We have now run into a terrible state of affairs. The ideal place

for ROMor PROM is at the top of storage, but the reset function,whichstarts up the system, is in the wrong place (as far as Vectorsare concerned). Since the reset function is essential to clean'startups, but the interrupt is not, let us perform a little trick on thesystem.

The load function should be activated as part of normal start-upanyway, so let us force it to be activated automatically. Figure 4-4showshowto accomplish this feat. Because the LOAD signalwill beon before the reset signal is finished, the vector at location0 is notused and the one at FFFC (HEX) is used instead. ROM nowbecomes part of the upper storage.

If we like, we can add memory mapped I/O; this technique ofI/O processing is particularly "sneaky" since it requires that anexternal device detect the signals used for memory access andsimulate memory. Such devices are basically outside the scope ofthis book, since they require peripheral controllers.

We can also add DMA; this technique allows an external deviceto access memory whilethe 9900 goes off-line. The pins on the 9900marked HOLD and HOLDA willallow this function to be performed.Figures 4-5 and 4-6 show a circuit (the Xis must be interconnected)whichallows up to 16 devices to seize the memory bus on a prioritybasis, while Figs. 4-7 and 4-8 give an architectural view of thistechniqueanda timing diagram. Since this technique is highly devicedependent and,.therefore, outside the scope of this book, we leavethe rest to the reader.

As we saw earlier, DMA and memory mapped I/O are twotechniques for getting data through the system without using the

61

•Il-C

SN74LS241

VS

2G 1Y-8Y

1A-8A

I—\Aa—•-<!ho-o—I*

2K

n—VW

tr-

SN74LS139

Q

DWEff

2K

t—vw

a:O

2K

o-l..

• R/Vy TMS 4043 2orCH SN74S287

"IF SWITCH IS OPEN.RAMt ARE USED.

Q

A7B-A14B

^

Sela

CRU. The DMA interfaces are very device dependent and outsidethe controlof the 9900. The result is a problem. How do we get thedata to the DMA device to allowit to perform its functions?

The answers are: via the CRU with interfacing, or via memorymapped I/O. We now see one of the main reasons for this form ofI/O. Figure 4-9 is one such diagram of a simple 16 bit memorymapping interface.

62

CS do-3

AH

CS 00-3

AH

CS 00-3

AH

1-0 CS. DO-3

3=tre 2G2G

1A/2Y 2A/1Y

SN74LS241

<—qcs O0-3

A ri

CS DO-J

AH

nCS 00-3

AH

04-07,4

*—0|CS D0-3A-H

i 2G

1A/2Y 2A/1Y

SN74LS241Ob-DII, >4

L-C CS DO-3

CS DO-3

AH

CS DO-3

AH

•-OJCS DO-3AH

I 2C

1A/2Y 2A/1Y

SN74LS241D12- .4

015

CS DO-3

AH

_0 CS DO-J

l—C|CS DO-3

AH

•-qcs O0-3AH

I 2G

1A/2Y 2A/1Y

SN74LS241

Rg. 4-3. When expanding the system to include additional memory, bufferingand chip selection become essential. This circuit shows how to mix PROM andROM chips. (Courtesy of Tl)

WHAT HAVE WE GOT NOW?

Our system currently consists of: 32,768 words of mixedROMand staticRAM. We have arealtimeclock, vectoredinterruptswithmasking, for up to 15 levels of interrupt, with at least 6 built in. Wehave 7 I/O lines, expandable (by sacrificing interrupt levels) to 16

63

9904/PIN4 -*—

TO "OLD" EXTERNAL

"NEW" EXTERNAL ' "^ LOAD

LOAD SIGNAL

Fig. 4-4. It's not always necessary to use both the LOAD and RESET vectorsprovided in the 9900 design. This circuit provides an auto-load start-up capability, permitting the LOAD vector at FFFC to serve for both LOAD and RESETactions.

I/O lines; up to 127 terminals of any protocol (remember that a 9903can be used anywhere a 9902 can be used); and up to 16 devices orcontrollers on the DMA line, with a virtually unlimited number ofmemory mapped peripherals. We have a cassette drive interface.What else can we add?

We can replace some of our bulky static RAMS with fasterRAMs, both static and dynamic. Of course, if we want to usedynamic RAMS, we have to use some sort of refresh circuitry and,for the fancier RAMS, address strobing. Since address strobing andrefresh circuitry are both dependent on the type of RAM, and sincethe number of different chips would fill a book (and they do), we showonly one example of one type of refresh circuit (Fig. 4-10).

If we have so much storage, we might like to avoid the horrorsof bad chips (rare though they are) by including parity circuits asshown in Fig. 4-11. Parity circuits allow the system to keep anintegrity check on the data by logging the count of the bits in eachword as being odd or even during storage. If the odd/even flag doesnot match the data retrieved, then a bit has been dropped and a chipmay be bad.

A very popular device for inputting data is the paper tapereader. Since most paper tape readers act as serial devices, wecould use a 9902 to interface to such a device. However, somereaders have no serializing logic and simply input the data in parallel.Figure 4-12 shows one way to interface such a parallel device.

We may wish to mix slow memory with fast, in order to improvethe cost-effectiveness of our system. This requires that the 9900,which has to know that the memory is valid, be signaled somehow.Figures 4-13 and 4-14 show how this can be done; Fig. 4-15 showsthe timing requirements.

64

p>^_ HOLD SIGNAL 0

7 BGS

—

"^

74148

A2 •—Xi

—Al

0 EO *

> X2

> X3

< i XZ j SN7408^L ^ PIN 64

7

74148—J

A2

Al

• X4

•^Xs

AO i—x«

o MHOLD SIGNAL 15

Fig. 4-5. For direct memory access applications we must be able to recognizerequests to HOLDthe 9900 off of the bus lines. This circuit prioritizes up to 16different HOLD requests.

xz»-

HOLDA

Xl-

X2-

X3-

+5V

+5V«

Yo

74LS138

G2A

G2B

G1

Yo

74LS138

G2A

G2B

G1 Y7

-DEVICE 0 MAX PRIORITY

-DEVICE 7

-DEVICE 8

-DEVICE 15 MIN PRIORITY

Rg. 4-6. No DMA activity can be permitted until the HOLD request is acknowledged. This circuit provides prioritized HOLD acknowledgement, for use withthe circuit of Fig. 4-5. Together the two circuits permit up to 16 different DMAactivities in conjunction with normal processing.

65

A0

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OUTPUTS.

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INPUTS.i I |

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16 26

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Fig. 4-9.Memory-mapped I/O is notdifficult. This circuit providesa single 16-bitword of memory-mapped I/O. When the assigned address is decoded (bycircuitry not shown), the data bus is connected to either the input or the outputport.

Have we taken this "minimum" system as far as we can?Almost, since most of what is left depends on external constraints.We can still add mass-storage devices; plotters and other graphicdevices; printers, card readers and punches; or just about anythingwe could think of. However, none of these devices are really part ofthe 9900. They are, rather, peripherals and don't really belong in thisbook.

THE MAXIMUM SYSTEM?

We have by now taken our little minimum system pretty far.Have we reached the maximum possible system? Not in theslightest.

Our system can easily handle 64K bytes of ROM and RAM, cancommunicate with 127 terminals, can use CRT terminals with

graphics* and as many floppy discs as we wish. If we have big and

68

CD

CO

un

Al

A2

43

A4

DB

IN

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Fig. 4-11. Forbetter confidence in system reliability the parity of each memorywordcan be checked at each access. This circuitgenerates and checks parity,with no wait states. (Courtesy of Texas Instruments)

DATA INPUTS

FROM PAPER

TAPE READER

DATAO »-

DATA1 »-

DATA? »-

OATaJ »-

0ATA4 »-

DATA? »~

DATAO »-

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L^ DECODED PAPER

TAPE READER AOORESS

(DECODED FROM AO • Al II

ADDRESS BUS

[PAPER TAPE READERINTERRUPT

ITO INTERRUPTPROCESSORI

Fig.4-12. Specific peripheral devices require specific interfaces. This circuit,toconnect an 8-level paper tape reader, is typical of such device-dependentdesigns. (Courtesy of Texas Instruments)

70

ADDRESS

TMS 9900READY

WAIT

ADDRESS

DECODEn

<T1r"i_

SLOMEM

a |

Rg. 4-13. If slowmemory is to be used, "wait" states must be introduced intonormal processor action to give the memory time to respond. This circuit provides one wait state on each memory access. (Courtesy of Texas Instruments)

grand ideas it can handle cartridge (and bigger) discs. We caninterface withprinters, card readers andplotters. And, ifwe wish,we can communicate with other computers in a network.

We could even design multi-processor configurations, withmemory mapping and banking (techniques to expand our storagecapacity). We could use many different outputdevicesfor our 9900system. The only limits are our ambition, time, and money.

ADDRESS

TMS 9900READY

WAIT

ADDRESS

DECODE

s~

:b sLOMEM

4V_

P\ P—I

D

>

Q

02TTL —

LRg. 4-14. For even slower memory, two wait states may be necessary. Thiscircuit providesthem. (Courtesy of Texas Instruments)

71

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Hints About Peripherals

Manyhobbyistsprefer to have, instead ofa printer, a CRTinterfaceto handle the printout from their systems. The reasons are quitesimple. Theelectronics ina CRTterminal are farless expensive thanthe mechanical parts in a printer. The electronics of a CRT systemare already packaged into every TV set sold. The speed of a CRTbased system will easily beat any hard-copy terminal.

There are ofcourse manyways to interface a CRT to the 9900system we have developed. We may use a separate terminal, suchas the Lear-Seigler ADM series or any other terminal of ASCIIRS232C or 20mAloop type. There are manyterminalsof thisclass,usually known as "Teletype replacement" CRT terminals. Otherexamples include the VUCOM terminals and the TI VDT913 (seeFig. 5-49). These canallbe interfacedthrougha 9902.The terminalsthat are known as CRT-specific terminals, such as the IBM 3270series, the VUCOM2 terminals and the IBM 2260 series, are meantto be seen by the processor as a CRT and not as any sort ofreplacement. These usually are connected through a 9903 (SCC)device.

The CRT interface is described here in general terms only,since a full set of plans would require a book by itself.

Figure 5-1 shows a basic block diagram of such a systeminterface, while Fig. 5-2showsa block diagram ofthe display controller.

73

DATA

ilADDRESS0

TMS9900

SYSTEM

MEMORY

DATA ADDRESS

tot

BUFFER

SN74S241

7^>

ADDRESS

CONTROL

BUFFER

SN745241

7T

ADDRESS

5^

DISPLAY

CONTROL

unit

0

<w>RF

MODULATOR

2sZ

T.V.

Fig. 5-1. Designof a video I/Osystem requiresdetailed knowledge of both videoand digital signalrequirements.This block diagramcan serve as a startingpointfordesign of a system using shared memory. Both the 9900 and the displaycontrol unit have access to the common system memory.

We can see a problem with this technique since the displaycontrollerneeds to access storage quite often. Two approaches arepossible:We canuse DMAlogicto interface both devices to storage.The 74S241 tri-state BUFFER chip can allow us to create such asystem, see Fig. 5-3 for an example. We can, alternatively, use adifferenttechniquewitha specialmemoryblock set up inan unusualfashion, which cycle-steals time from the 9900 (see Fig. 5-4).

This memory block would contain buffer latches such as the74LS374 and the 74LS241 chips, issuinga WAIT to the 9900if it isservicing the display controller when a request for a word in theblockbecomes available. Shouldyou wish to builda system using adisplay controller in either fashion above, a strong grounding indigital electronics and TV signal generation is recommended. Thefollowing chipsshouldbe investigated: The 74S412 makes nicedatabuffers, the TMS3409 recirculating shift registers, the 74LS253for

74

characterand graphics control, the74S472 as acharacter generatorPROM and control signal PROM, andthe 74LS241 forDMAcontrolbuffers. We can go no further on this subject within this book.

DISC SYSTEMS

The term "floppy disc" was coined by some rather annoyedpeople when they first saw an IBM "diskette." The diskette wasdesigned to hold the "microcode" for an IBM 370/145 computer.Becauseit resembledamagnetic disc(which it was)andwas flexibleenough to "flop" when waved around, someone called it a "blastedFLOPPY disc." He (or she) was only half-right.

C5

COLUMNC4

C3

C2

C1

R4

ROW FO

PS-

HOLDA-

ROW R1"

BL0CK

SELECT

SPARE GND-

HOLDA-

+5V-

+5V-

HOLDA-

745241

< TS 2G

745241

745241

-A14

-A13

-A12

-All

-A10

-A9

-A8

-A7

-HOLDA

-A6

-AS

-A4

-A3

-A2

-Al

-A0

-SPARE

-HOLDA

-WE

-DBIN

-M£MEM

SPARE

•HOLDA

Rg.5-2. Essential elements ofadisplay controller include counters tokeeptrackof rows and columns, a character generator, and blanking generator. Controlcircuitry must develop video sync pulses at appropriate intervals.

75

<>

DATA

BUSBUFFER

a ADDRESS

BUFFER

MASTER

COUNTER

COLUMNS IC)

ROWSlRl

_sz_

CONTROL

CIRCUITRY

SHIFT

REGISTER

IICHARACTER

GENERATOR

(PROMI

~Z^~

JSZ_

Hef1L

Mntl

output

omwtw

tUWI>

VIDEO

BLANK

AND

LEVEL

GENERATOR

Fig.5-3.Column and rowcounts can be converted to system memory addressesby this circuit, intended as a sample of DMA interfacing. Displaycapabilityis 16rows of 64 characters each.

The name has, to the chagrin of IBM, become part of com-puterese and a diskette is often called a floppy. Don't ask IBM forinformation about floppies, however, since it still makes them veryupset.

See Figs. 5-5 and 5-6 for an idea of what a floppy and its drivelooklike. Afloppydisc controDercan be built using a separate 9900,ifyouwish, in the form ofa smart storage device. Texas Instruments

•

512-1K WORD

DYNAMIC/STATIC

RAM

(EXTRA FAST)

DATA

TMS9900

SYSTEMDISPLAY

CONTROL

BUFFERS

AND

LOGICA14(

A6-A14

A6-

A14

BLOCK

SELECT

A6-,745241

BUFFERS

AND

LATCHESA14

wattWAIT

•siCONT ROL LINES

Fig. 5-4. Cycle stealing can be used instead of DMA to interface the displaycontroller to memory. This diagram shows how.

76

INDEX

HOLE

DRIVE HUB

OPENING

TRACK 00

TRACK 76

Fig. 5-5. Floppy disk layout looks like this. Disk itself is enclosed in protectiveenvelope and should never be removed from it. Total of 77 tracks are availablefor storage of data.

has, in fact, developed such a design as an example of the sheerflexibility and power of their 9900 processor, but I personally believethat this is pure over-kill. You may find a floppy or series of floppiesvery useful, but there are several ways to obtain them already torun. Any computer mag willhave information on available units fromvarious manufacturers. These manufacturers will either have a

Fig. 5-6. Typical floppy disk drive unit has slot with hinged lid. When disk (inenvelope) is inserted inslot and lidis closed, stored data is available for reading.

77

floppycapableof fittingyour 9900 system or will devise an interface.Texas Instruments already has a pre-built floppyfor use with a 990system, all 9900 systems and their TTL versions are called part ofthe 990 series machines. Of course you can obtain a floppy with astandard interface and modify it to fit. You will have to make thesebasic modifications most likely; a memory mapping interface forcontrol and status. If the floppy delivers bytes and generates byteaddress, then you willneed byte/word buffering for both data andaddresses. If you wish to use a CRU interface for control lines thenreread the section on CRU interfacing. Because of the variety ofoptions available at any stage of designing such a system, we mustleave this up to you to design. Once again, this project is outside thescope of this book.

Should you wish to have more capacity than is available in afloppy discsystem, withhigher access speeds, you may wish to lookat cartridge discs, such as the Texas Instruments DS31.

If even cartridge discs are insufficient, you may wish to lookateven higher capacity systems. These are, usually, of the 2314-compatible, 3330-compatible or "Winchester technology" drives,with single drive capacities of:

• 2311 type drives, to 7.25 megabytes• 2314 type drives, to 29.0 megabytes• 3330 type drives, to 200 megabytes• 3340 (Winchester), to 70 megabytes• 3350 (Winchester), to 300 megabytes.

If you need such capacities, you should remember the price riseswith capacity and speed, though you do get more for your dollar asthe price rises. Interfacingbecomes much more tricky and complex.Devices of this calibertake up more space. Devices like this use upmore power. This book is about the hobbyist and home computer,not your own versions of Colossus (and Guardian?).

OTHER PERIPHERALS

Plotters are now available, from several manufacturers, whichcan interface through a standard asynchronous interface, as if theywere teletypes. This can allow you do your own graphs, drawingsand other plotter oriented functions.

Unless you wish to use these devices seriously, be warned thatthey are still expensive in more ways than one. As an example, that

78

card reader might not be too expensive to purchase, but you willalsoneed a keypunch....

Youmay also wish to add a line printer. These printers are farfaster than the typical10 to 40 characters per second printers usedby the hobbyists. These printers can reach speeds of up to 2000 linesper minute (yes, two thousand), with up to 132 characters per line.The equivalent speed in characters per second is around 4,000 CPS.Once again, you can choose from several interface options. Youcanuse the CRU to output bytes and control. A 16-bit interface shouldbe adequate. You can use an ACC interface such as the 9902. Ofcourse you can always use memory mapped I/O, or perhaps youwould prefer to use the DMA and send full lines at a time, with abuffer.

Should you wish you can add a card reader to read your programs and data. When combined with a printer and some control cardcapabilities in your software, a card reader will give you a batchsystem, allowing unattended operation.

By using a 9903 SCC and a data-link you can hook up yoursystem to a larger computer, as if you had a "Remote Job Entry"(RJE) system. Since there is nothing stopping you from making theother computer another 9900 based system, you can start buildingyour own network.

We can use time-sharing to allow our friends access to themachine. We might even charge for the time and resources (shadesof the service bureau).

Basically the 9900, like any well-designed computer, is limitedmore by the ingenuityof the users and designers than anything else.We have gone as far as we can in this book. The rest is up to you!

79

Appendix

Instruction Codes

.This appendix containsthe instructioncodes of the 9900, the 990/4and the 990/10. As youwill quickly see, the instruction set of thesecomputers has been carefully thought out to allow efficient implementation on both an LSI microprocessor and a TTL minicomputer.

You will also see why it is easy to fall in love with the 9900family. Just compare this instruction set with that of any othermicroprocessor.

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tha

nS

T1

-0

an

dS

T2

»0

JMP

00

01

00

00

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mp

un

con

dit

ion

al

un

co

nd

itio

na

l

JN

C0

00

10

11

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mp

no

carr

yS

T3

-0

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E0

00

10

11

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mp

no

teq

ua

lS

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JN

O0

00

11

00

1Ju

mp

no

overf

low

ST

4=

0

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C0

00

11

00

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mp

on

carr

yS

T3

-1

JO

P0

00

11

10

0Ju

mp

od

dp

ari

tyS

T5

-1

A.8

CR

UM

UL

TIP

LE

-BIT

INST

RU

CT

ION

S

Gen

era

lfo

rma

t

01

23

45

67

89

10

11

12

13

14

15

OP

CO

DE

CT

SS

The

Cfi

eld

spec

ifie

sth

en

um

ber

of

bits

tobe

tran

sfer

red.

IfC

=0,

16bi

tsw

ill

betr

ansf

erre

d.T

heC

RU

base

regi

ster

(WR

12.

bits

3th

roug

h14

)de

fine

sth

est

arti

ngC

RU

bit

addr

ess.

The

bits

are

tran

sfer

red

seri

ally

and

the

CR

Uad

dres

sis

incr

emen

ted

wit

hea

chbi

ttr

ansf

er,a

ltho

ugh

the

cont

ents

ofW

R12

isno

taf

fect

ed.

Tg

and

Spr

ovid

em

ulti

ple

mod

ead

dres

sing

capa

bili

tyfo

rth

eso

urce

oper

and.

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orfe

wer

bits

are

tran

sfer

red

(C-

1th

roug

h8)

,th

eso

urce

addr

ess

isa

byt

ead

dres

s.If

9or

mor

ebi

tsar

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ansf

erre

d(C

=0

,9th

roug

h15

).th

eso

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ess

isa

wo

rdad

dres

s.If

the

sour

ceis

addr

esse

din

the

wor

kspa

cere

gist

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dire

ctau

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crem

ent

mod

e,th

ew

orks

pace

regi

ster

isin

crem

ente

dby

1if

C-

1th

rou

gh

8,an

dis

incr

emen

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by2

oth

erw

ise.

MN

EM

ON

ICO

PC

OD

EM

EA

NIN

G

RE

SU

LT

CO

MP

AR

ED

TO

O

ST

AT

US

BIT

S

AF

FE

CT

ED

DE

SC

RIP

TIO

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12

34

5

LD

CR

ST

CR

00

11

00

00

11

01

Lo

ad

co

mm

un

ca

tio

n

reg

iste

r

Sto

re

co

mm

un

ca

tio

n

reg

iste

r

Yes

Yes

0-2.

5*

0-2

J5T

Beg

inni

ngw

ith

LSB

of(S

A),

tran

sfer

the

spec

ifie

dn

um

ber

ofb

its

from

(SA

)to

the

CR

U.

Beg

inni

ngw

ith

LSB

of(S

A),

tran

sfer

the

spec

ifie

dn

um

ber

of

bit

sfr

om

the

CR

Uto

(SA

).L

oa

du

nfi

lled

bit

po

siti

on

sw

ith

0.

tST

5is

aff

ecte

do

nly

if1

<C

<8

.

A.9

CR

USI

NG

LE

-BIT

INST

RU

CT

ION

S

oi

Gen

era

lfo

rma

t:O

PC

OD

E

CR

Ure

lativ

ead

dres

sing

is'u

sed

toad

dres

sth

ese

lect

edC

RU

bit.

11

12

13

14

15

SIG

NE

DD

ISP

LA

CE

ME

NT

CO

MN

EM

ON

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PC

OD

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G

ST

AT

US

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S

AF

FE

CT

ED

DE

SC

RIP

TIO

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12

34

56

7

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O

SB

Z

TB

00

01

11

01

00

01

11

10

00

01

11

11

Set

bit

too

ne

Set

bit

toze

ro

Test

bit

2

Set

the

sele

cted

CR

Uo

utp

ut

bit

to1.

So

tth

ese

lect

edC

RU

ou

tpu

tb

itto

0.

Ifth

ese

lect

edC

RU

inp

utb

it»

1,se

tS

T2

.

Gen

era

lfo

rma

t:

01

23

45

67

89

10

111

21

31

4IS

OP

CO

DE

DIS

PL

AC

EM

EN

T

A.1

1SH

IFT

INS

TR

UC

TIO

NS

Gen

era

lfo

rma

t:

01

23

45

67

89

10

111

21

31

41

5

OP

CO

DE

CW

IfC

=0.

bits

12th

roug

h15

ofW

RO

cont

ain

the

shif

tco

unt.

IfC

=0

and

bits

12th

roug

h15

ofW

RO

=0,

the

shif

tco

un

tis

16

.

MN

EM

ON

ICO

PC

OD

EM

EA

NIN

G

RE

SU

LT

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MP

AR

EO

TO

O

ST

AT

US

BIT

S

AF

FE

CT

ED

DE

SC

RIP

TIO

N0

12

34

56

7

SL

A

SR

A

SR

C

SR

L

00

00

10

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00

00

10

00

00

00

10

11

00

00

10

01

Sh

ift

left

ari

thm

eti

c

Sh

ift

righ

ta

rith

met

ic

Sh

ift

righ

tci

rcu

lar

Sh

ift

rig

ht

logi

cal

Yes

Yes

Yes

Yes

0-4

0-3

0-3

0-3

Sh

ift

(W)

left

.F

ill

va

ca

ted

bit

po

siti

on

sw

ith

0.

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ift

(W)

rig

ht.

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lva

cate

db

it

posi

tion

sw

ith

orig

inal

MSB

of(W

).

Sh

ift

(W)

rig

ht.

Sh

ift

pre

vio

us

LS

B

into

MS

B.

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ift

(W)

righ

t.F

ill

vaca

ted

bit

po

siti

on

sw

ith

0*s.

JPA

.12

IMM

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IAT

ER

EG

IST

ER

INST

RU

CT

ION

S

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era

lfo

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t

01

23

45

67

89

10

11

12

13

14

15

OP

CO

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NI

W

IOP

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EM

ON

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PC

OD

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RE

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ST

AT

US

BIT

S

AF

FE

CT

ED

DE

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12

34

56

78

91

0

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AN

DI

CI

LI

OR

I

00

00

00

10

00

1

00

00

00

10

01

0

00

00

00

10

10

0

00

00

00

10

00

0

00

00

00

10

01

1

Ad

dim

med

iate

AN

Dim

med

iate

Co

mp

are

imm

ed

iate

Lo

ad

imm

ed

iate

OR

imm

ed

iate

Yes

Yes

Yes

Yes

Yes

0-4

0-2

0-2

0-2

0-2

<W

)+

IOP

-*(W

)

<W

)AN

DIO

P-M

W)

Co

mp

are

(W)

toIO

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dse

t

app

rop

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est

atu

sb

its

IOP

-*(W

)

(W)O

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P-+

(W)

A.1

3IN

TE

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AL

RE

GIS

TE

RL

OA

DIM

ME

DIA

TE

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RU

CT

ION

S

Gen

era

lfo

rma

t:

01

23

45

67

89

10

11

12

13

14

15

OP

CO

DE

N

IOP

MN

EM

ON

ICO

PC

OD

EM

EA

NIN

GD

ES

CR

IPT

ION

01

23

45

67

89

10

LW

PI

LIM

I

00

00

00

10

11

1

00

00

00

11

00

0

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ad

wo

rksp

ace

po

inte

rim

med

iate

Lo

ad

inte

rru

pt

mask

IOP

-*(W

P).

noS

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its

affe

cted

IOP

,b

its

12

thru

15

"*

ST

12

thru

ST

15

A.1

4IN

TE

RN

AL

RE

GIS

TE

RST

OR

EIN

STR

UC

TIO

NS

10

111

21

31

41

5

Gen

era

lfo

rma

t:

No

ST

bit

sa

rea

ffecte

d.

8

MN

EM

ON

ICO

PC

OD

EM

EA

NIN

GD

ES

CR

IPT

ION

01

23

45

67

89

10

ST

ST

ST

WP

00

00

00

10

11

0

00

00

00

10

10

1

Sto

rest

atu

sre

gis

ter

Sto

rew

ork

space

po

inte

r

(ST

)-+

(W)

(WP

)-*

(W)

A.1

5RE

TURN

WO

RKSP

ACE

POIN

TER

(RT

WP

)IN

STRU

CTI

ON

u1

23

45

6

Gen

era

lfo

rma

t

91

0

00

00

0o-

11

10

0N

Th

eR

TW

Pin

stru

ctio

nca

uses

the

foll

ow

ing

tran

sfer

sto

occ

ur:

(WR

15

)-(S

T)

(WR

14

)-(P

C)

(WR

13

1-C

WP

)

ST

AT

US

BIT

S

BIT

NA

ME

INS

TR

UC

TIO

NC

ON

DIT

ION

TO

SE

TB

ITT

O1

ST

OL

OG

ICA

L

GR

EA

TE

R

TH

AN

C.C

B

CI

AB

S

All

Oth

ers

IfM

SB

(SA

)-

1an

dM

SB

(DA

)-

0.

or

ifM

SB

(SA

)-

MS

B(O

A)

an

dM

SB

of((

DA

MS

A)]

-1

IfM

SB(W

)=

1an

dM

SBof

IOP

-0.

or

ifM

SB

(W)

-M

SBof

IOP

and

MSB

of|I

0P

-(W

))»

1

If(S

A)

*0

Ifre

su

lt*

0

ST

1A

RIT

HM

ET

IC

GR

EA

TE

R

TH

AN

C.C

B

CI

AB

S

All

Oth

ers

IfM

SB

(SA

)-

Oan

dM

SB

(DA

)•

l.o

rif

MS

B(S

A)

-M

SB

(DA

)

an

dM

SBof

[(D

A)-

ISA

!)>

1

IfM

SBIW

)=

0an

dM

SBof

IOP

-1.

orif

MSB

(W)

-M

SBof

IOP

an

dM

SBof

(I0

P-I

W)]

-1

IfM

SB

(SA

)»

0an

d(S

A)

*0

IfM

SB

of

resu

lt•

0an

dre

sult

10

seB

ITN

AM

EIN

ST

RU

CT

ION

CO

ND

ITIO

NT

OS

ET

BIT

TO

1

ST

2E

QU

AL

P.C

B

CI

CO

C

CZ

C

TB

AB

S

All

oth

ers

If(S

A)

-(D

A)

If(W

)=

IOP

If(S

A)

an

d(D

A)

-0

If(S

A)

an

d(D

A)

=0

IfC

RU

IN-

1

If(S

A)

=0

Ifre

sult

-0

ST

3C

AR

RY

A.A

B,

AB

S,A

l,D

EC

,

DE

CT

,IN

C,

INC

T.

NE

G,S

,SB

SL

A.S

RA

.SR

C.S

RL

IfC

AR

RY

OU

T-

1

Ifla

stb

itsh

ifte

do

ut

»1

ST

4O

VE

RF

LO

WA

.AB

Al

S.S

B

DE

C.D

EC

T

INC

,IN

CT

SL

A

DIV

AB

S.

NE

G

IfM

SB

(SA

)-

MS

B(D

A)

an

dM

SB

of

resu

lt*

MS

B(D

A)

IfM

SB

(W)

-M

SB

of

IOP

an

dM

SB

of

resu

lt*

MS

B(W

)

IfM

SB

(SA

)*

MS

B(D

A)

an

dM

SB

of

resu

lt*

MS

B(D

A)

IfM

SB

(SA

)=

1an

dM

SB

of

resu

lt=

0

IfM

SB

(SA

)-

Oan

dM

SB

of

resu

lt-

1

IfM

SBch

ang

esd

uri

ng

shif

t

IfM

SB

(SA

)'

Oan

dM

SB

(DA

)=

l.o

rif

MS

B(S

A)

»M

SB

(DA

)

and

MSB

of

((D

A)-

(SA

Il-

0

If(S

A)

-8

00

0,6

ST

SP

AR

ITY

CB

.M

OV

B

LD

CR

,S

TC

R

AB

.SB

.SO

CB

.SZ

CB

If(S

A)

has

od

dn

um

ber

of

1's

If1

<C

*8

an

d(S

A)

has

od

dn

um

ber

of

1's

Ifre

sult

has

od

dn

um

ber

of

1's

ST

6X

OP

XO

PIf

XO

Pin

str

ucti

on

isex

ecu

ted

ST

12

-ST

15

INT

ER

RU

PT

MA

SK

LIM

I

RT

WP

Ifco

rres

po

nd

ing

bit

ofIO

Pis

1

Ifco

rres

po

nd

ing

bit

of

WR

15

is1

Index

Architecture 45 LSI minicomputer 13

B

Buffer chip 74

M

Machines, 16 bit 11

Maximum system 68

c Memory bank selection 32

Chip, bufferClock generator

74Microprocessor, 12 bit 10

54Minicomputer, LSI 13

Communication controller,0

Organization, data & addressinternal

synchronousContext switching

51

2318

19CRT interface 73

CRU interfacing 28P

Peripherals 78

D Programmable system interface 41

Data & Address organization 18

Disc systems 75 R

Display, status 36 RAMS 64

E

External instructions 36

S

Selection, memory bank 32

Status display 36

Switching, context 23

G Synchronous communicationGenerator, clock 54 controller 51

Systems, disc 75

1 maximum 68

Input/output techniques 27 upgrading minimum 57

Instructions, external 36

Interface, CRT 73 T

programmable system 41 Techniques, input/output 27

Interfacing, CRU 28

Internal organization 19 U

Interrupts 24 Upgrading minimum system 57

95

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