Host-based V2X transceiver module - U-blox...THEO-P173 Host-based V2X transceiver module System...

THEO-P173 Host-based V2X transceiver module System Integration Manual

www.u-blox.com

UBX-15029954 - R05

Abstract

This manual describes the system integration of THEO-P173 module, which is designed for applications such as traffic safety, intelligent traffic management and entertainment. This host-based module implements a complete IEEE 802.11p radio that includes MAC/LLC/baseband processor and a dual 5.9 GHz RF front-end in a surface mount module. The module can be connected to a host processor through the USB and is offered in professional grade.

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THEO-P173 - System Integration Manual

UBX-15029954 - R05 Contents

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Document Information

Title THEO-P173

Subtitle Host-based V2X transceiver module

Document type System Integration Manual

Document number UBX-15029954

Revision and date R05 26-Jul-2017

Disclosure restriction

This document applies to the following products:

Product name Type number Firmware version PCN / IN reference Product status

THEO-P173 THEO-P173-01A-00 - N/A Engineering sample

THEO-P173 THEO-P173-02A-00 - N/A Engineering sample

u-blox reserves all rights to this document and the information contained herein. Products, names, logos and designs described herein may in whole or in part be subject to intellectual property rights. Reproduction, use, modification or disclosure to third parties of this document or any part thereof without the express permission of u-blox is strictly prohibited.

The information contained herein is provided “as is” and u-blox assumes no liability for the use of the information. No warranty, either express or implied, is given, including but not limited, with respect to the accuracy, correctness, reliability and fitness for a particular purpose of the information. This document may be revised by u-blox at any time. For most recent documents, visit www.u-blox.com.

Copyright © 2017, u-blox AG.

u-blox® is a registered trademark of u-blox Holding AG in the EU and other countries. ARM® is the registered trademark of ARM Limited in the EU and other countries.



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Contents Contents .............................................................................................................................. 3

1 System description ....................................................................................................... 5 1.1 Overview and applications .................................................................................................................... 5

1.1.1 Module architecture ...................................................................................................................... 6 1.1.2 Radio interface .............................................................................................................................. 6 1.1.3 Operation modes .......................................................................................................................... 7

1.2 Pin configuration and function ............................................................................................................. 8 1.2.1 Pin attributes ................................................................................................................................. 8 1.2.2 Pin description ............................................................................................................................... 8

1.3 Supply interfaces .................................................................................................................................. 9 1.3.1 Main supply inputs ........................................................................................................................ 9 1.3.2 Power-up sequence ..................................................................................................................... 10 1.3.3 Power-down sequence ................................................................................................................ 12

1.4 System function interfaces .................................................................................................................. 12 1.4.1 Module Power-on ....................................................................................................................... 12 1.4.2 Module Power-down ................................................................................................................... 12 1.4.3 Configuration signals .................................................................................................................. 12 1.4.4 USB link enable ........................................................................................................................... 13 1.4.5 1PPS signal .................................................................................................................................. 13

1.5 Data communication interfaces .......................................................................................................... 13 1.5.1 USB 2.0 Interface ........................................................................................................................ 13 1.5.2 SPI interface ................................................................................................................................ 14

1.6 General Purpose IO ............................................................................................................................. 14 1.7 Antenna interfaces ............................................................................................................................. 14

1.7.1 Antenna RF interfaces ................................................................................................................. 14

2 Design-in ..................................................................................................................... 16 2.1 Overview ............................................................................................................................................ 16

2.1.1 Reference schematic .................................................................................................................... 16 2.2 Antenna interfaces ............................................................................................................................. 17

2.2.1 RF Transmission line design ......................................................................................................... 18 2.2.2 Antenna design ........................................................................................................................... 21

2.3 Supply interfaces ................................................................................................................................ 24 2.3.1 Module supply design ................................................................................................................. 24

2.4 Data communication interfaces .......................................................................................................... 25 2.4.1 USB 2.0 ....................................................................................................................................... 25 2.4.2 SPI ............................................................................................................................................... 26

2.5 Other interfaces and notes ................................................................................................................. 26 2.6 General high speed layout guidelines .................................................................................................. 26

2.6.1 General considerations for schematic design and PCB floor-planning .......................................... 26



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2.6.2 Component placement ................................................................................................................ 27 2.6.3 Layout and manufacturing .......................................................................................................... 27

2.7 Module footprint and paste mask ....................................................................................................... 27 2.8 Thermal guidelines.............................................................................................................................. 29 2.9 ESD guidelines .................................................................................................................................... 30 2.10 Design-in checklist .............................................................................................................................. 31

2.10.1 Schematic checklist ..................................................................................................................... 31 2.10.2 Layout checklist ........................................................................................................................... 31

3 Software ..................................................................................................................... 32 3.1 Software development kit ................................................................................................................... 32 3.2 Software architecture overview ........................................................................................................... 32 3.3 Compiling the LLC driver and tool ...................................................................................................... 34 3.4 Loading the firmware ......................................................................................................................... 34 3.5 Loading the LLC driver ........................................................................................................................ 35

4 Handling and soldering ............................................................................................. 36 4.1 Packaging, shipping, storage and moisture preconditioning ............................................................... 36 4.2 ESD handling precautions ................................................................................................................... 36 4.3 Reflow soldering process .................................................................................................................... 36

4.3.1 Cleaning ...................................................................................................................................... 37 4.3.2 Other remarks ............................................................................................................................. 38

5 Regulatory compliance .............................................................................................. 39

6 Product testing ........................................................................................................... 40 6.1 OEM manufacturer production test .................................................................................................... 40

6.1.1 “Go/No go” tests for integrated devices ...................................................................................... 40 6.1.2 RF functional tests ....................................................................................................................... 41

Appendix A: Glossary ....................................................................................................... 43

Related documents........................................................................................................... 44

Revision history ................................................................................................................ 44

Contact .............................................................................................................................. 45


UBX-15029954 - R05 System description

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1 System description

1.1 Overview and applications The THEO-P173 module is a compact, embedded transceiver module from u-blox that facilitates development of electronics for Vehicle-to-Everything (V2X) communication systems. This module is offered in automotive grade for applications such as traffic safety, intelligent traffic management and entertainment.

The THEO-P173 module supports both the ETSI ITS-G5 and the IEEE 1609 (WAVE) standards at the access layer level, covering Europe and US. The module includes a complete dual channel single radio operating in the 5.9 GHz DSRC band with up to +23 dBm output power.

The THEO-P173 module comes in a surface mount package that requires connection to 5.9 GHz antennas, host processor connection through an USB or SPI link, and power supply. The module is an automotive-qualified single or dual channel IEEE 802.11p radio, operating from -40 °C to +85 °C ambient temperature.

Table 1: THEO-P173 main features summary

Applications

• Vehicle to vehicle communication • Intelligent Transport Systems • Vehicle Safety Services • Vehicle to Infrastructure Communication • Commercial transaction via cars



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1.1.1 Module architecture

The block diagram of THEO-P173 module is provided in Figure 1 and is valid for the professional grade variant.

Figure 1: THEO-P173 block diagram

1.1.2 Radio interface The THEO-P173 supports IEEE 802.11p standard operation in the 5.9 GHz radio band and is available in the following setup:

• THEO-P173-01A – Dual-channel single radio 5.9 GHz with two antenna pins for diversity support and USB 2.0 data link to the host.

• THEO-P173-02A – Dual-channel single radio 5.9 GHz with two antenna pins for diversity support and SPI Slave data link to the host.

Table 2 reports a summary of the supported features for the 802.11p standard on this module. Feature Description

Standards IEEE 802.11p – 2010 ETSI ES 202 663

IEEE 1609.4 – 2010

Frequency bands 5.850 – 5.925 GHz (channels 172, 174, 176, 178, 180, 182, 184)

Channel bandwidth 10, 20 MHz1

Supported data rates 3, 4.5, 6, 9, 12, 18, 24, 27 Mbps for 10 MHz BW signal

Maximum output power +23 dBm with IEEE 1609 Class C-compliant transmitting mask [13] [14]2

Minimum sensitivity -97 dBm@3 Mbps

Transmit power control 0.5 dB steps

Table 2: Radio characteristics of THEO-P173

1.1.2.1 Physical layer

The THEO-P173 PHY implements an 802.11p fully compliant physical layer radio transceiver employing advanced mobility receiver algorithms. The PHY RF front-end can provide multiple radio configurations, allowing the

1 20 MHz channel bandwidth is not supported by the current firmware. 2 RF output power limit for ITS-G5 is +23 dBm/MHz, G5-SCH2 and G5-SCH3 channels +13 dBm/MHz, G5-SCH4 channel -10 dBm/MHz [17].

USB

GPIOs

M_RST_NGPS1PPS_1.8V

SPI

SPIFLASH

BASEBANDCONTROLLER

TRANSCEIVER

POWER SUPPLY

TCXO

RF FRONTEND

RF FRONTEND

3.3V 5.0V

5.0V

ANT1

ANT2

THEO-P173



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THEO-P173 module to implement single or dual radio DSRC systems. The RF sub-system provides separate antenna ports for the 5.9 GHz band via castellated edges of the module. In the dual-radio configuration, the THEO-P173 PHY effectively operates as two independent PHY modules, each operating on a different radio channel.

The PHY provides 2-antenna diversity transmission and reception at 5.9 GHz for optimal radio performance. A summary of the operating modes and supported features are listed below:

• Single-radio mode (1 or 2 antenna diversity operation) • Dual-radio mode (1 antenna per channel), 2 independent IEEE 802.11p radios operating on different

radio channels3 • Transmit antenna cyclic delay diversity (2 antenna operations in 5.9 GHz band only) • Fast mode changes for synchronized channel switching systems.

1.1.2.2 MAC layer

THEO-P173 MAC implements a full IEEE 802.11p compliant MAC layer, for one or two independent radio channels providing fast, time-synchronized channel switching functionality. It also supports multiple queue sets thus allowing packets to be queued while the PHY/MAC is operating on another channel.

The MAC provides the following operating modes:

• Single radio, single channel operation: Only one radio is used. • Single radio, time-synchronized multi-channel operation: Channel switching between two channels with

independent set of transmit queues. • Dual radio, multi-channel operation: Independent MAC/PHY entities operating concurrently on different

radio channels. Optional coordination between the channels to avoid self-interference while operating on close radio channels.

• Dual radio time synchronized multichannel operation: Similar to dual-radio multi-channel operation, plus one of the radios optionally performs channel switching between two channels with independent sets of transmit queues.

Full support for MAC time-synchronization is provided via an external GNSS receiver under software control or using an external 1PPS signal. Other features of the MAC include various radio channel measurements:

• Channel utilization (ratio of channel busy time to measurement duration) • Channel active ratio (proportion of time that the radio is tuned to the SCH or CCH, respectively) • Per-channel statistics (number of packets successfully transmitted, number of packets that failed to

transmit, number of packets successfully received, and number of packets received in error. Broken down according to broadcast, multicast, and unicast packets)

• Received signal and noise power levels.

1.1.3 Operation modes The THEO-P173 module has several operating modes. The operation modes and general guidelines for operation are defined in Table 3:

General Status Operating Mode Description

Power-down Not Powered 5V0 and 3V3 supply not present or below the operating range: module is switched off.

Reset4 5V0-PAx and 3V3_DIG supply within operating range and M_RST_N pin is low. All internal voltage rails are still active, register and memory states are not maintained. Upon exiting reset mode, device boot is required to re-enter any operation mode mentioned below.

Normal Operation Active Tx/Rx data connection enabled, system running at specified power consumption.

Table 3: Description of operation modes of the module

3 Not supported by the current hardware and firmware release. 4 The module should not be held in this mode for an extended period of time.



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1.2 Pin configuration and function

1.2.1 Pin attributes 1. FUNCTION: Pin function. 2. PIN NAME: The name of the package pin or terminal. 3. PIN NUMBER: Package pin numbers associated with each signals. 4. POWER: The voltage domain that powers the pin 5. TYPE: Signal type description:

- I = Input - O = Output - I/O = Input and Output - D = Open drain - DS = Differential - PWR = Power - GND = Ground - PU = Internal Pull-Up - PD = Internal Pull-Down - H = High-Impedance pin - RF = Radio interface

6. SIGNAL NAME: The signal name for that pin in the mode being used. 7. REMARKS: Pin description and notes.

1.2.2 Pin description The pin definition for the THEO-P173 module is provided in Figure 2. Table 4 lists the pin-out of the THEO-P173 module, with pins grouped by function.

Figure 2: THEO-P173 pin assignment



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Table 4: THEO-P173 module pin description, grouped by function

Do not apply any voltage to digital, control and radio signal groups while in Not Powered mode to avoid damaging the module.

1.3 Supply interfaces

1.3.1 Main supply inputs The power for the THEO-P173 module must be supplied via 5V0_PA1/5V0_PA2 and 3V3DIG pins. All other supply voltages used inside the modules are generated from the 3V3_DIG through internal DC/DCs and LDOs, including the 1V8 voltage rail for digital and control I/O signals. M_USB_VBUS is used as voltage reference for USB PHY and can be connected to the same voltage rail of 5V0_PAx or supplied later to enable the USB link.

5 Not internally connected to Ant2 domain 6 Not internally connected to Ant1 domain 7 10 kΩ internal pull-up to 1.8 V

Function Pin Name Pin No. Power Type Signal Name Remarks

Power 3V3_DIG 3, 4 3V3_DIG PWR Module supply input Voltage supply range: 3.0V – 3.6V

5V0_PA1 13 5V0_PA1 PWR 5GHz RF supply (Ant1)5 Voltage supply range: 4.5V – 5.5V

5V0_PA2 36 5V0_PA2 PWR 5GHz RF supply (Ant2)6 Voltage supply range: 4.5V – 5.5V

GND 5, 12, 16, 18, 20, 22, 24, 25, 27, 29, 31, 32, 35, 37, 40, 44, 47, 51, 53, 60, ePAD

GND GND Module ground

Digital USB_DP 46 3V3_DIG DS USB Differential Data +

USB_DM 45 3V3_DIG DS USB Differential Data -

M_SPI_SCK 39 1.8V O SPI master clock Powered by internal domain

M_SPI_MOSI 38 1.8V O SPI MOSI Powered by internal domain

M_SPI_MISO 41 1.8V I SPI MISO Powered by internal domain

M_SPI_CS 42 1.8V O SPI chip select Powered by internal domain

Control M_RST_N 2 1.8V I/O,PU7,D Module reset Active low M_USB_VBUS 48 VBUS PWR USB VBUS detect input

GPS_1PPS 52 1.8V I 1PPS reference Powered by internal domain

BOOT0 56 1.8V I,PU Bootstrap Pin Refer to section 1.4.3

BOOT1 57 1.8V I,PD Bootstrap Pin Refer to section 1.4.3

BOOT2 55 1.8V I,PU Bootstrap Pin Refer to section 1.4.3

M_IO_SPARE 43 1.8V I/O GPIO Alt. function: additional SPI_CS

Radio RF5G_ANT1 19 5V0_PA1 RF Antenna signal

RF5G_ANT2 30 5V0_PA2 RF Antenna signal

Other NC 1, 6-11, 14-15, 17, 21, 23, 26, 28, 33-34, 49-50, 54, 58-59, 61-62

- - Reserved Do not connect



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The current drawn by the module through the supply pins can vary by several orders of magnitude depending on operation mode and state. It can change from the high current consumption during Wireless transmission at maximum RF power level, to the low current consumption during low power idle-mode. Average power consumption of the module in typical V2X use cases is ~2.1W over the temperature range. Peak power consumption may be however much higher due to RF modulation and signal amplification.

Detailed description on the electrical requirements of the supply voltages can be found in the THEO-P1 Data Sheet [1].

Rail

Allowable Ripple (peak to peak)8

over DC supply Current consumption, active mode

Current consumption, maximum

Notes

10-100kHz 100kHz-1MHz >1MHz

5V0_PA1 𝟖𝟖𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 𝟒𝟒𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 𝟐𝟐𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 380 mA 425 mA Peak current meas. at 85°C

5V0_PA2 𝟖𝟖𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 𝟒𝟒𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 𝟐𝟐𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 380 mA 425 mA Peak current meas. at 85°C

3V3_DIG 𝟖𝟖𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 𝟒𝟒𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 𝟐𝟐𝟖𝟖 𝒎𝒎𝒎𝒎𝒑𝒑𝒑𝒑−𝒑𝒑𝒑𝒑 650 mA 760 mA Peak current meas. at 85°C

Table 5: Summary of voltage supply requirements

The THEO-P173 module can be powered by one of the following DC supplies:

• Switching Mode Power Supply (SMPS) • Low Drop Out (LDO) regulator

The SMPS is the ideal choice when the available primary supply source has higher value than the operating supply voltage of the THEO-P173 module. The use of SMPS provides the best power efficiency for the overall application and minimizes current drawn from the main supply source.

While selecting SMPS, ensure that AC voltage ripple at switching frequency does not violate the requirements specified in Table 5. Layout shall be implemented to minimize impact of high frequency ringing. See section 2.3.1.1 for additional information.

The use of an LDO linear regulator is convenient for a primary supply with a relatively low voltage where the typical 85-90% efficiency of the switching regulator leads to minimal current saving. Linear regulators are not recommended for high voltage step-down as they will dissipate a considerable amount of energy.

Independent of the selected DC power supply, it is crucial that it can handle the high peak current generated by the module. It is recommended to provide at least 20% margin over stated peak current when designing the power supply for this module.

1.3.2 Power-up sequence During power up of the THEO-P173 module, it is a good practice to delay the power rail ramp-ups between each other (3V3_DIG and 5V0_PAx) to reduce the inrush current on the main voltage rail of the system. The only limitation is that M_USB_VBUS must always be provided only when the 3V3_DIG rail is stable; avoid M_USB_VBUS voltage presence when 3V3_DIG is absent as it may damage the module. A good addition to protect the module is a 47 kΩ resistor connected in series with the module pin 48. Figure 3 and Table 6 suggest a suitable circuit to provide the 5V reference to the M_USB_BUS pin using THEO-P173 own internal reset.

Figure 4 shows the recommended power sequence of the module while Table 7 specifies the recommended timings. If the M_RST_N pin is driven by the host, it is recommended to apply >100 ms delay with respect to 3V3_DIG ramp-up. Else, M_RST_N can be left open; in this case, the module will handle Power-on sequence by itself9.

8 Ripple measured on u-blox EVK’s power connectors. 9 Module internal reset delay is about 100 ms.



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Figure 3: USB_VBUS supply sequence example

Reference designator

Description Manufacturer P/N

Q1, Q2 N-channel + P-channel MosFET, 2,5 V drive voltage Panasonic FG6943010R

R1 Thick Film resistor, 10 kΩ 5%, 0402 Generic Generic

R2 Thick Film resistor, 1 kΩ 5%, 0603 Generic Generic

C1 Ceramic capacitor, 100 nF X7R 20% Generic Generic

Table 6: USB_VBUS supply sequence recommended parts

Parameter Min. Typ. Max. Unit Remarks

t_Vpa - - 100 ms 5V0_PAx must be enabled before M_RST_N release.

t_delay 0 1 - ms

t_ramp-up - - 1 ms Referred to soft-start of internal supplies.

t_reset 100 - - ms M_RST_N internally held low for 100 ms.

Table 7: THEO-P173 recommended power sequence timings

Figure 4: Recommended power-up sequence of THEO-P173 module



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1.3.3 Power-down sequence Figure 5 shows the two recommended power down sequences for the module. The designer is required to choose one of the recommended sequences while removing power from the module.

Figure 5: Recommended power-down sequence of THEO-P173 module

It is recommended not to apply power to a single rail for an extended period of time.

1.4 System function interfaces

1.4.1 Module Power-on The power-on sequence of THEO-P173 module can be initiated by applying the respective voltage to the supply pins and releasing M_RST_N signal. An internal pull-up resistor is available on the M_RST_N pin. Rebooting of the module is required every time M_RST_N is de-asserted (if a module reboot is required, M_RST_N should be held low for >2 ms).

1.4.2 Module Power-down THEO-P173 module can enter Reset mode by asserting M_RST_N signal (logic level 0). After M_RST_N assertion, power on 5V0_PAx/3V3_DIG can be removed to enter Not Powered mode.

Name I/O Description Remark

M_RST_N I/O Module reset Referenced to internal domain through a pull-up resistor.

M_RST_N signal is powered by internal 1V8 voltage domain and should be driven in Open-Drain mode without any pull circuitry to ground or to external voltage rails.

1.4.3 Configuration signals The integrator can set the BOOT [2: 0] pins before M_RST_N release to configure the desired host interface. The pins should not be set externally on -01A and -02A versions of the module as they are already configured with a default operation mode.



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Bootstrap options are listed in Table 8 and are used to set communication bus with the host. A 4.7 kΩ resistor to ground is required to configure a pin as logic level 0; else, the pin must be left open (logic level 1) to keep its default value.

Host interface selection BOOT2 BOOT1 BOOT0 Remark

SPI Master 1 0 1 Default configuration for THEO-P173-01A10. Firmware supports USB connection to the Host.

SPI Slave 1 1 0 Default configuration for THEO-P173-02A. SPI connection to the Host for firmware download.

Reserved - - - All other configurations are reserved.

Table 8: Bootloader interface selection

The BOOT [2: 0] pins are powered by internal 1.8 V voltage domain.

1.4.4 USB link enable THEO-P173 module detects the M_USB_VBUS signal to enable USB communication link. Connect this pin to a 5 V reference voltage to enable the USB physical interface. This pin provides a voltage reference to the internal USB phy.


M_USB_VBUS I USB 5V reference pin Connect to 5V reference voltage to enable USB phy.

1.4.5 1PPS signal The GPS_1PPS input is required by the radio to align transmissions during channel switching and for timekeeping. The signal rising edge must be synchronized with UTC time. The maximum pulse width can be up to 250 ms.


GPS_1PPS I 1Hz UTC time reference Powered by internal domain

The 1PPS signal from a GPS receiver is mandatory on this pin to support the WAVE protocol stack [8] though this is not strictly required as per ITS-G5 [7] (still recommended due to future standard updates under discussion). The 1PPS signal can also be used to add a time tag to the registered events.

If the 1PPS signal is not used, this pin can be pulled low through a 100 kΩ resistor.

GPS_1PPS signal is powered by the internal 1.8 V voltage domain. Avoid GPS_1PPS signal presence when 3V3_DIG is absent.

1.5 Data communication interfaces The THEO-P173 module supports USB 2.0 peripheral Interface or SPI as host interfaces and the Wireless traffic will always be communicated via one of these interfaces. Currently, the firmware supports USB 2.0 communication link only.

1.5.1 USB 2.0 Interface The USB Device interface is compliant with the USB 2.0 Specification [4] with 480 Mbps link speed.

Name I/O Description Remarks

USB_DP I/O USB Serial Data + Differential signal

USB_DM I/O USB Serial Data - Differential signal

The module's USB host interface pins are powered by the 3V3_DIG voltage domain.

10 May require external SPI Flash for other THEO-P173 modules.



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1.5.2 SPI interface THEO-P173 module supports an SPI Master/Slave interface, which is used to download the bootloader from a flash memory or an application processor. The SPI Master mode is used to download the module’s bootloader from the internal flash memory (THEO-P173-01A) and then the firmware is downloaded through the USB bus11. When the SPI is set in Slave mode (THEO-P173-02A), the interface will be used to download the firmware directly from the host.


M_SPI_SCK I/O SPI master clock Powered by internal domain Output if SPI Master mode Input if SPI Slave mode

M_SPI_MOSI I/O SPI MOSI Powered by internal domain Output if SPI Master mode Input if SPI Slave mode

M_SPI_MISO I/O SPI MISO Powered by internal domain Input if SPI Master mode Output if SPI Slave mode

M_SPI_CS I/O SPI chip select Powered by internal domain Reserved if SPI Master mode Input if SPI Slave mode

M_SPARE_IO I/O SPI chip select Powered by internal domain. Output if SPI Master mode Configurable as GPIO

Table 9: SPI signal definition

The module's SPI interface pins are powered by an internal 1V8 voltage domain.

1.6 General Purpose IO12 A configurable GPIO is available on the module and its usage is configured by available firmware releases. See section 3 for further information.


M_SPARE_IO I/O GPIO Powered by internal domain. Alt. function: SPI chip select.

M_SPARE_IO is powered by an internal 1V8 voltage domain.

1.7 Antenna interfaces

1.7.1 Antenna RF interfaces THEO-P173 module provides two antenna interfaces for multiple stream support; the designer must follow the recommendations mentioned below while developing an antenna interface for the module:

• The RF5G_ANT1/RF5G_ANT2 pins have a nominal characteristic impedance of 50 Ω and must be connected to the external antennas through a 50 Ω transmission line to allow proper RF transmission and reception.

• Good isolation must be provided between the various antennas in the system. Special care should be taken to maximize isolation between antennas operating in the same or nearby bands.

Refer to section 2.2 for information on how to properly design circuits compliant with these requirements.

11 THEO-P173 supports DFU protocol for firmware download through USB. 12 Not supported by the current firmware release.



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RF5G_ANT1 RF Antenna 1 interface Internal AC coupling, pin compliant to EN61000-4-2 Level 4 [5]

RF5G_ANT2 RF Antenna 2 interface Internal AC coupling, pin compliant to EN61000-4-2 Level 4 [5]

Special care is required to avoid enabling RF transmission without a properly terminated antenna trace. The module tolerates up to 10 dBm reflected power on antenna interfaces in transmission mode.

The receiver maximum operating input level is -20 dBm (PER may exceed 10% above this value). The input level should not exceed 0 dBm to avoid damage to the receiver section.

The module's RF5G_ANT1 and RF5G_ANT2 pins are internally AC-coupled and powered by 5V0_PA1 and 5V0_PA2 voltage domains respectively.


UBX-15029954 - R05 Design-in

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2 Design-in

2.1 Overview For an optimal integration of THEO-P173 module in the final application board, it is recommended to follow the design guidelines stated in this chapter. Every application circuit must be properly designed to guarantee the correct functionality of the related interface, however a number of points require close attention during the design of the application device.

The following list provides a rank of importance in the application design, starting from the highest relevance:

• Module antenna connection and layout: RF5G_AN1 and RF5G_ANT2 pins and component/ground clearance.

The antenna circuit affects the RF compliance of the device integrating THEO-P173 module with applicable certification schemes. Follow the recommendations provided in section 2.2 for schematic and layout design.

• Module supply: 5V0_PAx, 3V3_DIG, and GND pins.

The supply circuit affects the RF compliance of the device integrating THEO-P173 module with applicable certification schemes. Follow the recommendations provided in section 2.3 for schematic and layout design.

• High speed interfaces: USB and SPI pins.

High speed interfaces can be a source of radiated noise and can affect the compliance with regulatory standards for radiated emissions. Follow the recommendations provided in section 2.4 and 2.6 for schematic and layout design.

• System functions: pins indicated as Configuration signals and other NC pins.

Accurate design is required to guarantee that the voltage level is well defined during module boot. Follow the recommendations provided in section 2.5 and 2.6 for schematic and layout design.

2.1.1 Reference schematic Figure 6 illustrate a typical application schematic for THEO-P173 while Table 10 lists the suggested part numbers for a generic application.

Reference Designator

Description Manufacturer P/N

U1 THEO-P173 module u-blox

J1, J2 Application specific RF connector Generic Generic

C1 to C6 CAP, CER, 47uF ±20%, X5R, 10V, SMD 1206 Generic Generic

C7, C8 CAP, CER, 100nF ±20%, X7R, 50V, SMD 0603 Generic Generic

L1, L2 Ferrite bead

R1 Thick film resistor, 100KΩ 5%, SMD 0603 Generic Generic

R2 Thick film resistor, 4K7Ω 5%, SMD 0603 Generic Generic

Q1 N-channel MOS transistor, logic level FET Generic Generic

Table 10: Reference schematic part list



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Figure 6: THEO-P173 Application schematic

2.2 Antenna interfaces THEO-P173 module provides two RF interfaces for connecting the external antennas.

Antenna ports RF5G_ANT1 and RF5G_ANT2 have a nominal characteristic impedance of 50 Ω and must be connected to the related antenna or RF switch through a 50 Ω transmission line to allow proper impedance matching along the RF path; a bad termination of the pin may result in poor performance or even damage to the RF section of the module.

For optimal antenna performance in multi-radio mode, the isolation between the antennas must be maximized; the designer must follow the requirements specified in Table 11 and Table 12 to ensure good performance.



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2.2.1 RF Transmission line design RF transmission lines from the antenna pins up to the related antenna connectors must be designed so that the characteristic impedance is close to 50 Ω. Figure 7 illustrates the design options and the main parameters that need to be considered when implementing a transmission line on a PCB:

• The micro strip (a track coupled to a single ground plane, separated by dielectric material). • The coplanar micro strip (a track coupled to ground plane and side conductors, separated by dielectric

material). • The strip line (a track sandwiched between two parallel ground planes, separated by dielectric material).

The coplanar micro strip is the most common configuration for printed circuit boards.

Figure 7: Transmission line trace design

To properly design a 50 Ω transmission line, the following remarks should be taken into account:

• The designer should provide enough clearance from surrounding traces and ground in the same layer; in general a trace to ground clearance of at least two times the trace width should be considered and the transmission line should be “guarded” by ground plane area on each side.

• The characteristic impedance can be calculated as first iteration using tools provided by the layout software. It is advisable to ask the PCB manufacturer to provide the final values that are usually calculated using dedicated software and available stack-ups from production. It could also be possible to request an impedance coupon on panel’s side to measure the real impedance of the traces.

• FR-4 dielectric material, although its high losses at high frequencies may be considered in RF designs providing that (also refer to section 2.2.1.1):

o RF trace length must be minimized to reduce dielectric losses. o If traces longer than few centimeters are needed, it is recommended to use a coaxial connector

and cable to reduce losses. o Stack-up should allow for thick 50 Ω traces and at least 200 µm trace width is recommended to

assure good impedance control over the PCB manufacturing process. o FR-4 material exhibits poor mechanical and thermal stability and thus less control of impedance

over the trace length. Contact the PCB manufacturer for specific tolerance of controlled impedance traces and use materials characterized for 6 GHz applications13.

13 For example, Isola 370HR.



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• The transmission line’s width and spacing to GND must be uniform and routed as smoothly as possible: route RF lines in 45° angle.

• Add GND stitching vias around transmission lines as shown in Figure 814.

• Ensure solid metal connection of the adjacent metal layer on the PCB stack-up to main ground layer, providing enough vias on the adjacent metal layer as shown in Figure 8.

• Route RF transmission lines far from any noise source (as switching supplies and digital lines) and from any sensitive circuit to avoid crosstalk between RF traces and Hi-impedance or analog signals.

• Avoid stubs on the transmission lines, any component on the transmission line should be placed with the connected pin over the trace. Also avoid any unnecessary component on RF traces.

Figure 8: Example of RF trace and ground design from THEO-P173 Evaluation Kit (EVK)

2.2.1.1 Additional remarks

The THEO-P173 RF interface uses the 5.9 GHz band for communicating with other 802.11p devices. This band requires additional considerations to reduce the losses due to PCB traces. Two main factors should be considered during stack-up definition to minimize PCB costs while keeping trace losses within acceptable ranges:

• Skin depth losses • Dielectric dissipation factor • Stray capacitance of components on the transmission line

The formulas presented in this section are intended to provide an introduction to high-frequency RF design and should be considered as an approximation. It is the responsibility of the designer to evaluate the best tradeoff between cost and performance to guarantee that PCB losses are kept under control.

Total loss along the transmission line should be kept lower than 1 dB in order not to degrade the module performance.

Total Return Loss at module pin (including antenna contribution) should be better than 15 dB in the whole frequency band to guarantee module reliability.

If the designer cannot fulfill the requirements in this section with respect to using standard FR-4 material, it is recommended to consider using substrate materials specifically suited for high-frequency applications.

14 Recommended via to via pitch for coplanar micro strip design is <λ/10 (~2.5mm).



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Skin depth losses

At low frequencies the current flowing on a PCB traces follows the path of lower resistance while at frequencies higher than 1 MHz, the current follows the so called “lowest impedance” path. In the second case, the Skin Effect takes place imposing the signal current to flow only on the outer parts of the conductors; in some cases only a fraction of a micrometer. Skin depth effect is dependent both on material characteristics and frequency and can be estimated using the equation below:

𝜌𝜌𝜋𝜋𝜋𝜋𝜋𝜋

[𝑚𝑚];

Where: 𝜌𝜌 is the material resistivity [Ωm], 𝜋𝜋 is the magnetic permeability [H/m] and 𝜋𝜋 the frequency of interest.

The signal current can be assumed to flow in the first 5 skin depths of the conductor and for a copper trace at 6 GHz; this results in an effective depth of 4 μm around the trace section.

Ferromagnetic materials (like Nickel-based surface finishing) can play a major role in high-frequency signal attenuation, greatly reducing the skin depth and thus increasing resistive losses on the transmission line.

Wider traces exhibit lower losses. Removing the solder resist on the transmission line should be carefully evaluated to guarantee that copper finishing process won’t affect the transmission line performance.

Dielectric dissipation factor

Insulating materials used in PCB fabrication may exhibit frequency-dependent dielectric constant (𝜀𝜀𝑟𝑟) or dielectric losses (tangent loss, θ). 802.11p uses a relatively small channel bandwidth so phase distortion related to dielectric constant variation over frequency is not a concern; however losses related to particular dielectrics still present a challenge for the designer. Those losses can be estimated by the following equation15:

𝜋𝜋𝜋𝜋𝜋𝜋√𝜀𝜀𝑟𝑟𝑐𝑐

[% 𝑐𝑐𝑚𝑚⁄ ];

Where: 𝜀𝜀𝑟𝑟 is the relative dielectric constant, 𝜋𝜋 is the tangent loss of the material and 𝑐𝑐 is the speed of light.

The standard FR-4 material widely used for PCB manufacturing is in general a poor choice due to high losses over 1 GHz (tangent loss: 0.01 to 0.02) but may still be considered in the design if the RF trace length is kept at minimum (not more than a few centimeters).

If a long transmission line is required, the designer must consider low tangent loss dielectric materials.

Stray capacitance of components on the transmission line

Stray capacitance from SMT pins can play a major role in signal integrity at 6 GHz. Hence, it is important to fulfill the recommended specifications for proper operation. The designer should define the stack-up so that the discontinuities introduced by those pins are contributing only by a fraction of total trace width to reduce return loss degradation. This includes the module RF pins and connector pin themselves. Once the excess area from SMT pins is known, the stray capacitance can be estimated using the following:

𝐶𝐶𝑠𝑠𝑠𝑠𝑟𝑟𝑠𝑠𝑠𝑠 = 𝜀𝜀𝑟𝑟𝜀𝜀0𝐴𝐴𝑠𝑠𝑠𝑠𝑟𝑟𝑠𝑠𝑠𝑠

ℎ

𝐴𝐴𝑠𝑠𝑠𝑠𝑟𝑟𝑠𝑠𝑠𝑠 is the effective parasitic capacitance of the pin (excluding trace width) while ℎ is the dielectric height.

Maximum achievable return loss can then be assumed to be calculated from the parallel 𝑍𝑍𝐿𝐿 between the stray capacitance from the pin and an ideal 50 Ω termination, while 𝑍𝑍𝑆𝑆 is assumed to be 50 Ω (line impedance):

𝑅𝑅𝑅𝑅𝑚𝑚𝑠𝑠𝑚𝑚 = −20 log10 𝑍𝑍𝐿𝐿−𝑍𝑍𝑆𝑆𝑍𝑍𝐿𝐿+𝑍𝑍𝑆𝑆

;

Consider stray capacitance of SMT pins in the trace design and define the proper stack-up accordingly to minimize its effect.

15 The equation is valid for a strip line; micro strip lines exhibit a slightly lower loss due to lower time delay.



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2.2.2 Antenna design Designers must take care of the antennas from all perspectives at the very start of the design phase when the physical dimensions of the application board are under analysis/decision since the RF compliance of the device integrating THEO-P173 module with all the applicable required certification schemes heavily depends on the radiating performance of the antennas. The designer is encouraged to consider one of the antennas listed in the THEO-P173 Data sheet [1].

• External antennas such as linear dipole:

o External antennas basically do not imply physical restriction to the design of the PCB where the module is mounted.

o The radiation performance mainly depends on the antennas. It is required to select antennas with optimal radiating performance in the operating bands.

o RF cables should be carefully selected with minimum insertion losses. Additional insertion loss will be introduced by low quality or long cable. Large insertion loss reduces radiation performance.

o A high quality 50 Ω coaxial connector provides proper PCB-to-RF cable transition.

• Integrated antennas such as patch-like antennas:

o Internal integrated antennas imply physical restriction to the PCB design:

Integrated antennas excite RF current on its counterpoise, typically the PCB ground plane of the device that becomes part of the antenna; its dimension defines the minimum frequency that can be radiated. Therefore, the ground plane can be reduced down to a minimum size that should be similar to the quarter of the wavelength of the minimum frequency that has to be radiated, given that the orientation of the ground plane related to the antenna element must be considered.

The RF isolation between antennas in the system has to be as high as possible and the correlation between the 3D radiation patterns of the two antennas has to be as low as possible. In general, an RF separation of at least a quarter wavelength between the two antennas is required to achieve a minimum isolation and low pattern correlation; increased separation should be considered if possible, to maximize the performance and fulfil the requirements in Table 12.

The one below is a numerical example to estimate the physical restriction on a PCB:

Frequency = 6 GHz Wavelength = 5 cm Quarter wavelength = 1.25 cm16

o Radiation performance depends on the whole product and antenna system design, including product mechanical design and usage. Antennas should be selected with optimal radiating performance in the operating bands according to the mechanical specifications of the PCB and the whole product.

Table 11 summarizes the requirements for the antenna RF interface while Table 12 specifies additional requirements for dual antenna design implementation.

16 Wavelength referred to a signal propagating over the air.



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Item Requirements Remarks

Impedance 50 Ω nominal characteristic impedance

The impedance of the antenna RF connection must match the 50 Ω impedance of the ANT pin.

Frequency Range 5850 - 5925 MHz For 802.11p.

Return Loss S11 < -13 dB (VSWR < 1.5:1) Abs. Max. The Return loss or the S11, as the VSWR, refers to the amount of reflected power, measuring how well the primary antenna RF connection matches the 50 Ω characteristic impedance of the RF5G_ANTx pin. The impedance of the antenna termination must match as much as possible the 50 Ω nominal impedance of the RF5G_ANTx pin over the operating frequency range thus, maximizing the amount of the power transferred to the antenna.

Efficiency > -1.5 dB ( > 70% ) recommended > -3.0 dB ( > 50% ) acceptable

The radiation efficiency is the ratio of the radiated power to the power delivered to the antenna input. The efficiency is a measure of how well an antenna receives or transmits.

Table 11: Summary of antenna interface requirements

Item Requirements Remarks

Isolation (in-band)

|S21| > 50 dB recommended |S21| > 43 dB minimum

The antenna to antenna isolation is the loss between the primary and the secondary antenna; high isolation results from low coupled antennas.

Isolation (out-of-band)

|S21| > 35 dB recommended |S21| > 30 dB acceptable

Out-of-band isolation is evaluated in the band of the aggressor to ensure that the transmitting signal from the other radio is sufficiently attenuated by the receiving antenna to avoid saturation and intermodulation effects at the receiver’s port.

Table 12: Summary of antenna isolation requirements

In both the cases, while selecting external or internal antennas, the following recommendations should be observed:

• Select antennas that provide optimal return loss (or VSWR) figure over all the operating frequencies. • Select antennas that provide optimal efficiency figure over all the operating frequencies. • Select antennas that provide appropriate gain not to exceed the regulatory limits specified in some

countries such as by FCC in the United States, as mentioned in section 5.

2.2.2.1 RF Connector Design

If an external antenna is required, the designer should consider using a proper RF connector. While different types of connector and cable assembly are available, the designer should select the best one that is suited to the application. The key characteristics are:

• RF connector type: Select U.FL, FAKRA or equivalent series

• Nominal impedance: 50 Ω

• Minimum frequency rating: 6 GHz

Consider that SMT connectors may be rated for a limited number of insertion cycles (like the U.FL series).

Some of the series commonly used in RF applications are listed in Table 13. It is the responsibility of the designer to verify the compatibility between plugs and receptacles used in the design.

U.FL connector

The U.FL receptacle is available as an SMT part while the plug is provided as cable assembly. Table 13 suggests some RF connector series that can be used by the designers to connect RF coaxial cables to the PCB based on the declaration of the respective manufacturers. The Hirose U.FL-R-SMT RF receptacles (or similar parts) require a suitable mated RF plug from the same connector series. Due to wide usage of this connector, several manufacturers offer compatible equivalents.



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Manufacturer Series Remarks

Hirose U.FL® Ultra Small Surface Mount Coaxial Connector Recommended

I-PEX MHF® Micro Coaxial Connector

Tyco UMCC® Ultra-Miniature Coax Connector

Amphenol RF AMC® Amphenol Micro Coaxial

Lighthorse Technologies, Inc. IPX ultra micro-miniature RF connector

Table 13: U.FL compatible plug connector

The key characteristics are:

• Cable thickness: Typically from 0.8 mm to 1.37 mm. Select thicker cables to minimize insertion loss

• Cable length: Standard length is typically 100 mm or 200 mm; custom lengths may be available on request. Select shorter cables to minimize insertion loss.

• RF connector on the other side of the cable: For example, another U.FL (for board-to-board connection) or SMA (for panel mounting)

Consider that SMT connectors are typically rated for a limited number of insertion cycles. In addition, the RF coaxial cable may be relatively fragile compared to other types of cables. To increase application ruggedness, connect the U.FL connector to a more robust connector such as SMA fixed on panel or change the connector type.

FAKRA RF connector

The FAKRA jack is available either as an SMT or though hole part while the plug is provided as cable assembly. Table 14 lists some manufacturers of the FAKRA series connectors. This connector type is commonly used in applications where mechanical key and locking latch are required to guarantee correct assembly and to meet automotive standards like the USCAR 17 & 18 or ISO 20860-1 & 2. Similar considerations as specified in the U.FL connector section applies to the FAKRA RF connector as well.

Manufacturer Series Remarks

Molex FAKRA II SMB 6 GHz rating

Rosenberger FAKRA HF 6 GHz rating

Table 14: FAKRA compatible connector series

General recommendations

Strictly follow the connector manufacturer’s recommended layout to maintain 50 Ω controlled impedance on the RF path17. The following recommendations apply for proper layout of the connector:

• Strictly follow the connector manufacturer’s recommended layout. Some examples are provided below:

o SMA Pin-Through-Hole connectors require GND keep-out (that is, clearance, a void area) on all the layers around the central pin up to annular pins of the four GND posts.

o U.FL surface mounted connectors require no conductive traces (that is, clearance, a void area) in the area below the connector between the GND land pins.

• In case of connector’s RF pin size wider than the micro strip, remove the GND layer beneath the RF connector to minimize the stray capacitance thus keeping the RF line 50 Ω. For example, the active pin of the UF.L connector must have a GND keep-out (also called “void area”) at least on the first inner layer to reduce parasitic capacitance to ground.

2.2.2.2 Integrated antenna design

If integrated antennas are used, the transmission line is terminated by the antennas themselves. Follow the guidelines mentioned below:

17 This is especially important when choosing a connector close to its frequency rating, like the U.FL or FAKRA series (rated for use up to 6 GHz).



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• The antenna design process should start together with the mechanical design of the product. PCB mock-ups are useful in estimating overall efficiency and radiation path of the intended design during early development stages.

• Use antennas designed by an antenna manufacturer providing the best possible return loss (or VSWR).

• Provide a ground plane large enough according to the related integrated antenna requirements. The ground plane of the application PCB may be reduced down to a minimum size that must be similar to one quarter of wavelength of the minimum frequency that has to be radiated, though overall antenna efficiency may benefit from larger ground planes. Proper placement of the antenna and its surroundings is also critical for antenna performance. Avoid placing the antenna close to conductive or RF-absorbing parts such as metal objects or ferrite sheets as they may absorb part of the radiated power, shift the resonant frequency of the antenna or affect the antenna radiation pattern.

• Follow strictly the specific guidelines provided by the antenna manufacturer regarding correct installation and deployment of the antenna system, including PCB layout and matching circuitry.

• Further to the custom PCB and product restrictions, antennas may require tuning/matching to reach the target performance. It is recommended to plan measurement and validation activities with the antenna manufacturer before releasing the end-product to manufacturing.

• The receiver section may be affected by noise sources like hi-speed digital busses. Avoid placing the antenna close to busses such as DDR or consider taking specific countermeasures like metal shields or ferrite sheets to reduce the interference.

• Take care of interaction between co-located RF systems. Transmitted power on nearby bands may interact or disturb the performance of THEO-P173 module where specific coexisting countermeasures are not present.

2.3 Supply interfaces

2.3.1 Module supply design Though the GND pins are internally connected, it is recommended to connect all the available ground pins to solid ground on the application board as a good (low impedance) connection to external ground can minimize power loss and improve RF and thermal performance. The THEO-P173 module must be sourced through 5V0_PA1/5V0_PA2 and 3V3_DIG pins with proper DC power supplies that comply with the requirements summarized in Table 5.

Good connection of the module power supply pins with DC supply source is required for accurate RF performance and schematic guidelines are summarized below:

• All power supply pins must be connected to an appropriate DC source. • Any series component with Equivalent Series Resistance (ESR) greater than a few mΩ should be avoided.

Only exceptions to this rule are ferrite beads used for DC filtering, however those parts should be used carefully to avoid instability of the DC/DC supply powering the module and are in general not required.

• A minimum bulk capacitance of 100µF on each 5V0_PAx and 3V3_DIG rail is required close to the module to help filter current spikes from the RF section. The preferred choice is a ceramic capacitor with X7R or X5R dielectric due to low ESR/ESL. Special care should be taken in the selection of X5R/X7R dielectrics due to capacitance derating vs DC bias voltage.

• Additional bypass capacitors in the range of 100 nF to 1 µF on all supply pins are required for high frequency filtering. The preferred choice is a ceramic capacitor with X7R or X5R dielectric due to low ESR/ESL. Smaller size bypass capacitors should be chosen for the manufacturing process to minimize ESL.

2.3.1.1 Guidelines for VCC supply circuit design using a switching regulator

It is recommended to use a Switching Mode Power Supply (SMPS) when the difference from the available supply rail to the module’s rails allows significant power savings. For example, conversion of a 12 V or greater voltage supply to the nominal 3.3 V value for the 3V3_DIG supply.



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The characteristics of the SMPS connected to the supply pins should meet the following prerequisites to comply with the module requirements summarized in Table 5.

• Power capability: The switching regulator together with any additional filter in front of the module must be capable of providing a voltage value within the specified operating range, and must be capable of delivering the specified peak current.

• Low output ripple: The switching regulator must be capable of providing a peak-to-peak Voltage ripple within the specified limits. This requirement applies both to voltage ripple generated by SMPS operating frequency and to high frequency noise generated by power switching.

• PWM/PFM mode operation: It is preferable to select regulators with fixed Pulse Width Modulation (PWM) mode. Pulse Frequency Modulation (PFM) mode typically exhibits higher ripple and may affect RF performance. If power consumption is not a concern, PFM/PWM mode transitions should be avoided in favor of fixed PWM operation to reduce the peak-to-peak noise on voltage rails. Switching regulators with mixed PWM/PFM mode can be used provided that the PFM/PWM modes and transition between modes complies with the requirements.

2.3.1.2 Guidelines for supply circuit design using a Low Drop-Out (LDO) linear regulator

The use of a linear regulator is suggested when the difference from the available supply rail and the 5V0_PAx or 3V3_DIG value is relatively low. The linear regulators provide acceptable efficiency when transforming a supply of less than 5 V to a voltage value within the normal operating range of the module.

The characteristics of the Low Drop-Out (LDO) linear regulator used to power the voltage rails must meet the following prerequisites to comply with the requirements summarized in Table 5.

• Power capabilities: The LDO linear regulator with its output circuit must be capable of providing a voltage value to the supply pins of the module within the specified operating range and must be capable of withstanding and delivering the maximum specified peak current while in connected-mode.

• Power dissipation: The power handling capability of the LDO linear regulator must be checked to limit its junction temperature to the rated operating range. The worst-case junction temperature can be estimated as shown below:

𝑇𝑇𝑗𝑗,𝑒𝑒𝑠𝑠𝑠𝑠 = (𝑉𝑉𝑖𝑖𝑖𝑖 − 𝑉𝑉𝑜𝑜𝑜𝑜𝑠𝑠) ∗ 𝐼𝐼𝑠𝑠𝑎𝑎𝑎𝑎 ∗ 𝜋𝜋𝑗𝑗𝑠𝑠 + 𝑇𝑇𝑠𝑠

Where: 𝜋𝜋𝑗𝑗𝑠𝑠 is the junction-to-ambient thermal resistance of the LDO’s package18, 𝐼𝐼𝑠𝑠𝑎𝑎𝑎𝑎 is the current consumption of the given voltage rail in continuous TX/RX mode and 𝑇𝑇𝑠𝑠 is the maximum operating temperature of the end product inside the housing.

2.4 Data communication interfaces

2.4.1 USB 2.0 The USB bus of THEO-P173 supports Hi-Speed connectivity with a transfer rate of 480 Mb/s. USB differential data pair is a controlled impedance bus and the main parameters considered for the track impedance calculation are depicted in Figure 9.

Figure 9: USB differential pair, controlled impedance parameters

18 Thermal dissipation capability reported on datasheet is usually tested on a reference board with adequate copper area (ref. to JESD51 [12]). Junction temperature on a typical PCB may be higher than the estimated value due to the limited space to dissipate the heat. Thermal reliefs on pads also affect the capability of a device to dissipate the heat.



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The USB data lines must follow the recommendations stated in Table 15 to guarantee bus signal integrity and to avoid EMI issues.

Signal Group Parameter Min. Typ. Max. Unit

USB differential data Single Ended impedance, 𝑍𝑍𝑆𝑆𝑆𝑆 45 Ω

Differential impedance, 𝑍𝑍𝑑𝑑𝑖𝑖𝑑𝑑𝑑𝑑 90 Ω

Common mode impedance, 𝑍𝑍𝐶𝐶𝐶𝐶 30 Ω

Impedance control, 𝑍𝑍𝑆𝑆𝑆𝑆, 𝑍𝑍𝑑𝑑𝑖𝑖𝑑𝑑𝑑𝑑, 𝑍𝑍𝐶𝐶𝐶𝐶 𝑍𝑍0 − 10% 𝑍𝑍0 𝑍𝑍0 + 10%

Series termination resistors Not recommended

Bus skew length mismatch between differential pair 0 1519 mm

Isolation to other signals 4 w

Table 15: USB bus requirements

If the USB data link is routed on a connector, the designer is encouraged to consider including a common mode choke and ESD protections on USB power and data lines while complying with the recommended power sequence for USB_VBUS. Common mode chokes should be considered only in case of EMI issues as they can introduce signal degradation. More details about proper selection of ESD protections can be found in section 2.9.

2.4.2 SPI The SPI pins should be routed by applying enough clearance from RF and other data communication interfaces to reduce cross talk. A minimum 3W clearance from those signals is required in case of parallel routing for long distances. For more information, refer to section 2.6.

All pins have internal keeper resistors; leave it open if not used.

2.5 Other interfaces and notes Control pins should be routed applying enough clearance from RF and data communication interfaces to reduce cross talk. A minimum 3W clearance from those signals is required in case of parallel routing for long distances. For more information, refer to section 2.6).

All pins have internal keeper resistors; leave it open if not used.

NC pins are reserved for future use and must be left unconnected.

2.6 General high speed layout guidelines These general design guidelines are considered as best practices and are valid for any bus present in the THEO-P173 module; the designer should prioritize the layout of higher speed busses. Low frequency signals are in general not critical for layout.

One exception is represented by High Impedance traces (such as signals driven by weak pull-resistor) that may be affected by crosstalk. For those traces, a supplementary isolation of 4w20 from high frequency busses is recommended.

2.6.1 General considerations for schematic design and PCB floor-planning • Verify which signal bus requires termination and add series resistor terminations to the schematics. • Carefully consider the placement of the module with respect to antenna position and Host processor; RF

trace length should be minimized first, followed by USB bus length. • USB bus routing should be planned to minimize layer-to-layer transition to a minimum. • Verify with PCB manufacturer allowable stack-ups and controlled impedance dimensioning for antenna

traces and busses.

19 Total mismatch includes skew introduced by cable and host side routing; keep it at minimum if the USB bus is routed on a connector. 20 ‘w’ refers to trace width and is used in general as a measurement unit to specify insulation requirements in crosstalk.



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• Verify that the power supply design and power sequence are compliant with THEO-P173 specification (refer to section 1.3).

2.6.2 Component placement • Accessory parts like bypass capacitors should be placed as close as possible to the module to improve

filtering capability, prioritizing the placement of the smallest size capacitor close to module pins. • Particular care should be taken not to place components close to the antenna area. The designer should

carefully follow the recommendations from the antenna manufacturer about the distance of the antenna vs. other parts of the system. The designer should also maximize the distance of the antenna to Hi-frequency busses like DDRs and related components or consider an optional metal shield to reduce interferences that could be picked up by the antenna thus reducing the module’s sensitivity.

2.6.3 Layout and manufacturing • Avoid stubs on high speed signals. Test points or component pads should be placed over the PCB trace. • Verify the recommended maximum signal skew for differential pairs and length matching of buses. • Minimize the routing length; longer traces will degrade signal performance. Ensure that maximum

allowable length for high speed busses is not exceeded. • Ensure to track your impedance matched traces. Consult early with your PCB manufacturer for proper

stack-up definition. • RF, analog and digital sections should have dedicated and clearly separated areas on the board. • No digital routing is allowed in the GND reference plane area of RF traces (ANT pin and Antenna). • Is strongly recommended to avoid digital routing beneath all layers of RF traces. • Ground cuts or separation is not allowed below the module. • Minimize the length of the RF traces as first priority. Then, minimize bus length to reduce potential EMI

issues from digital busses. • All traces (Including low speed or DC traces) must couple with a reference plane (GND or power), Hi-

speed busses should be referenced to the ground plane. In this case, if the designer needs to change the ground reference, an adequate number of GND vias must be added in the area of transition to provide a low impedance path between the two GND layers for the return current.

• Hi-Speed busses are not allowed to change reference plane. If a reference plane change is unavoidable, some capacitors should be added in the area to provide a low impedance return path through the different reference planes.

• Trace routing should keep a distance greater than 3w from the ground plane routing edge. • Power planes should keep a distance from the PCB edge sufficient to route a ground ring around the

PCB, the ground ring must then be connected to other layers through vias.

The heat dissipation during continuous transmission at maximum power can significantly raise the temperature of the application base-board below the THEO-P173 module. Avoid placing temperature sensitive devices close to the module and provide adequate grounding to transfer the generated heat to the PCB.

2.7 Module footprint and paste mask The module is a rectangular unit with dimensions of 40 mm x 30 mm and a height of approximately 3.85 mm.

Due to manufacturing tolerances, module alignment during SMT process should rely on metal pins and not on mechanical outline. Failing to fulfill this recommendation may result in poor production yield.

The THEO-P173 module outline and recommended footprint are shown in Figure 10.



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Figure 10: Recommended footprint for THEO-P173 module

The exact mask geometries, distances and stencil thicknesses must be adapted to the specific production processes of the customer.

Due to the module size and to improve the quality of soldering on the castellated pins, it is recommended to follow the paste mask and solder mask patterns specified in Figure 11 and Figure 12.

Figure 11: Paste mask design for NON-RF PADS (left) and RF PADS (right), dimensions are in mm



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Figure 12: Soldermask and Pastemask recommendations for THEO-P1 central pad

2.8 Thermal guidelines The THEO-P173 module has been successfully tested from -40 °C to +85 °C ambient temperature. The board will generate heat during high loads that must be dissipated to sustain the life time of the component.

The improvement of module’s thermal dissipation will decrease its internal temperature. This improves the long-term reliability of the device for applications operating at a high ambient temperature.

Heat generated on the THEO-P173 module is mainly transferred to the module's bottom side. Thus, the host PCB is required to offer enough ground plane area as heat-sink to lower the module temperature.

Use the hardware techniques mentioned below to reduce the Module-to-Ambient thermal resistance in customer’s applications:

• Connect each GND pin to a solid ground layer of the application board and connect each ground area on outer layers down to internal ground layers with multiple vias.

• Provide a ground plane as wide as possible on the application board and consider the SMD design for module’s pins.

• Maximize antenna’s return loss to reduce reflected RF power to the module. • Optimize the thermal design of any component that generates heat in the application, including linear

regulators and processor, to spread the generated heat distribution over the application device. • Properly design the mechanical enclosure of the application device to provide ventilation and good

thermal dissipation.



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• Provide a heat sink component attached to the module top side, with electrically insulated / high thermal conductivity adhesive, or on the backside of the application board, below the radio module.

2.9 ESD guidelines THEO-P173 module is manufactured through a highly automated process which complies with IEC61340-5-1 [9] (STM5.2-1999 Class M1 devices) standard. A manufacturing process on customer’s manufacturing site that implements a basic ESD control program is considered sufficient to guarantee the necessary precautions21 for handling the modules. The ESD ratings of THEO-P173 module pins are stated in Table 16.

Applicability Immunity level

All pins Human Body Model (HBM), ANSA/ESDA/JEDEC JS-001-201422. ±2000 V

Charged Device Model (CDM), JESD22-C101. ±450 V

RF5G_ANT1, RF5G_ANT2

EN 61000-4-2 level 4, contact discharge. ±8000 V

Table 16: ESD immunity rating for pins of THEO-P173 module

The designer must implement proper measures to protect from ESD events any pin that may be exposed to the end user in compliance with the following European regulations.

• ESD testing standard CENELEC EN 61000-4-2 [5] • Radio equipment standard ETSI EN 301 489-1 [6]

The minimum requirements as per these European regulations are summarized in Table 17.

Application Category Immunity Level

All exposed surfaces of the radio equipment and ancillary equipment in a representative configuration of the end product.

Contact Discharge 4 kV

Air Discharge 8 kV

Table 17: Minimum ESD immunity requirements based on EN 61000-4-2

Compliance with standard protection level specified in EN 61000-4-2 [5] can be achieved by including proper ESD protections in parallel to the line, close to areas accessible by the end user.

RF5G_ANT1 and RF5G_ANT2 pins include ESD protections in compliance with EN61000-4-2 Level 4; no further protection is required or recommended due to the signal degradation caused by any additional capacitance introduced on the transmission line.

21 Minimum ESD protection level for safe handling is specified in JEDEC JEP155 (HBM) and JEP157 (CDM), respectively ±500 V and ±250 V. 22 Compliant with AEC-Q100-002 Rev E requirements.



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2.10 Design-in checklist

2.10.1 Schematic checklist Module pins are properly numbered and designated on the schematic (including thermal pins). Power supply design complies with the specification. The power sequence (including M_RST_N signal handling in Open Drain mode) is properly

implemented. Adequate bypassing is present in front of each power pin. Each signal group is consistent with its own power rail supply or proper signal translation has been

provided. Configuration pins are properly set at bootstrap. Unused pins are properly terminated. A pi-filter is provided in front of each antenna for final matching. RF co-location additional filters have been considered in the design.

2.10.2 Layout checklist PCB stack-up and controlled impedance traces follow PCB manufacturer’s recommendation. All pins are properly connected and the package follows u-blox’s recommendations for pin design. Proper clearance has been provided between RF section and digital section. Proper isolation has been provided between Antennas (RF co-location, diversity or multi-antenna

design). Bypass capacitors are placed close to the module. Low impedance path to power sources has been provided to the module. Controlled impedance traces are properly implemented on the layout (both RF and digital) and follow

PCB manufacturer recommendations. 50 Ω RF traces and connectors follow the rules in section 2.2. Antenna design has been reviewed by the antenna manufacturer. Proper grounding has been provided to the module for low impedance return path and heat sink. Reference plane skipping has been minimized for high frequency busses. All traces and planes are routed inside the area defined by the main ground plane.


UBX-15029954 - R05 Software

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3 Software The THEO-P173 module requires firmware and a host-side driver to run. The firmware implements the 802.11p MAC and PHY layers on the module. The driver that is currently available for the Linux operating system, interfaces with the USB bus drivers, and provides the API for attaching the upper layers of the V2X stack.

The software package for THEO-P173 is provided as a virtual machine with a pre-installed SDK (Software Development Kit). A software package containing only the driver and firmware can be provided separately. Each software package contains the following:

• A firmware image that has to be downloaded to the module on system start and • A driver, which is placed between the bus driver and network layer of the V2X stack.

Various control tools are also included.

3.1 Software development kit The Software Development Kit is provided in a VMware virtual machine that runs on Linux OS (Ubuntu 14.04 LTS). The SDK contains the driver, firmware and low-level evaluation tools for operating the THEO-P173 module. This SDK is also referred to as the “LLC SDK”23, as the contained drivers and tools provide access to the module at the Logical Link Control (LLC) layer.

The LLC SDK serves as an environment for evaluation of the THEO-P173 module and can be used for the development and integration of upper layer V2X solutions on top of the provided LLC API. The driver and part of the tools are provided as source code and can be used as example implementations.

Refer to the EVK-THEO-P1 User Guide [2] for a description on how to use the LLC SDK and evaluation tools.

3.2 Software architecture overview An overview of the LLC software architecture is shown in Figure 13. The THEO-P173 module implements the 802.11p MAC and PHY layers. Firmware runs on the THEO-P173 module, which needs to be downloaded from the host to the module through USB after each power-on. The driver on the host communicates to the module through USB and provides the API between the upper network layer and the radio. For additional information regarding the specification of the LLCremote API, refer to [17].

23 The LLC SDK, including driver and firmware for the THEO-P173 module, is developed by Cohda Wireless and can be provided free of charge. A full SDK supporting IEEE 1609 and ETSI ITS software stacks can be obtained separately from Cohda Wireless.



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Figure 13: Overview of the LLC software architecture

The description of the main components is provided in Table 18.

Component Description Location in the LLC SDK

Firmware - Controls the baseband and radio modules - Implements the 802.11p MAC and PHY layers

~/x86/cohda/kernel/drivers/cohda/llc/SDRMK5Dual.bin

LLCremote driver

- Kernel device driver - Provides access to the THEO-P173 module through the USB

interface - Provides the LLCremote API and an interface to the user

space via the cw-llc network device

Sources: ~/x86/cohda/kernel/drivers/cohda/llc/ Kernel module: ~/x86/cohda/kernel/drivers/cohda/llc/cw-llc.ko

LLCremote API

- Interface between the network layer and the radio for o Configuring the radio o Sending and receiving of 802.11p data packets o Reading status and statistics o UTC time synchronization (timestamping of

received packets) o Debugging

LLC Lib - Provides the LLCremote API in user space Sources: ~/x86/cohda/app/llc/lib/

LLC tool - Wrapper for plugins Built Executable: ~/x86/cohda/app/llc/llc

LLC plugins - Small programs for accessing the radio, e.g. for o Configuration o Reading statistics o Sending and receiving packets

~/x86/cohda/app/llc/plugin/ Sources for chconfig, test-tx, test-rx plugins: ~/x86/cohda/app/llc/plugin/simtdapi/

Table 18: Description of the software components

Kernel space

THEO-P1(802.11p MAC+PHY)

LLCremote driver

(cw-llc.ko)

LLCremote API

IEEE 1609 / ETSI ITS stack

USB

User space

LLC Lib

LLCremote API

IEEE 1609 / ETSI ITS stack

LLC tool

...

cw-llc

Host

Firmware



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3.3 Compiling the LLC driver and tool

The LLC driver and tool can be provided as part of the LLC SDK or as a standalone package that contains an extract of the relevant files from the LLC SDK. The Makefiles for the LLC driver and application must be modified for the target platform.

First, run the LLC SDK virtual machine or extract the standalone software package. To compile the LLC driver, run the following commands, which will build the driver’s kernel module ‘cw-llc.ko’:

cd ~/x86/cohda/kernel/drivers/cohda/llc make

To compile the LLC tool and plugins, run the following commands:

cd ~/x86/cohda/app/llc make

This builds the LLC tool ‘llc’, the LLC library ‘libLLC.so’ and the LLC plugins24 below the plugin directory.

3.4 Loading the firmware After supplying power to the evaluation board and connecting the micro-USB to the PC, the THEO-P173 module enumerates itself on the USB as “NXP SAF510x DFU” device. The USB device ID (vendor/product ID) of the device is 1fc9:0102, which can be checked using the ‘lsusb’ command:

$ lsusb Bus 001 Device 003: ID 1fc9:0102 NXP Semiconductors […]

Next, use ‘dfu-util’ or a similar tool to download the firmware to the THEO-P173 module through USB via the Device Firmware Update (DFU) protocol:

sudo dfu-util -d 1fc9:0102 -R -D ~/x86/cohda/kernel/drivers/cohda/llc/SDRMK5Dual.bin

The output from the ‘dfu-util’ command should be as shown below:

dfu-util 0.5 (C) 2005-2008 by Weston Schmidt, Harald Welte and OpenMoko Inc. (C) 2010-2011 Tormod Volden (DfuSe support) This program is Free Software and has ABSOLUTELY NO WARRANTY dfu-util does currently only support DFU version 1.0 Filter on vendor = 0x1fc9 product = 0x0102 Opening DFU USB device... ID 1fc9:0102 Deducing device DFU version from functional descriptor length Run-time device DFU version 0100 Claiming USB DFU Runtime Interface... Determining device status: state = dfuIDLE, status = 0 WARNING: Runtime device already in DFU state ?!?

24 LLC Plugins for channel configuration, sending, and receiving packets are provided as source code. Other plugins are provided as binary only.



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Found Runtime: [1fc9:0102] devnum=0, cfg=1, intf=0, alt=0, name="UNDEFINED" Claiming USB DFU Interface... Setting Alternate Setting #0 ... Determining device status: state = dfuIDLE, status = 0 dfuIDLE, continuing Deducing device DFU version from functional descriptor length DFU mode device DFU version 0100 Device returned transfer size 4096 No valid DFU suffix signature Warning: File has no DFU suffix bytes_per_hash=8534 Copying data from PC to DFU device Starting download: [##################################################] finished! state(8) = dfuMANIFEST-WAIT-RESET, status(0) = No error condition is present Done! can't detach Resetting USB to switch back to runtime mode

After this, the USB mode of the THEO-P173 module will switch over to a normal USB communication device “MK5 SDR 802.11p RADIO” with the USB device ID 1fc9:0103. The ‘lsusb’ command can be used to check for the new USB device:

Bus 001 Device 004: ID 1fc9:0103 NXP Semiconductors […]

The output of the ‘dmesg’ command for the firmware download procedure is provided below.

usb 1-1: new high-speed USB device number 3 using ehci-pci usb 1-1: New USB device found, idVendor=1fc9, idProduct=0102 usb 1-1: New USB device strings: Mfr=1, Product=3, SerialNumber=0 usb 1-1: Product: NXP SAF510x (DFU Mode) usb 1-1: Manufacturer: NXP Semiconductors usb 1-1: reset high-speed USB device number 3 using ehci-pci usb 1-1: USB disconnect, device number 3 usb 1-1: new high-speed USB device number 4 using ehci-pci usb 1-1: New USB device found, idVendor=1fc9, idProduct=0103 usb 1-1: New USB device strings: Mfr=1, Product=3, SerialNumber=0 usb 1-1: Product: MK5 SDR 802.11p RADIO - High Speed usb 1-1: Manufacturer: CohdaWireless Pty Ltd

3.5 Loading the LLC driver To load the LLC driver, simply insert the kernel module and enable the ‘cw-llc’ network interface:

sudo insmod ~/x86/cohda/kernel/drivers/cohda/llc/cw-llc.ko sudo ip link set cw-llc up


UBX-15029954 - R05 Handling and soldering

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4 Handling and soldering

4.1 Packaging, shipping, storage and moisture preconditioning The THEO-P173 module is delivered in a standard 40 mm x 40 mm tray. Small ESD foam is placed at the tray to prevent the module from movement during shipping and transportation.

For information pertaining to reels, tapes or trays, moisture sensitivity levels (MSL), shipment and storage, and drying for preconditioning refer to THEO-P173 Data sheet [1] and u-blox Package Information Guide [3].

4.2 ESD handling precautions

THEO-P173 modules are Electrostatic Sensitive Devices (ESD). Observe precautions for handling! Failure to observe these precautions can result in severe damage to the module!

Wireless transceivers are Electrostatic Sensitive Devices (ESD) and require special precautions when handling. Particular care must be exercised when handling patch antennas, due to the risk of electrostatic charges. In addition to standard ESD safety practices, the following measures should be taken into account whenever handling the receiver:

• Unless there is a galvanic coupling between the local GND (i.e. the work table) and the PCB GND, then the first point of contact when handling the PCB must always be between the local GND and PCB GND.

• Before mounting an antenna patch, connect ground of the device

• When handling the RF pin, do not come into contact with any charged capacitors and be careful when contacting materials that can develop charges (e.g. patch antenna ~10 pF, coax cable ~50-80 pF/m, soldering iron, …)

• To prevent electrostatic discharge through the RF input, do not touch any exposed antenna area. If there is any risk that such exposed antenna area is touched in non ESD protected work area, implement proper ESD protection measures in the design.

• When soldering RF connectors and patch antennas to the receiver’s RF pin, make sure to use an ESD safe soldering iron (tip).

4.3 Reflow soldering process The devices are surface mount modules supplied on a multi-layer FR4-type PCB with gold plated connection pins and produced in a lead-free process with a lead-free soldering paste. The bow and twist of the PCB is maximum 0.75% according to IPC-A-610E. The thickness of solder resist between the host PCB top side and the THEO-P173 module bottom side must be considered for the soldering process.

The module is compatible with industrial reflow profile for RoHS solders. Use of "No Clean" soldering paste is strongly recommended.



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The reflow profile used is dependent on the thermal mass of the entire populated PCB, heat transfer efficiency of the oven and particular type of solder paste used. The optimal soldering profile used is dependent on specific process and PCB layout thus has to be trimmed for each case.

Process parameter Unit Target

Pre-heat Ramp up rate to TSMIN K/s 3

TSMIN °C 150

TSMAX °C 200

tS (from 25 °C) s 150

tS (Pre-heat) s 110

Peak TL °C 217

tL (time above TL) s 90

TP (absolute max) °C 245

tP (time above TP -5 °C) s 30

Cooling Ramp-down from TL K/s 6

General Tto peak s 300

Allowed soldering cycles - 1

Table 19: Recommended reflow profile

Figure 14: Reflow profile

Lower value of TP and slower ramp down rate (2 - 3 °C/sec) is preferred.

After reflow soldering, optical inspection of the modules is recommended to verify proper alignment.

Target values in Table 19 should be taken as general guidelines for a Pb-free process, refer to JEDEC J-STD-020C [10] standard for further information.

4.3.1 Cleaning

Cleaning the modules is not recommended. Residues underneath the modules cannot be easily removed with a washing process.



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• Cleaning with water will lead to capillary effects where water is absorbed in the gap between the baseboard and the module. The combination of residues of soldering flux and encapsulated water leads to short circuits or resistor-like interconnections between neighboring pins. Water will also damage the sticker and the ink-jet printed text.

• Cleaning with alcohol or other organic solvents can result in soldering flux residues flooding into the two housings, areas that are not accessible for post-wash inspections. The solvent will also damage the sticker and the ink-jet printed text.

• Ultrasonic cleaning will permanently damage the module, in particular the crystal oscillators.

For best results use a "no clean" soldering paste and eliminate the cleaning step after the soldering process.

4.3.2 Other remarks • Only a single reflow soldering process is allowed for boards with a module populated on it. • Boards with combined through-hole technology (THT) components and surface-mount technology

(SMT) devices may require wave soldering to solder the THT components. Only a single wave soldering process is allowed for boards populated with the modules. Miniature Wave Selective Solder process is preferred over traditional wave soldering process.

• Hand soldering is not recommended. • Rework is not recommended. • Conformal coating may affect the performance of the module; hence, it is important to prevent the

liquid from flowing into the module. The RF shields do not provide protection for the module from coating liquids with low viscosity; therefore care is required while applying the coating. Conformal coating of the module will void the warranty.

• Grounding metal covers: Attempts to improve grounding by soldering ground cables, wick or other forms of metal strips directly onto the EMI covers is done at the customer's own risk and will void module’s warranty. The numerous ground pins are adequate to provide optimal immunity to interferences.

• The module contains components that are sensitive to Ultrasonic Waves. Use of any ultrasonic processes (cleaning, welding etc.) may damage the module. Use of ultrasonic processes on an end product integrating this module will void the warranty.


UBX-15029954 - R05 Regulatory compliance

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5 Regulatory compliance Information about regulatory compliance is provided in the THEO-P173 Data Sheet [1].


UBX-15029954 - R05 Product testing

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6 Product testing

6.1 OEM manufacturer production test The OEM manufacturer should focus on:

• Module assembly on the device; it should be verified that: o Soldering and handling process did not damage the module components o All module pins are well soldered on device board o There are no short circuits between pins

• Component assembly on the device; it should be verified that: o Communication with host controller can be established o The interfaces between module and device are working o Overall RF performance test of the device including antenna

Dedicated tests can be implemented to check the device. For example, the measurement of module current consumption when set in a specified state can detect a short circuit if compared with a “Golden Device” result.

The standard operational module firmware and test software on the host can be used to perform functional tests (communication with a Golden Device, check interfaces) and to perform basic RF performance tests. In addition, a special manufacturing firmware can be used to perform more advanced RF performance tests. See the following sections for details.

6.1.1 “Go/No go” tests for integrated devices A “Go/No go” test is typically to compare the signal quality with a “Golden Device” in a location with known signal quality. This test can be performed using a golden device as reference equipment to verify transmitted power and received sensitivity through RSSI information. In this configuration, an attenuator of at least 50 dB between the two devices is required to prevent receiver saturation.

This test is illustrated in Figure 15. The antennas, ANT1 and ANT2 of the DUT are connected to a splitter through a >50 dB attenuator and then to the Golden Device used as a reference. A fixed amount of packets will be transmitted from each side to test transmit power level and sensitivity on both the antennas of the DUT. The simulated wireless environment is static and known, and the RSSI results can be correlated to the transmitted and received power.

Figure 15 illustrates an exemplary test setup for such a basic RF functional test.



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Figure 15: Loopback setup with RF shielded box and standard devices for Go/No-Go test

6.1.2 RF functional tests The overall RF functional test of the device including the antenna can be performed with basic instruments such as a spectrum analyzer (or an RF power meter) and a signal generator with the help of the delivered toolset such as continuous wave and duty cycles. The utility allows setting the module into Rx or Tx test modes and perform tests to determine the RF performance such as:

• Transmit in a specified channel and power level in all supported rates and bands to measure output power

• Receive in a specified channel to verify sensitivity

See the THEO-P1 Radio Test Guide for description of the provided toolset and a detailed guide of its usage.

This feature allows the measurement of the transmitter and receiver power levels to check component assembly related to the module antenna interface and to check other device interfaces from which depends the RF performance.

To avoid damage to the module during transmitter test, a proper antenna according to module specifications or a 50 Ω termination must be connected to RF ports.

To avoid damage to the module during receiver test, the maximum power level received at RF ports must meet the module specifications and proper attenuators should be included in series to the transmission lines of THEO-P173 module.



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Figure 16: Setup with spectrum analyzer or power meter and signal generator for radiated measurements


UBX-15029954 - R05 Appendix A: Glossary

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Appendix A: Glossary Name Definition

API Application Programming Interface

CS Chip select

DC Direct Current

DSRC Dedicated Short-Range Communications

ESD Electrostatic Sensitive Devices

ETSI European Telecommunications Standards Institute

FCC Federal Communications Commission

GND Ground

GPIO General Purpose Input/Output

IEEE Institute of Electrical and Electronics Engineers

ITS Intelligent Transport Systems

LDO Low Drop Out

LLC Logical Link Control

MAC Media Access Control

OEM Original equipment manufacturer

OS Operating System

PCB Printed Circuit Board

PER Packet error rate

RF Radio Frequency

RoHS Restriction of Hazardous Substances

USB Universal Serial Bus

UTC Coordinated Universal Time

VCC IC power-supply pin

VIO Input offset voltage

V2X Vehicle-to-Everything

Table 20: Explanation of abbreviations used


UBX-15029954 - R05 Related documents

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Related documents [1] u-blox THEO-P173 Data sheet, Docu. No. UBX-15023940

[2] u-blox EVK-THEO-P1 User Guide, Docu. No. UBX-15013939

[3] u-blox Package Information Guide, Docu. No. UBX-14001652

[4] Universal Serial Bus Specification, Rev. 2.0, Apr 27, 2000

[5] IEC EN 61000-4-2 - Electromagnetic compatibility (EMC) - Part 4-2: Testing and measurement techniques - Electrostatic discharge immunity test.

[6] ETSI EN 301 489-1 - Electromagnetic compatibility and Radio spectrum Matters (ERM); Electro-Magnetic Compatibility (EMC) standard for radio equipment and services; Part 1: Common technical requirements.

[7] ETSI ES 202 663 v1.1.0 (2009-11) - Intelligent Transport Systems (ITS); European profile standard for the physical and medium access control layer of Intelligent Transport Systems operating in the 5 GHz frequency band.

[8] IEEE SA 1609.0-2013 - IEEE Guide for Wireless Access in Vehicular Environments (WAVE) – Architecture.

[9] IEC61340-5-1 - Protection of electronic devices from electrostatic phenomena – General requirements.

[10] JEDEC J-STD-020C - Moisture/Reflow Sensitivity Classification for Non-hermetic Solid State Surface Mount Devices.

[11] ETSI EN 60950-1:2006 - Information technology equipment – Safety – Part 1: General requirements.

[12] FCC Regulatory Information, Title 47 – Telecommunication.

[13] FCC Regulatory Information, Title 47 – Telecommunication, section 90.377.

[14] FCC Regulatory Information, Title 47 – Telecommunication, section 95.1509.

[15] ETSI TS 102 636-4-2 V1.1.1 (2013-10) - Intelligent Transport Systems (ITS); Vehicular Communications; Geo-Networking; Part 4: Geographical addressing and forwarding for point-to-point and point-to-multipoint communications; Sub-part 2: Media-dependent functionalities for ITS-G5.

[16] ETSI EN 302 571 v1.2.1 (2013-09) - Intelligent Transport Systems (ITS); Radio communications equipment operating in the 5 855 MHz to 5 925 MHz frequency band; Harmonized EN covering the essential requirements of article 3.2 of the R&TTE Directive.

[17] CohdaMobility MKx Radio LLCremote API Specification, CWD-MKx-0208

For regular updates to u-blox documentation and to receive product change notifications, register on our homepage (http://www.u-blox.com).

Revision history Revision Date Name Comments

R01 10-Feb-2016 sbia, kgom Initial release.

R02 22-Apr-2016 sbia Added reference circuit in the power sequence section for VBUS (Figure 3). Updated noise tolerance table with measured values (Table 5). Simplified ESD section; included manufacturing ratings (section 2.9).

R03 18-Jul-2016 sbia Added integration support for THEO-P173-02A (sections 1.3.2, 1.4.3, and 1.5.2). Removed loopback test from section 6.1.1 as it is not supported by the current firmware.

R04 25-Nov-2016 este Changed the product name as “THEO-P173” and the product grade as Professional. Modified Table 1.

R05 26-Jul-2017 sbia, mzes Included recommendations for paste mask and solder mask in section 2.7. Updated section 1.3.2. Replaced Document status with Disclosure restriction on page 2.

https://en.wikipedia.org/wiki/IEC_EN_61000-4-2

http://www.u-blox.ch/


UBX-15029954 - R05 Contact

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Contact For complete contact information visit us at www.u-blox.com.

u-blox Offices

North, Central and South America

u-blox America, Inc.

Phone: +1 703 483 3180 E-mail: [email protected]

Regional Office West Coast:


Technical Support:


Headquarters Europe, Middle East, Africa

u-blox AG

Phone: +41 44 722 74 44 E-mail: [email protected] Support: [email protected]

Asia, Australia, Pacific

u-blox Singapore Pte. Ltd.

Phone: +65 6734 3811 E-mail: [email protected] Support: [email protected]

Regional Office Australia: Phone: +61 2 8448 2016 E-mail: [email protected] Support: [email protected]

Regional Office China (Beijing):

Phone: +86 10 68 133 545 E-mail: [email protected] Support: [email protected]

Regional Office China (Chongqing):

Phone: +86 23 6815 1588 E-mail: [email protected] Support: [email protected]

Regional Office China (Shanghai):


Regional Office China (Shenzhen):


Regional Office India:


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Regional Office Taiwan:


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