High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach...

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High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date: Januar 2010 Part B - Final Presentation

Transcript of High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach...

Page 1: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

High Speed Digital Design ProjectHigh Speed Digital Design Project

SpaceWire RouterSpaceWire Router

Student: Asaf Bercovich

Instructor: Mony Orbach

Semester: Winter 2009/2010

2-Semester Project

Date: Januar 2010

Part B - Final Presentation

Page 2: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Project GoalProject Goal• Designing a SpaceWire Switch Core (Router)

compatible to ECSS-E-50-12A standard with the “Path Addressing” routing scheme.

• Designing a SpaceWire Switch Core (Router) compatible to ECSS-E-50-12A standard with the “Path Addressing” routing scheme.

Project ResultsProject Results• D1117_SPWPort – SpaceWire Network Device• D1117_SPWRepeater – SpaceWire Network Repeater• D1117_SPWRouter – SpaceWire Router

• D1117_SPWPort – SpaceWire Network Device• D1117_SPWRepeater – SpaceWire Network Repeater• D1117_SPWRouter – SpaceWire Router

Page 3: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

System TopologySystem Topology

SpaceWire RouterSpaceWire Router

Page 4: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

System TopologySystem Topology

D1117_SPWRouterD1117_SPWRouter

PORT

• Low latency

• Point-to-point

• Wormhole Routing

• Asynchronous communication

• Path Addressing

• 100 Mb/s of Total Traffic.

Page 5: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Layer 2 (Character Level) Network Port

ReceiverReceiver

D1117 SpaceWire PortD1117 SpaceWire PortArchitectureArchitecture

Port Controller

Port Controller

DinDin

SinSin

DoutDout

SoutSout

Sys ClockSys Clock

ResetReset

RX DATA / ControlRX DATA / Control

TX DATA / ControlTX DATA / Control

Link Start Link Start

State MachineState Machine

TransmitterTransmitter

FIFOFIFORX CLOCKRX CLOCK

FIFOFIFO

WriteWrite

ReadyReady

ReadyReady

ReadRead

ReadRead

ReadyReady

ReadyReady

WriteWrite

Link ReadyLink Ready

Tx ClockTx Clock

Page 6: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

System TopologySystem Topology

D1117_SPWRouterD1117_SPWRouter

PORT

• Low latency

• Point-to-point

• Wormhole Routing

• Asynchronous communication

• Path Addressing

• 100 Mb/s of Total Traffic.

Page 7: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

SpaceWire Packet FormatSpaceWire Packet Format

<DESTINATION<<CARGO<<END OF PACKET<

SpaceWire Packet

A SpaceWire ‘Routing Switch’ shall transfer packets from the input port of the switch where the packet arrives, to a particular output port determined by the packet destination address.

SpaceWire ‘Routing Switch’SpaceWire ‘Routing Switch’

Page 8: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Routing with Path-AddressingRouting with Path-Addressing

4 3 2 Cargo EOP 4 3 2 Cargo EOP

Page 9: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Layer 2 RepeaterLayer 2 Repeater

SP

W P

ort-0

Re

ad

Inte

rfac

eRX_EMPTY

READ_EN

RX_CONTROL

RX_DATASP

W P

ort

-1

Wri

te I

nte

rfa

ce TX_FULL

TX_WRITE

TX_CONTROL

TX_DATA

SpaceWire Connection Broker

Spa

ceWire signa

ls

Spa

ceWire signa

ls

D1117_SPWRepeater

ENABLE

Page 10: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Router ArchitectureRouter Architecture

Re

ad

Inte

rfac

e

Read Interface S

paceWire M

ux

SP

W P

ort-0

Re

ad

Inte

rfac

e

RX_EMPTY

READ_EN

RX_CONTROL

RX_DATA

SP

W P

ort-1

Re

ad

Inte

rfac

e

RX_EMPTY

READ_EN

RX_CONTROL

RX_DATA

SP

W P

ort-2

Re

ad

Inte

rfac

e

RX_EMPTY

READ_EN

RX_CONTROL

RX_DATA

SP

W P

ort

-0

Wri

te I

nte

rfa

ce TX_FULL

TX_WRITE

TX_CONTROL

TX_DATA

SP

W P

ort

-1

Wri

te I

nte

rfa

ce TX_FULL

TX_WRITE

TX_CONTROL

TX_DATA

SP

W P

ort

-2

Wri

te I

nte

rfa

ce TX_FULL

TX_WRITE

TX_CONTROL

TX_DATA

Wri

te I

nte

rfa

ce

Writ

e In

terf

ace

Spa

ceW

ire M

ux

RX_EMPTY

READ_EN

RX_CONTROL

RX_DATA

TX_FULL

TX_WRITE`

TX_CONTROL

TX_DATA

SpaceWire Connection Broker

Source Address Register

SpaceWire Router Control

HE

AD

ER

_D

EL

ET

ION

EN

_D

ES

T_

AD

DR

_R

EG

IST

ER

REGISTERED_SOURCE_ADDR

Packet Detection

Unit

Destination Address Register

REGISTERED_DEST_ADDR

SYSTEM_CLOCK

EN

_S

OU

RC

E_

AD

DR

_R

EG

IST

ER

EOP Detection

Unit

EN

_P

AC

KE

T_D

EL

IVE

RY

PACKET_DETECTEDEOP_DETECTED

Page 11: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Router ControllerRouter Controller

PACKET_DETECTED=1EOP_DETECTED=1

“CONFIGURESOURCEADDRESS”

EN_SRC_ADDR_REGISTER = 1 All other controller output signals are zero.

“CONFIGUREDESTINATION

ADDRESS”

EN_DEST_ADDR_REGISTER = 1HEADER_DELETION = 1

All other controller output signals are zero.

“WAIT FOR EOP/EEP”

EN_PACKET_DELIVERY = 1All other controller output signals are zero.

“IDLE”

All controller output signals are zero.

“RESET”

SPW PORT RESET = 1All other controller output signals are zero.

Page 12: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Hardware in testHardware in test

• GR-RASTA running D1117_SPWRouteras SpaceWire router.

• Gaisler GRESB – Gaisler Ethernet Bridge.(To be explained.)

• 3 PCs as SpacWire stations connected to one D1117 SpaceWire Router. Together they form a SpaceWire network based on ‘Path Addressing’ routing.

• GR-RASTA running D1117_SPWRouteras SpaceWire router.

• Gaisler GRESB – Gaisler Ethernet Bridge.(To be explained.)

• 3 PCs as SpacWire stations connected to one D1117 SpaceWire Router. Together they form a SpaceWire network based on ‘Path Addressing’ routing.

Page 13: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Software in testSoftware in test

• TCP Test Tool 2.3 Freeware.www.SimpleComTools.com

• TCP Test Tool 2.3 Freeware.www.SimpleComTools.com

Page 14: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Main Test TopologyMain Test Topology

Core : D1117 SpaceWire RouterFPGA : GR-RASTA

SPW-0 SPW-1 SPW-2

Logic LinkPC-0

OS: WindowsPC-1

OS: WindowsPC-2

OS: Windows

Page 15: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Main Test TopologyMain Test Topology

Core : D1117 SpaceWire RouterFPGA : GR-RASTA

SPW-0 SPW-1 SPW-2

PC-0OS: Windows

PC-1OS: Windows

PC-2OS: Windows

Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2

Ethernet

Ethernet

SpaceW

ire

Page 16: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

SpaceWire Ethernet BridgeSpaceWire Ethernet Bridge

Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2

EthernetSPW Physical Port Ethernet/IPv4/TCP - Transmit

Ethernet/IPv4/TCP - Receive

#0 SPW-0 2000 2001

#1 SPW-1 3000 3001

#2 SPW-2 4000 4001

Page 17: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Main Test TopologyMain Test Topology

Core : D1117 SpaceWire RouterFPGA : GR-RASTA

SPW-0 SPW-1 SPW-2

PC-0OS: Windows

PC-1OS: Windows

PC-2OS: Windows

Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2

Ethernet

Ethernet

SpaceW

ire

Page 18: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

PC-0PC-0

Path Address Destination Address

Cargo

TCP Message Header specifying transmission of a SpaceWire packet the size of 6 bytes.

IP Address of GRESB on the IP network.

The TCP Listening Socket on the GRESB.

2000 TCP port corresponds for transmission on SpaceWire port 0.

Send button for dispatching the TCP Message to GRESB

Page 19: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Main Test TopologyMain Test Topology

Core : D1117 SpaceWire RouterFPGA : GR-RASTA

SPW-0 SPW-1 SPW-2

PC-0OS: Windows

PC-1OS: Windows

PC-2OS: Windows

Gaisler SpaceWire Ethernet BridgeSPW-0 SPW-1 SPW-2

Ethernet

Ethernet

SpaceW

ire

Page 20: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

PC-1PC-1

Encapsulated SpaceWire PacketTCP Message Header

specifying reception of a SpaceWire packet the size of 5 bytes.

Page 21: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Test MiscellaneousTest Miscellaneous

• “2 Routers Topology” was tested in addition to the “Main Topology” to simulate complex routes in a SpaceWire network with more then one router.

• D1117_SPWRouter delivered successfully thousands of SpaceWire packets originated in PCs, to correct destinations which are PCs as well on the same SpaceWire network.

• “2 Routers Topology” was tested in addition to the “Main Topology” to simulate complex routes in a SpaceWire network with more then one router.

• D1117_SPWRouter delivered successfully thousands of SpaceWire packets originated in PCs, to correct destinations which are PCs as well on the same SpaceWire network.

Page 22: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

Further Possibilities Further Possibilities

• The router can be redesigned for multiple connections ‘routing matrix’. Currently the datapath of the router can only support one simultaneous connection from port to port.

• The router can be extended to support more SpaceWire routing schemes. (Not just Path Addressing + Header Deletion).

• The router can be redesigned for higher data rate ~200Mhz on the XC2v6000 FPGA using pipeline design.

• Writing a software Device Driver for windows to virtually make GRESB a SpaceWire network connection on a PC. It can be done by implementing a Device Driver which exposes an Ethernet Device abstraction towards Windows and on the other side, coding SpaceWire packets on GRESB. Such a Device Driver actually solves the problem of “Ethernet over SpaceWire” for PC.

• The router can be redesigned for multiple connections ‘routing matrix’. Currently the datapath of the router can only support one simultaneous connection from port to port.

• The router can be extended to support more SpaceWire routing schemes. (Not just Path Addressing + Header Deletion).

• The router can be redesigned for higher data rate ~200Mhz on the XC2v6000 FPGA using pipeline design.

• Writing a software Device Driver for windows to virtually make GRESB a SpaceWire network connection on a PC. It can be done by implementing a Device Driver which exposes an Ethernet Device abstraction towards Windows and on the other side, coding SpaceWire packets on GRESB. Such a Device Driver actually solves the problem of “Ethernet over SpaceWire” for PC.

Page 23: High Speed Digital Design Project SpaceWire Router Student: Asaf Bercovich Instructor: Mony Orbach Semester: Winter 2009/2010 2-Semester Project Date:

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