Final Presentation Final Presentation

Packet I/O Packet I/O Software Software

Management Management Application Application

PISMA®PISMA®Supervisor: Mony OrbachSupervisor: Mony Orbach

D0317D0317One-Semester ProjectOne-Semester Project

Liran Tzafri Liran Tzafri Michael GartsbeinMichael Gartsbein

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Background – Desired Background – Desired SystemSystem

Parallel Processing SystemParallel Processing SystemBased on Altera FPGA Based on Altera FPGA

Using Nios coreUsing Nios core

Sampling Sampling SystemSystem

PreprocessingPreprocessingSystemSystem

Data Data StreamStream

Analog Analog InputInput

N

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Equivalent SystemEquivalent System

Data Data StreamStream

Parallel Processing System Based on Altera FPGA Using Nios core

Parallel accelerator Parallel accelerator AlgorithmAlgorithm

MultiCore Embedded SystemMultiCore Embedded System

PCIPCI

ProcStarII boardProcStarII boardBased on STRATIX IIBased on STRATIX II

Data PackagesData Packages

Generator & Generator & Flow Flow ManagementManagement

Our Project

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Block DiagramBlock Diagram

PCI

BUS

Hardware processing

Transmitter

Reciever

Analyzer

Software

processing

Generator

The Host Application

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The Host ApplicationThe Host Application System flow:System flow:

Host Application generates times of arrival (TOA) vector in software

The Host App sends the vectors to the hardware system and gets the results

The communication is through PCI bus It will also make processing in software The results are analyzed

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Project ObjectivesProject Objectives

Programming the Host application, which Programming the Host application, which will generate the datawill generate the data

Creating modular designCreating modular design Defining the interface and protocol to the Defining the interface and protocol to the

board with the relevant groupsboard with the relevant groups Adding software processing to the Host Adding software processing to the Host

program for comparison with hardwareprogram for comparison with hardware Testing simulations resultsTesting simulations results

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Stratix 2 FPGA on Altera board

PCI bus

Host PC’s fan

ToolsTools

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ToolsTools

Stratix 2 FPGA Altera boardAltera board Gidel’s Proc wizard and IP coresGidel’s Proc wizard and IP cores …… Host PCHost PC Visual Studio 2005Visual Studio 2005

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Host Application Host Application InterfaceInterface

InputsInputs Packet noise parametersPacket noise parameters Missing elements parameters Missing elements parameters Region of interestRegion of interest Operation modeOperation mode

OutputsOutputs System throughputSystem throughput Vectors after hardware or software Vectors after hardware or software

processingprocessing

This image is for illustation only

Packet Structure :Packet Structure :Packet Generator OutputPacket Generator Output**

Sync=0x55555555 Sync=0x55555555

IDControl Bits Len

TOA2

TOAN

64 bits (DWORD)

Num TOA=N

...

Padding (if necessary)=0x55555555

Start TimeNum Params=M

TOA1

...

Param1

ParamM

8 bits

Nios Number (For Sw)

Type Sw/Hw Version Unused

Packet Structure :Packet Structure :Packet Receiver InputPacket Receiver Input**

*For further details see the Packet Structure document

IDControl bits Len

Durat (1)

64 bits (DWORD)

Ass1

Num Seq=M Num Assoc=N

Ass2…AssN

Conf level 1 (1)

Sync=0xAAAAAAAA Sync=0xAAAAAAAA

Start Time

Num non zero AssocUnused

…Pad=0x55Pad=0x55Pad=0x55

Finish Time

Num pulses (1)

Delay (1)

Conf level 2 (1)…

Durat (M)

Conf level 1 (M)

Num pulses (M)

Delay (M)

Conf level 2 (M)[Padding] Sync=0xAAAAAAAA

E

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Packet Generator\Packet Generator\Receiver InterfaceReceiver Interface

InputsInputs Was the data series identifiedWas the data series identified Average periodAverage period Number of values assigned to the data seriesNumber of values assigned to the data series Indexes of these valuesIndexes of these values

OutputsOutputs TOA vectors of random length between 8 to 1024TOA vectors of random length between 8 to 1024 Each TOA is a DWORD (32 bits)Each TOA is a DWORD (32 bits) Each vector has 1 to 3 data series with a random Each vector has 1 to 3 data series with a random

period between 10 to 10000, and noiseperiod between 10 to 10000, and noise Percentage of noise in each vector is an input to the Percentage of noise in each vector is an input to the

Host AppHost App Percentage of missing data from each vector is an Percentage of missing data from each vector is an

input to the Host Appinput to the Host App

Host App Operation Modes

In order to check the performance of the system, there should be two modes of operation: Correctness test: Checks correctness

for finite number of packets Performance test: Packets will be sent

continuously, elaborated in next slides

API Functions

Communication with the board is done using Gidel’s API functions

These functions offer a comparatively simple way to send, and receive data from the board

These also offer important tools for working with the board, such as resetting it, checking how much data it contains, etc.

Packet Send Chain (HW)

Packets are generated continuously, by the Packet Generator®. Here, the Packet contains only the data (TOAs), an ID, and the length

The Packets are forwarded to the Packetizer®, which adds a “header” and “footer” to the packet, according to the interface

Packet Send Chain (Cont.)

The Packetizer® then forwards a bit stream to the RxTx entity

The data is then sent immediately to the hardware (using DMA and Gidel’s API)

Packet Send Chain (SW) – Refers to The SW Processing Entity

Packets are generated and Packetized like in HW

Those are sent through the SW Rx\Tx entity

This entity contains a thread pool, from which it selects an available thread, or waits until one is available

The chosen thread gets the stream of data of the packet, and independently processes it

Packet Receive Chain (HW)

While there is data in hardware, it is read continuously, and stored in a local FIFO

The Depacketizer® entity transforms the DWORD stream from the FIFO into packets

Performance of the system is checked: number of packets processed compared with the run time

Packet Receive Chain (SW)

When one of the processing threads is done with a packet, it writes the result to a similar local FIFO as seen in HW

The Depacketizer® entity can read data from this FIFO as with the HW chain

The SW Processing

The software processing entity makes the same manipulations over the input data as the hardware

The component is implemented in a code package delivered by the algorithms team

This sw package can be replaced if a newer version comes

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This page was left blank This page was left blank on purposeon purpose

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Special ProblemsSpecial Problems Problem:Problem: Naming the project with a Naming the project with a

meaningful namemeaningful name Solution:Solution: Packet I/O Software Management Packet I/O Software Management

Application (PISMA)Application (PISMA)

Problem:Problem: Integration and synchronicity Integration and synchronicity between different project parts/groups between different project parts/groups Solution:Solution: Defining an all-accepted Interface Defining an all-accepted Interface

Problem:Problem: Debugging hardware and software Debugging hardware and software simultaneouslysimultaneouslySolution: Solution: Signal Tap, differential diagnosisSignal Tap, differential diagnosis

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Special ProblemsSpecial Problems

Problem:Problem: 1 MB limit on sending to 1 MB limit on sending to hardwarehardware

Solution:Solution: Solved Solved

Problem: Problem: Hard to measure real Hard to measure real performanceperformance

Solution: Solution: Different tests when each Different tests when each time another part of the system is time another part of the system is disableddisabled

Installation

The detailed installation how-to guide is available in the Final project document

Any configuration to the development environment (visual studio etc..) is also documented at the same location.

Usage

The usage is done by creating configuration files (with the vectors parameters) and passing commands line arguments to the program Details at the final document

Data analysis

The program outputs (with the processing results) statistics about the time spent in the computations

The program creates a log file with the TOAs indices and their associations to a sequence

In the hardware run, statistics about the different ICs, or clock ticks spent in HW available

Future Development

In general, the design of the system allows to add new functionality relatively easily

Any part can be replaced or improved

Future Development (cont.)

New groups (other than the lbs group) can use our sw with their hw

New processing hardware (different algorithm or better accelerator) can be tested

Improvement to the packet generation algorithm, new features etc

Improvement to the packet sending/receiving unit