Functional Coverage Driven Test Generation for Validation of Pipelined Processors

P. Mishra and N. Dutt

Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, Vol. 2, pp. 678 – 683, 2005

Speaker: Wen-Kai Huang

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Abstract Functional verification of microprocessors is one of the most

complex and expensive tasks in the current system-on-chip design process. A significant bottleneck in the validation of such systems is the lack of a suitable functional coverage metric. This paper presents a functional coverage based test generation technique for pipelined architectures. The proposed methodology makes three important contributions. First, a general graph-theoretic model is developed that can capture the structure and behavior (instruction-set) of a wide variety of pipelined processors. Second, we propose a functional fault model that is used to define the functional coverage for pipelined architectures. Finally, test generation procedures are presented that accept the graph model of the architecture as input and generate test programs to detect all the faults in the functional fault model. Our experimental results on two pipelined processor models demonstrate that the number of test programs generated by our approach to obtain a fault coverage is an order of magnitude less than those generated by traditional random or constrained-random test generation techniques.

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What’s the Problem Functional validation of microprocessors is one of

the most complex and expensive tasks in SOC design

Code coverage measures are commonly used Statement coverage Branch coverage Condition coverage Path coverage FSM coverage

However, these measures do not have any direct relationship to functionality of the device

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Related Works Simulation is the most widely used form

Random (constrained-random) test programs Directed test programs

Many techniques have been proposed for automatic generation of test programs [1, 4, 9, 11, 12, 16, 7, 3, 8, 6, 10, 13, 2, 14, 15].

However, these previous works do not Provide a comprehensive metric to measure the coverage

of the pipeline interactions, or Describe functional fault models for pipelined

architectures, use it to define functional coverage

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Main Ideas This paper makes three important contributions

Use general graph-theoretic model to capture the structure and behavior of pipelined processors

Propose a functional fault model for functional coverage measurements

Design an automatic test generation that accept the graph model as input and generate test programs as output

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Modeling for Processor Structure

Modeled as a graph

Components nodes Units (e.g. ALUs) Storages (e.g. register files)

Connectivity edges Pipeline edges Data transfer edges

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Example of Structure Graph

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Modeling for Instruction Behavior

Also use the graph model

Fields of each operation nodes Opcode Argument

Orderings between the fields edges Syntactical ordering Execution ordering

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Example of Behavior Graph

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Mapping between Structure and Behavior unit-to-opcode (opcode-to-unit)

Maps unit nodes in structure graph to opcode nodes in behavior graph

Example Unit Fetch maps to opcodes {ADD, STORE} Unit ALU maps to opcode {ADD} Unit AddrCalc maps to opcode {STORE}

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Functional Fault Models

Register Read/Write Model Operation Execution Model Execution Path Model Pipeline Execution Model

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Fault Model for Register Read/Write All registers should be written and read corre

ctly If VRi is written in register Ri and read back, the outpu

t should be VRi. In the presence of a fault, output in not equal to VRi

Coverage Estimation A fault in this model is covered if the register is writte

n first and read later

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Test Generation for Register Read/Write

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Fault Model for Operation Execution All operations must execute correctly

Let vali, where vali = fopcodei(src1,src2,…), denote the result of computing the operation “opecodei dest, src1, src2, …”.

The destination will contain the value vali. Under a fault, the destination is not equal to vali

Coverage Estimation A fault in this model is covered if the operation is perf

ormed, and the result of the computation is read

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Test Generation for Operation Execution

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Fault Model for Execution Path Execution Path (ep)

For an operation, the activated pipeline path (pp) with its data-transfer paths (dp)

An execution path epopi is faulty if it produces incorrect result during execution of operation opi

Coverage Estimation A fault in this model is covered if the execution path i

s activated, and the result of the computation is read

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Test Generation for Execution Path

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Fault Model for Pipeline Execution

A pipeline is faulty if it produces incorrect results due to execution of multiple operations in the pipeline Stall sets Exception sets Pipeline interactions

Coverage Estimation A fault in this model is covered if the fault is activated

due to execution of multiple operations in the pipeline, and the result of the computation is read

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Test Generation for Pipeline Execution

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Case Study Apply the proposed methodology on two architectur

es VLIW DLX LEON2 (SPARC V8)

Experimental Setup Use Specman Elite ‘e’ language to implement execut

able specification Use the propsed methodology to generate test progr

ams Apply the programs on the RTL codes and specificati

ons, and compare the results

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Experimental Results

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Conclusions Functional verification of microprocessors is one of

the most complex and expensive tasks in the SOC design process

The three contributions of this paper A general graph-model for structure and behavior

modeling A functional fault model used in defining the

functional coverage An test generation procedures were presented