Full-quantum simulation of heterojunction TFET inverters ...Sb heterojunction. Subthreshold slope...
Transcript of Full-quantum simulation of heterojunction TFET inverters ...Sb heterojunction. Subthreshold slope...
Full-quantum simulation of heterojunction
TFET inverters providing better performance
than Multi-Gate CMOS at sub-0.35V VDD
E. Baravelli, E. Gnani, A. Gnudi, S. Reggiani, G. Baccarani
Advanced Research Center on Electronic Systems (ARCES),
Department of Electronics (DEIS) – University of Bologna, Italy
This work has been supported by the EU Grant No. 257267 (STEEPER) and the Italian Ministry via the “Futuro in
Ricerca” Project (FIRB 2010).
E. GNANI 2ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Outline
Challenges of TFET design
Optimization of complementary hetero-junction
TFETs on the same technology platform
TFET-based inverter design and speed-
performance assessment
Comparison with CMOS logic
Conclusions
E. GNANI 3ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Challenges of TFET design
Simultaneously co-integrating n- and p-type
devices on the same technology platform.
E. GNANI 4ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Design approach
The transmission probability is enhanced by an abrupt
InAs-Al0.05Ga0.95Sb heterojunction.
Subthreshold slope and drain conductance are
optimized by a suitable choice of the degeneracy level
in the source and drain.
Ambipolarity is controlled by drain engineering.
The gate length is set at 20 nm in order to prevent
direct source-to-drain tunneling; the cross section is
thus 7x7 nm wide.
Device optimization is carried out with a 3D full-
quantum k·p simulation code.
E. GNANI 5ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Candidate devices
(Tn) 7nm-side n-TFET
(Tp) 7nm-side p-TFET
Al2O3 with EOT=1nm
E. GNANI 6ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Device performance @ VDD=0.4 V
E. GNANI 7ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Inverter configurations
0
1
2
3
I D [A
]
n-TFET (Tn2)
p-TFET (Tp1)
0 0.1 0.2 0.3 0.40
1
2
3
Vo [V]
I D [A
]
n-TFET (Tn2)
p-TFET (4Tp1)
|VGS
| = 0, ..., 0.4 V
| VGS
| = 0.05V
(a) I1 VTC construction
(b) I2 VTC construction
Inverter VTCs are constructed by combining ID-VDS families obtained by simulation in 0.05 VGS steps and non-linear Interpolation
Inv. I1Inv. I2
Vi
Vo
ID,p
ID,n
VDD
Tp
TnTn
Tp
E. GNANI 8ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Static performance
I1 has asymmetric VTC due to strong ION unbalance between Tn2 and Tp1
This is compensated for in I2 by using 4xTp1
In I2, WFs of the 4 Tp1 devices are adjusted to have 4xIOFF, p=IOFF, n=IOFF, LOP
E. GNANI 9ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Transient performance estimation
Device gate capacitance Cg is estimated from the
integrated charge of the whole device in the off
(QOFF) and on state (QON)
10% to 90% rise/fall times tr, f are computed by inte-
grating the drain currents at VGS = 0 V or VGS = |VDD|
(assuming instantaneous input transitions)
Miller effect expected to be significant for TFETs is
accounted for as CM = 2 ×Cgd , with Cgd ≈ 0.8 × Cg
→ Cload = 2.6 × (Cg,n + Cg,p) for a self-loaded inv.
,
Vi
Vo
ID,p
ID,n
VDD
pFET
nFET
Cgd
Cg,p
Cg,n
E. GNANI 10ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
TFET-based I2 vs. CMOS
-0.4 -0.2 0 0.2 0.4
10-10
10-8
10-6
VGS
[V]
I D [A
]
Tn2
4xTp1
CMOS nFET
CMOS pFET
|VDS
| = 0.4 V
CMOS: 10nm FinFETs simulated using PTM-MG models in Spice
WFs adjusted to make IOFF (and static power) of FinFETs equal to that of TFETs
TFET shows advantage at low VDD (< 0.35 V)
10-7
10-5
10-3
I ON [A
/m
]
102
104
106
10-8
10-6
10-4
ION
/IOFF
I ON [A
/m
]
TFET (Tn2)
CMOS 10nm
(a) VDD
= 0.4 V
(b) VDD
= 0.25 VNode L GATE WFIN HFIN
10nm 14nm 9nm 21nm
E. GNANI 11ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Comparison with CMOS @ VDD = 0.4 V
Miller effect and lower drive current make TFET inverter slower than CMOS under self-loading
Under constant loading, Miller capacitance is negligible, but CMOS is faster due to higher drive current at VDD = 0.4V
Rise/fall times under self-loading
TFET - I2b CMOS 10nm0
5
10
15
20
25
30
tr &
tf [p
s]
tr
tf
VDD
= 0.4 V
Rise/fall times under constant loading
1 1.5 2 2.5 3 3.5 4
0.5
1
1.5
2
Load Capacitance CL [fF]
tr &
tf [ns]
tr (TFET - I2b)
tf (TFET - I2b)
tr (CMOS)
tf (CMOS)
-0.4 -0.2 0 0.2 0.4
10-10
10-8
10-6
VGS
[V]
I D [A
]
Tn2
4xTp1
CMOS nFET
CMOS pFET
|VDS
| = 0.4 V
TFET
CMOS
E. GNANI 12ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Comparison with CMOS @ VDD = 0.25 V
At VDD = 0.25V, TFET is substantially faster than CMOS in both self-loading and constant-loading
This is due to the drive current advantage (≈10x) associated with a steeper SS
Rise/fall times under self-loading
TFET - I2b CMOS 10nm0
100
200
300
400
tr &
tf [p
s]
tr
tf
VDD
= 0.25 V
Rise/fall times under constant loading
1 1.5 2 2.5 3 3.5 4
5
10
15
20
25
30
Load Capacitance CL [fF]
tr &
tf [ns]
tr (TFET - I2b)
tf (TFET - I2b)
tr (CMOS)
tf (CMOS)
-0.4 -0.2 0 0.2 0.4
10-10
10-8
10-6
VGS
[V]
I D [A
]
Tn2
4xTp1
CMOS nFET
CMOS pFET
|VDS
| = 0.4 V
7x
10x
E. GNANI 13ALMA MATER STUDIORUM – UNIVERSITÀ DI BOLOGNA
Summary
Optimized n- and p-type hetero-junction TFETs based on the
InAs/Al0.05Ga0.95Sb material pair have been designed
The p-type TFET design requires substantial improvements in both ION
current and drain conductance at low VDD
Comparison of TFET and CMOS inverter performance at the 10nm
technology node:
CMOS wins at VDD = 0.4 V BUT TFET largely wins at VDD = 0.25 V
The analysis did not consider: (i) strain to improve TFET performance,
(ii) carrier scattering, (iii) interface states.
the obtained results should be regarded as qualitative indicators
The rise/fall times at these limiting VDD values are expected to be of the
order of 10 ps or a few tens of ps for a self-loaded inverter
TFETs will find possible uses for low-power,
moderate-performance applications