Frequency Changer

7/27/2019 Frequency Changer

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920 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 4, ALJGUST1990

An Analytical Maximum Toggle FrequencyExpression and its Application toOptimizing High-speed ECLFrequency Dividers

Abstruct -A novel method has been used to analyze static and regen-erative frequency dividers by relating their performance to that of theconstituent EXCLUSIVE-OR (XOR) ates. It ha s been found that the behav-ior of the propagation delay of XOR gates is quite linear and this hasallowed the derivation of a propagation delay expression for XOR gatesusing a sensitivity analysis. The validity of the expression has beencarefully checked by comparison with SPICE simulations and withreported results in the literature, and agreement to 10% has beenobtained.

In order to optimize frequency dividers, figures of merit for frequencydividers realized in silicon and AIGaAs/GaAs technologies are pro-posed. Expressions for optimum load resistance R,,,,,, and henceoptimum collector current density J, , are then derived from thesefigure-of-merit expressions. By comparing the optimum collector curr entdensities with the current densities at which the maximum f T occurs, itis found tha t improved performance can be obtained for silicon technol-ogy by designing transistors in which the maximum f T occurs at ahigher collector current density. For AIGaAs/GaAs technology, im-proved performance requires general reductions in T ~ ,,, and R E .This conclusion is consistent with results obtained on ECL and CMLring oscillators Ul, thereby demonstrating that the use of a ring oscilla-tor to optimize the fabrication process and transistor design shouldautomatically lead to an optimum value for the maximum toggle fre-quency of a frequency divider.

NOMENCLATURE

Propagation delay of logic circuit.Transistor forward transit time.Transistor cutoff frequency.Maximum toggle frequency of frequency divider.Transistor base parasitic series resistance.Transistor collector parasitic series resistance.Transistor emitter parasitic series resistance.Load resistance of logic gate.Optimized load resistance of logic gate.Intrinsic base-collector junction capacitance.Extrinsic base-collector junction capacitance.

Manuscript received November 28, 1989; revised March 5 , 1990.The authors are with the Department of Electronics and ComputetScience, University of Southampton, Southampton SO9 5 N H , EnglandIEEE Log Number 9036474.

20 -

15 -

10 -

5 -

o t f0 5 10 15 20 25

Reported Maximum Toggle Frequency (GHz)Comparison between predicted and reported maximum togglefrequency of frequency dividers.Fig. 1.

C,, Total base-collector junction capacitance.C,, Base-emitter junction depletion capacitance .C,, Collector-substrate junction capacitance.C, Base-emitter junction diffusion capacitance.C, Estimated metal track loading capacitance.

I. INTRODUCTIONITH advances in gigabit-per-second communica-tion systems, the need for very high-speed fre-quency dividers has become more important. Static andregenerative frequency dividers can operate up to 15 121and 18.0 GHz [3], respectively, utilizing silicon bipolartechnology. For AIGaAs/GaAs heterojunction bipolartransistor (HBT) static frequency dividers, an even higherfrequency of 22.15 GHz [4 ] has been reported in theliterature. The maximum toggle frequency of a frequency

divider is commonly used as a benchmark to assess theperformance of a technology for digital circuits.In order to predict the maximum toggle frequency andoptimize the circuit of the frequency divider, it is desir-able to have an expression which relates the maximum0018-9200/90/0800-0920$01.00 01990 IEEE

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FANG et al. : ANALYTICAL M AXI M UMTOGGLE FREQUENCY EXPRESSION

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fin-lout loutLow Pass Finer

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T-F.F.Circuit i Buffer CircuitFig. 2. Circuit diagram of static frequency divider.

toggle frequency to the electrical parameters of the di-vider. However, up to now, no such expression has beenavailable in the literature.The objective of this work is to derive a maximumtoggle frequency expression for frequency dividers thatrelates circuit electrical parameters to the maximum tog-gle frequency. The predicted results using the expressionagree very well with the reported data in the literature asshown in Fig. 1.

11. DERIVATIONF MAXIMUMOGGLEFREQUENCYXPRESSIONSAccording to previous results published in 111, a sensi-tivity analysis can be used to generate accurate propaga-

tion delay expressions for bipolar circuits. Therefore, thesensitivity analysis is used here to derive the maximumtoggle frequency expressions for bipolar frequency di-viders.A. Types of Frequency Dicider Investigated

There are two categories of frequency divider whichhave been described in the literature. One is a staticfrequency divider (SFD) [ 5 ]and the other is a regenera-tive frequency divider (RFD) [31. Both types will be in-cluded in the following discussion since each of them hassome advantages over the other.The typical circuit of a divide-by-two static frequencydivider is shown in Fig. 2 [5] .The circuit design is basedon the well-known T-connected master-slave D-typeflip-flop which uses the CML two-level series gating tech-nique. To achieve low power dissipation, two power sup-ply voltages of V E E nd VTr have been adopted. It is alsoreported that all the transistors in the T-type flip-flop arethe same and that they operate at the same current

7 out IFig. 3 . Principle of regenerative frequency divider

density, i.e., = I , , in Fig. 2. The internal buffersoperate as signal amplifiers and level shifters betweeneach T-type flip-flop.The advantage of static frequency dividers is that theycan operate from dc to the maximum toggle frequency.Therefore, they are very useful in digital circuit design.However, the static frequency divider contains more tran-sistors and consumes more power than the regenerativefrequency divider. Moreover, the maximum toggle fre-quency of a static frequency divider is lower than that of aregenerative frequency divider.Another very popular circuit for frequency dividers isthe regenerative frequency divider which was described byMiller in 1939 [6]. The maximum toggle frequency re-ported for regenerative frequency dividers in silicon tech-nology is 18.0 GHz [ 3 ] ,which is twice as high as the valueof 9.1 GHz reported for a static frequency divider [SIusing the same SST technology.The block diagram of a regenerative frequency divideris shown in Fig. 3 . The input frequency f is applied to onemixer input, and the output of the mixer is fed back to theother mixer input. The output signal of the mixer containsthe frequency f / 2 and its harmonics 3 f / 2 , 5 f / 2 , . . . .The high-order harmonic components are filtered out bythe low-pass filter and the wanted frequency f / 2 is am-plified and is fed back to the mixer.The circuit diagram of the regenerative frequency di-vider is depicted in Fig. 4 [ 3 ] using a double-balancedmodulator. Transistors e, -Q, , act as the modulators



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922 IEFE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25, NO. 4, AUGLJST 1990

Fig. 4. Circuit diagram of regenerative frequency divider.'JEE

active load. The single-ended input frequency is fed to thef, , node and the output frequency can be obtained at thef i n / 2 node.The disadvantage of regenerative frequency dividers isthat they have a higher minimum toggle frequency f M v l l Nbecause the harmonic 3f/ 2 may no longer be suppressedif the input frequency f falls below f M A X / 3 . This is amajor disadvantage in some applications.

B. Choosing the Electrical ParametersThe electrical parameters used for deriving the maxi-mum toggle frequency expression of bipolar frequencydividers are based on a 0.5-pm self-aligned transistor andare listed in Table I . The electrical parameters in Table Iare the same as those published in [ l ]with the exception

of the wiring capacitance C, which has been increased totake account of the longer interconnections and the higherfan-out in the frequency divider.Second-order effects in the SPICE bipolar junctiontransistor model have been neglected in order to get asimple and general expression for frequency dividers. Themost important of these is the increase in T~ with collec-tor current at very high current density. This mechanismcan reasonably be neglected provided the transistors op-erate below the current density of maximum f 7 . , where T~is a constant [7], [SI as shown in Fig. 5. This can bejustified by noting that the propagation delay of bipolarcircuits as a function of collector current is very flat athigh current density as shown in 111. This implies that anyincrease in T~ at high current density will increase thepropagation delay significantly because r F is a dominanttime constant in bipolar logic circuits [l]. Therefore, foroptimum speed, the maximum collector current in logiccircuits should be designed to be below that of the maxi-mum f r which corresponds to the onset of T~ rise.The output voltage swing of the frequency divider was

TABLE IELECTRICALAR AM ETER SORO.s-/.LmTRANSISTOR

123.0

30

U24- 20.ErceE 10ELL

0 0.1 10Collector Current (mA)

Fig. S . The behavior of a bipolar transistor at high current density aspredicted by SPICE.chosen as 400 mV because of the compromise betweenthe speed and the noise immunity [l]. It should be notedthat, for all types of frequency divider, the maximumtoggle frequency depends only on the first stage-1/2frequency divider. It is therefore only necessary to study1/2 frequency dividers since the results for 1/4 or 1 /8frequency dividers will be the same.C. Maximum Toggle Frequency Expression

Ideally, to optimize the performance of frequency di-viders, one would like to have an expression that relatesthe maximum toggle frequency to the electrical parame-ters of the divider:1 1

f M * X = f ( % ~ , > G ) = - + + . . . (1 )K P F K,R,C,c,However, it is difficult to derive the weighting factors inthe above expression since the maximum toggle frequencyof a frequency divider is difficult to estimate accuratelyusing SPICE simulations.



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FANG et al.: ANALYTICAL M A X I M U M TOGGLE FREQUENCY EXPRESSION 923I 1 T T I

Q7yq ,r t T hFig. 6. Equivalent XOR gate for frequency dividers.

In order to overcome this problem, a novel method forderiving the maximum toggle frequency expression is pro-posed as follows. Firstly, all the feedback wires in thefrequency divider a re cut, thereby converting the sequen-tial frequency divider circuit into a combinational circuit.Secondly, the constituent circuit is configured as an in-verter to form an inverter chain, and the propagationdelay T~ of the inverter is then derived using a sensitivityanalysis. Finally, the maximum toggle frequency of thefrequency divider is expressed as

SFD, which agrees well with the experimental data pub-lished in the literature [31, [51.D. Converting the XOR Gate into an Inuerter

Th e XO R gate shown in Fig. 6has two inputs A and Band two outputs S and s. Since the circuit is fully sym-metrical, the propagation delays of the complementaryoutputs S and 5 are identical. If we select S as the outputto study the propagation delay of the circuit, there aretwo ways to convert the XOR gate into an inverter: letB = 1 then S = Aa nd let A = 1 then S = B.The XO R gateis implemented by stacking CML circuits vertically andsimulation shows that the propagation delay through in-put A is longer than that through input B. According tothe operating concept of the frequency dividers, the maxi-mum toggle frequency of a frequency divider is deter-mined by the critical path which is the longest propaga-tion path. Therefore, we let B = 1 and use A as the inputnode to study the propagation delay of the XOR gate.In Fig. 6, notice that the input voltage of node Arequires - 1.8f 0.2 V, while the output voltage from theemitter of Q7 is about - 1kO.2 V. In order to form apropagation delay chain, a voltage source is inserted inthe emitter follower to shift the output voltage to therequired value. In real circuits, the voltage source wouldbe replaced by another emitter follower or a diode.

1f M A X =- ( 2 ) E. Linearity of the Propagation DelayK T D

where K is a weighting factor depending on the particularcircuit configuration used for the frequency divider. Thepropagation delay T~ can be expressed as the linearweighted sum of all the time constants of the inverter [l]:rD = K O l r F + RL( K02CJCl + K03CJCX

+ K04C./E + K 0 5 C J S ++ R B ( K07CJCI + K08CJCX + K09CJE-k K I O C D + KllCJS + K 1 2 C L )+ R C ( K i 3 C J C I + K, ,CJCx + Ki,CJE+ K 1 6 C D + K l l C J S + K 1 8 C L )+ R E ( K19CJCl + K20CJCX + K 2 i C J E+ K22CD + K23CJS + K 2 4 C L ) . (3)

For the static frequency divider shown in Fig. 2, if wecut all the feedback wires in the circuit, the frequencydivider is converted into two identical XOR gates as de-picted in Fig. 6. Since these two XOR gates are identical,the weighting factor K in (2) for the SFD can be expectedto be 2.Similarly, the regenerative frequency divider shown inFig. 4 is converted into a single XOR gate, and so in thiscase the weighting factor K in (2 ) for the RFD can beexpected to be unity. This implies that for the same set oftransistor parameters the maximum toggle frequency ofan RFD will be approximately twice as high as that of an

In order to predict the maximum toggle frequencyaccurately, we must make sure that the propagation delayof the XOR gate is linear over a reasonable electricalparameter range as represented in (3). Although thelinearity of ECL and CML inverters has been confirmedin a previous paper [l], the linearity of the propagationdelay of XOR gates is not necessarily the same as ECL andCML inverters. Therefore, a linearity study has beencarried out in order to determine the ranges of electricalparameter values over which the weighting factors arevalid.The SPICE program has been used to study the linear-ity of the propagation delay of XOR gates. A plot ofthe propagation delay of XOR gates as a function of theparasitic capacitances is shown in Fig. 7. This figure isobtained by changing the transistor parameters listed inTable I one by one and plotting the propagation delay asa function of the element values. From the plot shown, itis seen that t he behavior of the propagation delay of XORgates is approximately linear over a reasonable range ofelectrical parameter values, and so a general-purposepropagation delay expression for XOR gates is achievable.All of the 24 weighting factors for the XO R gate propaga-tion delay expression in (3) have been extracted using asensitivity analysis [1] and they are listed in Table 11.It is necessary to clarify here that the fan-in of the XORgate is 2 and the fan-out of the XO R gate is 1 in thederivation of the XOR propagation delay expression. How-

- -



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924 I E E E JOURNAL OF SOLID-STATE CIRCUITS, VOL. 25 , NO. 4, AUGUST 1990TABLE I1D ELA Y ONSTANTSND CORRESPONDINGWEIGHTINGACTORS

90

60

30I, 10 2 4 6 6

Various Capacitances (B)Fig. 7 . SPICE-simulated propagation delay as a function of variouscapacitances for a n XOR gate with FI = 2, FO = 1 .

ever, the propagation delay of XOR gates with fan-outgreater than 1 can be calculated by adding an equivalentload capacitance to the output of the XOR gate becausethe base current which is required to drive the secondstage is negligibly small compared to the output currentof the emitter follower. It should also be noted that thepropagation delay expression derived by this method isgeneral, because the propagation delay characteristics ofbipolar logic circuits are linear, as demonstrated in Fig. 7. Moreover, because ECL circuit design is quite unique,there is not much room to maneuver after the collectorcurrent and output voltage swing are determined. Forexample, if the voltage supply V,, is increased, the biasvoltages of the operating transistors remain the same , andthe extra voltage will be dropped across the currentsource. Therefore, the choice of electrical parameters forthe bipolar transistors in the derivation of the propaga-tion delay expression is not important.

111. VERI F I CATI ONIn order to validate the maximum toggle frequencyexpression for the two types of frequency divider, a strictverification procedure is carried out in the following sec-tions.

I RECD 1 15 1 1.560.14 0.25

RBCL 0.07K13 R&JCI 1.72 3.13K M R&JCX 1.62 3.23

0.09

From the plots shown in Fig. 8, it can be concluded thatthe weighting factors of the XOR gate propagation delayexpression are accurate and the discrepancy between theSPICE simulation and the expression is within + 10% formost types of bipolar transistor. For example, a propaga-tion delay of 51.1 ps is obtained from SPICE simulationusing the 0.5-pm silicon transistor parameters listed inTable I while the value predicted by the propagationdelay expression is 51.0 ps.

A. EXCLUSIVE-OR Gate B. Static Frequency DividerSince the maximum toggle frequency of frequency di-viders is based on the propagation delay of XO R gates,verification is initially obtained by comparing the resultsof SPICE simulations with the values predicted by thepropagation delay expression. The electrical parametersused for verification are the parameters of the 0.5-pmstate-of-the-art silicon transistor listed in Table I. Theplot verification method [1] has also been used to provideverification over a wide range of parameter values asshown in Fig. 8. The curves marked as SPICE areSPICE simulation results and the curves marked as TDEquation are the predicted values of the XOR propaga-tion delay expression.

The motivation of deriving the propagation delay ex-pression for an XOR gate is to predict the maximum togglefrequency of frequency dividers. For example, if the prop-agation delay of an XOR gate using 0.5-pm self-alignedtransistors is 51.0 ps, according to (21, the maximumtoggle frequency of the static frequency divider should bearound 9.8 GHz. In order to verify this relationship,direct SPICE simulations have been carried out as fol-lows.The circuit diagram of a static frequency divider isshown in Fig. 2. In the following simulations, the single-ended sinusoidal input signal was connected to the clockinput C and the complementary clock input c was con-



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FANG et al .: ANALYTICAL M A X I M U M TOGGLE FREOUENCY EXPRESSION 925

5012Intrinsic Collector Capacitance (F)

(a )70 c -1t 1

55 ,0 2 4 6 8

Extrinsic Collector Capacitance (fF)(b)

5572 4 6Emitter Capacitance (fF)

(c)! ~ . ' l ' ' ~ l ' l ' l l

55 ,0 2 4 6 8

Substrate Capacitance (fF)

3032Load Capac i tance ( fF)

(e)Fig. 8. Propagation delay ascapacitance for an XOR gate,capacitance for an XO R gate,

a function of (a) intrinsic collector capacitance for(c) emitter capacitance for an XOR gate, (d) substrateand (f ) forward transit time for an XO R gate.

Forward Transit Time (psec)(f )

an XOR gate, (b)capacitance for an extrinsic collectorXO R gate, (e) load

nected to a reference voltage. Since only one flip-flop isnecessary for the SPICE simulation, the internal bufferoperating as a signal amplifier and a level shifter wasomitted and the output frequency was obtained directlyfrom the emitters of Q14 and Q15.The amplitude of theinput signal was 400 mV.In order to verify that the static frequency dividers canoperate at low frequency, a 1-GHz input frequency was

used initially and satisfactory operation obtained. Onincreasing the input frequency gradually up to 9.6 GHz,the frequency divider still operated correctly. Fig. 9(a)shows the input and output waveforms of the frequencydivider at an input frequency of 9.6 GHz. However, if theinput frequency was increased to 9.8 GHz, the frequencydivider stopped working properly, as shown in Fig. 9(b).Therefore, the maximum toggle frequency of the 0.5-pm



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IEEE JOURNAL OF SOLID-STATE CIRCUITS,VOL. 25, NO . 4, AUGUST 1990

Unit Si[12] HBT[14] HBT [13] HBT [4]llm2 1 x 5 2 x 5 2 x 4 2 x 5

s- -1.9-2.2

L -1Em0d -1.328 -1.6E

- nput-- output

-

:-

- nput-- output

p -1.9-2.2

RLcJCICJCXCJE

0 100 200 300 400 500 600Time (psec)( a )

n 40 0 270 185 250fF 3.20 8.50 8.00 8.50fF 13.8 0 0 0fF 19.0 15.0 12.0 15.0

-0.71 4

CReportedf,Predictedf,

t

fF 60.0 60.0 60.0 60.0GHz 6.0 13.7 20.1 22.2GHz 5.7 14.9 19.6 22.6

- nput-- output

g -1.9I -2.2

0 200 400 600 800Time (psec)(b)

Fig. 9. SPICE-simulated input and output waveforms of a static fre-quency divider at an i nput frequency of (a) 9.6 GHz and (b) 9.8 GHz.

silicon static frequency divider is 9.7 GHz, which agreeswell with the predicted value of 9.8 GHz.Since the maximum toggle frequency of static frequencydividers is widely used as a benchmark for evaluating thespeed performance of bipolar technologies, a large num-ber of papers have been published in the literature onstatic frequency dividers as shown in Table 111. Amongthese papers, only four of them have published the elec-trical parameters of the circuits [4], [12]-[14] as listed inTable IV . In the table, r F , R,, and C, are calculatedfrom reported values of f T and I , by approximating

r F= 1/2.rrfT,,,,, RL = A v / I 0 , and c, = 27-~/R,. cLis estimated from the wiring capacitance between twoconsecutive flip-flop stages taking account of the higherfan-out, and is assumed to be 60 fF for all the circuits.C,, is estimated from the reported emitter area and thedoping concentration. The substrate capacitance C,, isassumed to be zero in the HBT circuits because they aremanufactured on semi-insulating substrates. Since thebase contact resistance is dominant in AlGaAs/GaAsHBT technology, all of the collector junction capacitancecan be considered to belong to C,,,, and C J C x s approxi-mately zero, as can be seen by referring to the SPICE

TABLE 111RECENTLY EVELOPEDCL STATIC REQUENCY D I V I D E R S

I 1/8divider I 10.38GHz I SiliconSST-1A I NTT 1 [111 II 1/8 divider I 9.1GHz I Silicon SST I NTI I [ 5 ] II 1/8 divider I 6.0GHz I SiliconHE I Plessev I 1121 II 1/4divider I 22.15GHz I HBTSSBE I NTI I 141 II 1/4divider I 2O.lGHz I HBTSADLO I Rockwell I 1131 II 1/4divider I 13.7GHz I HBTSSBE I N l T I 1141 I

TABLE IVRFPORTED LECTRICALARAMETFRSOR STATIC RE O UE NCYI V I D F R ~

model shown in 111. Using this data, the predicted maxi-mum toggle frequency using (2) for the silicon frequencydivider is 5.7 GHz, which agrees well with the measuredvalue of 6 GHz [12]. Excellent agreement is also obtainedfor the three dividers realized in AlGaAs/GaAs technol-ogy as listed in Table IV , which indicates that the maxi-mum toggle frequency expression is also valid for HBTtechnologies.It is interesting to note that although completely differ-ent technologies have been used in these static frequencydividers, the discrepancies between experiment and pre-diction are less than 10%. It seems reasonable to con-clude that the maximum toggle frequency expression offrequency dividers is accurate and should be very usefulfor design, optimization, and performance prediction.C. Regenerative Frequency Dicider

The circuit diagram of the regenerative frequency di-vider is described in Fig. 4. The relationship betweeninput frequency and output voltage swing of the regenera-tive frequency divider is shown in Fig. 10 using the



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92 1F A N G et al.: ANALYTICAL M A X I M U M TOGGLE FREQUENCY EXPRESSION

400rn5 10 15 20 25

Input Frequency (GHz)SPICE-simulated output voltage swing of a regenerative fre-ig. 10. quency divider as a function of input frequency.

0.5-km transistor parameters listed in Table I. Notice thatthere is a minimum input frequency for the regenerativefrequency divider and the output voltage swing decreaseswhen the input frequency increases. Therefore, there isno obvious boundary which determines the maximumtoggle frequency. However, if the output voltage swing istoo small, the next stage of the frequency divider will notbe able to work properly. If a minimum output voltageswing equal to half of the original is postulated for correctoperation of the subsequent stage, a maximum togglefrequency of approximately 20 GHz can be obtained fromthe plot, which is about twice the value of 9.8 GHzpredicted for the static frequency divider. This is consis-tent with a weighting factor of unity in (2) for regenera-tive frequency dividers.The above discussion indicates that it is necessary forregenerative frequency dividers to use an amplifier be-tween two stages to amplify the output voltage so that theoutput voltage swing of the first stage is large enough todrive the next stage. Otherwise, the output voltage swingof regenerative frequency dividers is too small to drive thenext stage at high frequencies.At very high frequencies, the output voltage swing ofthe regenerative frequency divider decreases markedly.Although the output voltage swing can be amplified by abuffer, the maximum toggle frequency of the regenerativefrequency divider is limited by the second stage, which isa static frequency divider. Therefore, the maximum togglefrequency of a cascaded regenerative frequency divider istwice as high as that of the static frequency divider of thesecond stage. Consequently, in the design of regenerativefrequency dividers, attention must be paid not only to theregenerative frequency divider of the first stage, but alsoto the static frequency divider of the second stage.

simulation program, which is not only tedious but some-times the program does not converge due to the positivefeedback. More importantly the expression can quantifythe contribution of each time constant and therefore isvery useful in circuit design, performance optimization,and technology assessment.A. Figure of Merit for A lGaA s / Ga As Diciders

Although the maximum toggle frequency expression offrequency dividers has been shown to be a general-pur-pose expression, it can be considerably simplified forparticular technology applications. The generality of thefull expression can therefore be traded for a short expres-sion which we have called a figure of merit.One of the advantages of the maximum toggle fre-quency expression is that it allows us to break down thetotal propagation delay, and the contribution of each timeconstant to the propagation delay is quantified as shownin Fig. 11. For state-of-the-art HBT transistors, the tenmost important time constants of the expression can read-ily be identified and therefore the figure of merit for HBTstatic frequency dividers can be expressed as1

-= 1.927,-+ R,(2.57CJ, +0.65CJ, +0.28C,)2fh4AX + RR(2.94CJ, + 1 56CJ, + 1.56CL,)+ R,(3.86CJ, +3.49CJ, +1.93CD). ( 4 )By substituting some HBT electrical parameters intothe above equation, one should be convinced that thisfigure-of-merit expression is also reasonably accurate. Forexample, for the three HBT electrical parameters listed inTable IV, the maximum toggle frequencies predicted bythe figure-of-merit expression are 16.1, 21.6, and 25.3GHz, respectively, which agree reasonably well with thereported values of 13.7, 20.1, and 22.2 GHz, respectively.

B. Optimization of HBT Frequency Dir'idersIt can be seen from (4) that the maximum togglefrequency expression takes account of the dependence oncollector current automatically since the load resistance

R,. is an implicit function of the collector current RL =AV/Z,. The choice of R, involves a trade-off betweenthe C, and R , terms because the diffusion capacitanceC, is equal to 2 r , / R , , and therefore there is an opti-mum value of R,. By differentiating the right side of (4 )with respect to R, and setting it equal to zero, theoptimum R, for both static and regenerative frequencydividers can be expressed as

IV. APPLICATIONS2 ~ ~ (.56R, + 1.93RE)2.57CJ, +0.65CJ, + 0.28CL . ( 5 )L,,,, =

One of the advantages of using the maximum togglefrequency expression is to predict the maximum togglefrequency of a frequency divider without running a SPICESubstituting the electrical parameters of the state-of-the-art HBT [13] listed in Table IV into ( 5 ) gives R,,,,,

= 139 R (hence I,, = 2.9 mA and J , = 3.6 X l o 4 A/cm2



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928 I E E E JOURNAL or SOLID-STATF CIRCUITS. VOL. 25 , NO. 4, AUGUST 1990

6 - Ref. [14] -li Ref.[13]Qv

EB 4 -5-

02.0)-0 2 - -

0 - -L 1z p RLCK RLCJE LCL R&K RK JE BCDR.&L R E X RE IS R E D R E L R&K R K J E ~ C D

Fig. 11 . Components of propagation delay for AlGaAs/GaAs frequency dividers predicted using the maximum togglefrequency expression.

25 4

- RB=BOohms-- RB=4Oohms

,,,,,,/ optimum current- RB=BOohms-- RB=4Oohms

0 1 , -10.1 1 10

Collector Current (mA)Fig. 12. Maximum toggle frequency of HBT frequency dividers as afunction of transistor collector current predicted by the maximumtoggle frequency expression.

for an output voltage swing of 400 mV). This yieldsf M A X= 22.1 GHz, which is not much of an improvementover the value of f M A X= 21.6 GHz when the reportedvalue of R , = 185 0 ( I , E 2.2 mA and J , = 2 . 7 ~0'A/cm2) is used in the figure-of-merit expression (4). Itshould be noticed that the predicted optimum value ofI , E 2.9 mA, which corresponds to a current density of3.6X lo4 A/cm2, is well below the current density of6 X l o 4 A/cm2 at which the maximum f T occurs [13] .The relationship between the maximum toggle fre-quency and the collector current, obtained using themaximum toggle frequency expression ( 2 ) , s shown in Fig.12 .From the plot, it can be seen clearly that there is anoptimum value of I , (or an optimum value of R,) atI , E 2.7 mA (hence R , = 148 R ) which agrees well withthe value of R , = 139 R predicted by (5) .In order to further optimize the circuit, one can use (4 )to obtain a breakdown of the delay components andhence identify the most important terms. Fig. 11 showsthat the three most important terms for HBT frequency

dividers are r F , R I .C J C , nd R,C,, and therefore furtherdecreases in rF , R, , and the parasitic capacitances aredesirable. However, IC designers are fully aware of theeffects of T~ and parasitic capacitances and these param-eters are usually kept to a minimum. Hence, the onlyremaining option for optimizing HBT frequency dividersis to decrease the load resistance R, .According to (51, it is very clear that there is little to begained from decreasing R, further without optimizingHBT technology. I n order to decrease the optimum valueof R,, further reduction of R , or R , is important. Forexample, if R, can be reduced from 80 R to 40 R , themaximum toggle frequency can be increased to 23.6 GHzat a collector current of I , = 3.2 mA, which is equivalentto a load resistance of R , = 125 R as shown in Fig. 12 .Away of reducing R , and R, without increasing parasiticcapacitances is to decrease the contact resistance of theemitter and base as discussed in [11.C. Figure of Merit for Silicon DiLiders

In Table V, the contribution of each time constant tothe propagation delay of silicon frequency dividers isquantified. By inspection of the table, the ten most impor-tant terms of the expression can be identified and there-fore the figure of merit for silicon static frequency di-viders can be expressed as1-- - 1.927, + R B (1.56C,, +1.56CD)

2 f M A X + RL (2.57C,, + 0.65CJ, + 1.32CJ, + O.28CL)+ R,(3.23CJ, +O.78CD + 1.56CJ,) ( 6 )

where C,,, is the total collector capacitance C, , = cJ,[+C,,,. These have been combined because the weightingfactors for C,,, and C,,, associated with the R, and R ,terms are nearly the same as shown in Table 11.



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929ANG et a l . : ANALYTIC'AI- MAXIMUMTOGGLE FREOUENC'Y E X P R E S S I O N

KIJRLCJS I 15.84

TABLE VDFIA Y C O M P O N F N T SOR SII C O N TRA~W\ISTORSI Delay component I Delay forXOR I DelayforECL 1

3.24I IK,RrCr I 6.72 3.72

43.49ps

The accuracy of the figure-of-merit expression for sili-con frequency dividers can be verified by substituting thesilicon electrical parameters listed in Table IV into (6).The maximum toggle frequency predicted by the figure-of-merit expression ( 6 ) is 6.1 GHz, which is in excellentagreement with the reported value of 6 GHz [121.D. Optimization of Silicon Frequency Dividers

In a similar way to that described for HBT frequencydividers, according to ( 6 ) , the optimum load resistanceR,,,,, for silicon frequency dividers can be derived as

2 r F ( .56 R B + 0.78 R, )RL,OPT = 2.57C,, +0.65C,, + 1.32C,, +0.28C, '

( 7 )For the silicon electrical parameters listed in Table IV,the optimum value of load resistance is R,-,,,,= 194 R(hence I o = 2 . 1 mA and J c = 4 . 1 X 1 O 4 A/cm2 for anoutput voltage swing 400 mV), well below the reportedvalue of R, = 400 R (hence I , = 1 mA and J , = 2X l o 4A/cm*). This means that if the silicon transistor could bedesigned to operate at a higher current density, an in-crease in the maximum toggle frequency could be achieved

through the use of a smaller R,-. or example, if themaximum f T was obtained at J , = 4X lo4 A/cm2, theload resistance of the frequency divider could be reducedto R , = 2 00 R . This would yield a maximum togglefrequency f M m of 8.5 GHz, which is 1.4 times faster thanthe value of 6.1 GHz obtained with R, = 400 R. A way ofincreasing the current density at which the maximum f7.occurs is to design a transistor with a selective ion-implanted collector, which has been discussed in [11.If increasing the current density for maximum f r andhence the usable operating current density is not possible,we can still decrease the value of R , but keep the samecurrent density in order to prevent the high-current Kirkeffect [16]at the expense of a lower output voltage swingand hence a lower noise immunity. It has been reportedin [5 ] hat a circuit using an internal voltage swing of 225mV is capable of operating 1.5 times faster than thatusing 450 mV.Although the requirements for optimizing HBT or sili-con frequency dividers are totally different, the expres-sions for the optimum load resistance are similar, as canbe seen by comparing ( 5 ) with (7 ) . The only differencesare that silicon transistors have a higher collector resis-tance than HBT devices and the substrate capacitance forHBT devices is zero. Therefore, (5) and (7) could becombined as

- I 2 r F ( 1 . 5 6 R B+ 1.93RE +0.78R,)KL.oPT = 2.57C,, +0.65C,, + 1.32C,, +0.28CL .

E. Comparison of Time Constants for E C L and XO R GatesECL ring oscillators are widely used as test vehicles forevaIuating bipolar technology. However, since real circuitsare more complex than ECL inverters, the question arises

as to how well they reflect the performance of realcircuits. In order to answer this question, we have tocompare the weighting factors of ECL inverters and theweighting factors of real circuits.Suppose an ECL ring oscillator was used for evaluatingthe performance of frequency dividers. The weightingfactors for ECL inverters and frequency dividers arelisted in Table 11. By comparison, it is seen that there is aclose correspondence between the relative magnitudes ofthe weighting factors for frequency dividers and ECLinverters.In order to establish further confidence in the testvehicle of ECL ring oscillators, a comparison of each timeconstant is made between a silicon ECL inverter and afrequency divider as shown in Table V using the silicontransistor parameters listed in Table IV. It is found thatthe ECL inverter and XO R circuit have the same five mostimportant terms, namely r F ,R,C,, R,C,,,, R,C ,,, andR,C,, indicating that the use of a ring oscillator tooptimize the fabrication process and transistor designshould automatically lead to an optimum value for the



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930 IEFE J OURNAI OF SOLID-STATE CIRCUITS,OL. 25, NO.4, AUGUST 1990maximum toggle frequency of a frequency divider. Forinstance, the predicted optimum load resistance for thesilicon ECL inverter is 225 a, hich is very close to thatof 19 4 R for t he frequency divider.

V. CONCLUSIONSA novel method has been used to analyze static andregenerative frequency dividers by relating their perfor-mance to that of the constituent EXCLUSIVE-ORates. Ithas been found that the behavior of the propagation delayof XOR gates is quite linear and this has allowed thederivation of a propagation delay expression for XORgates using a sensitivity analysis. The validity of the ex-pression has been carefully checked over a wide range oftransistor and circuit parameter values by comparisonwith SPICE simulations and reported results in the litera-ture.It has been found that this expression can be used toaccurately predict the maximum toggle frequency of fre-quency dividers. Using this expression, it has also beenverified that the maximum toggle frequency of regenera-

tive frequency dividers is about twice as high as that ofstatic frequency dividers. Direct SPICE simulations haveproved that for regenerative frequency dividers there is aminimum toggle frequency below which circuit operationceases, and this is about a third of the maximum togglefrequency.In order to optimize frequency dividers, figures of merithave been proposed for silicon and AlGaAs/GaAs HBTdividers. Expressions for optimum load resistance R,,,,,(hence the optimum collector current density J, ) havealso been derived from these figure-of-merit expressions.By comparing the predicted optimum collector currentdensities with the current densities of maximum fT, it isfound that increasing the current density at which themaximum fT occurs is very important for silicon transis-tors, while reductions in r F ,R,, and RE are desirable forAlGaAs/GaAs transistors in order to reduce R , andtherefore increase the maximum toggle frequency of thedividers. This conclusion is consistent with that of ECLand CML circuits [ll and therefore the study shows thatthe use of a ring oscillator to optimize the fabricationprocess and transistor design should automatically lead toan optimum value for the maximum toggle frequency of afrequency divider. This approach can also be used foroptimizing adder and multiplier circuits because the basicconstituent circuit of them is an XO R gate.REFERENCES

[l ] W. Fang, Accurate analytical delay expressions for ECL andCML circuits and their applications to optimising high-speed bipo-lar circuits, IEEE J . Solid-State Circuits, vol. 25, no. 2, pp.572-583, Apr. 1990.P. Weger, L. Treitinger, J. Bieger, and H.-M. Rein, 15 GHz staticfrequency-divider IC in silicon bipolar technology, Electron. Lett.,vol. 25, pp. 513-514, 1989.H. Ichino et al., Super self-aligned process technology (SST) andits applications, in BCTM Tech. Dig. , 1988, pp. 15-18.

[2][3]

[4][5]

Y. Yamauchi et ul., 22 GHz 1/4 frequency divider using Al-GaAs/GaAs HBTs, Electron. Lett., vol. 23, pp. 881-882, 1987.M. Suzuki, K. Hagimoto, H. Ichino, and S. Konaka, A 9-GHzfrequency divider using Si bipolar super self-aligned process tech-nology, IEEE Electron Decice Lett., vol. EDL-6, pp. 181-183,1985.[6] R. D. Miller, Fractional-frequency generators utilizing regenera-tive modulation, Proc. IRE, vol. 37, pp. 446-457, 1939.[71 I. E. Getreu, Modeling the Bipolar Transistor. Amsterdam: Else-vier, 1984.[81 P. Antognetti and G. Massobrio, Semiconductor Delice Modelingwith SPICE. New York: McGraw-Hill, 1988.[9] A. Tahara et al., Low-power high-speed EC L circuits with 0.5-fimrules and 30 GHz f T technology, in BCTM Tech. Dig., 1989, pp.169-171.

[ I O ] M. C. Wilson, P. C. Hunt, and D. J. Bazley, 10.7 GHz frequencydivider using double layer silicon bipolar process technology,Electron. Lett., vol. 24, pp. 920-922, 1988.[ l l ] T. Sakai, S. Konaka, Y. Yammamoto, and M. Suzuki, Prospectsof SS T technology for high speed LSI, in IEDM Tech. Dig., 1985,pp. 18-21.S. Duncan, M. C. Wilson, P. C. Hunt, and D. J. Bazley, A 1-pmtrench isolated high speed bipolar transistor, presented at theVLSI Symp., San Diego, CA, 1988.K., C. Wang, P. M. Asbeck, M. F. Chang, G. J. Sullivan, and D. L.Miller, A 20-GHz frequency divider implemented with hetero-junction bipolar transistors, IEEE Electron Dwice Lett. , vol.T . Ishibashi, Y. Yamauchi, 0. Nakajima, K. Nagata, and H. Ito,High-speed frequency dividers using self-aligned AlGaAs/GaAsheterojunction bipolar transistors, IEEE Electron Decice Lett.,K. .Nagata et al., Self-aligned AIGaAs/GaAs HBT with lowemitter resistance utilizing InGaAs cap layer, IEEE Trans. Elec-tron Deikes , vol. 35, pp. 2-7, 1988.C. T. Kirk, A theory of transistor cutoff frequency ( f r ) falloff athigh current densities, IRE Trans. Electron Der.ices, vol. ED-9,

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EDL-8, pp. 383-385, 1987.[I41vol. EDL-8, pp. 194-196, 1987.[15]

[I61pp. 164-174, 1962.

Wen Fang (S90) was born in Shanghai, PeoplesRepublic of China, on July 11, 1956. He re-ceived the B.S. degree in physics from FudanUniversity, China, in 1982, and the M.S. degreein electrical engineering from the Shanghai In-stitute of Metallurgy, the Chinese Acaiemy ofSciences, in 1985 He joined the Institute in1985 working in the areas of 16-b microproces-sor design, four-chip IC development for colorTV receivers, three-chip IC testing for B/W TVreceivers, and high-speed CMOS static RAMcircuit simulation. In October 1987 he received a grant from the ChineseAcademy of Sciences. He is currently working towards the Ph.D. degreeat Southampton University, Southampton, England, in the field ofhigh-speed bipolar circuits including ECL and CML gate optimization,high-speed frequency divider simulation, and BiCMOS circuit modeling.Mr. Fang is the recipient of the British Overseas Research StudentAwards for the session 1989/1990

Arthur Brunnschweiler (M82) was born inManchester, England, in 1936. He received theB.A. degree from Cambridge University in 1956,the M.S. degree from Pennsylvania State Uni-versity in 1960, and the Ph.D. degree from theUniversity of Manchester Institute of Scienceand Technology in 1966.From 1960 to 1964 he was employed in theCamera Tube Research Department of the En-glish Electric Valve Company, Chelmsford, Eng-land, and since 1966 he has been on the aca-demic staff of Southampton University, Southampton, England, wherehe is currently Senior Lecturer in the Department of Electronics andComputer Science. His research and teaching interests include mostareas of microelectronics, particularly device and circuit design. He hasacted as consultant to several industrial companies and his presentduties include the management of the Microelectronics Industrial Unitat Southampton University.



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FANG et al.: ANALYTICAL MAXIMUM TOGGLE FREVUENCY EXPRESSION 931Peter Ashburn (M89) was born in Rotherham,England, in 1950 He received the B S degreein electrical and electronic engineering in 1971and the Ph D degree in 1974, both from theUniversity of Leeds His dissertation topic wasan experimental and theoretical study of rddia-tion damage in silicon p-n junctionsIn 1974 he joined the technical staff of thePhilips Research Laboratories, Redhill, dndworked on ion-implanted bipolar integrated-cir-cult transistors In 1976 he was transferred to a

project on electron lithography, and studied the processing problemsencountered when the electron image projector was used to fabricateintegrated circuits. In 1978 he joined the academic staff of the Electron-ics Department of Southampton University, Southampton, England. Hi5present areas of research are the physics of polysilicon emitter bipolartransistors, heterojunction bipolar transistors, and device technology forhigh-speed bipolar integrated circuits.Dr. Ashburn is a member of the IEE.

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