FPSLIC STK594 User Guide - Digi-Key Sheets/Atmel PDFs/ATSTK594 Use… · Introduction 1-2 FPSLIC...

FPSLIC STK594..............................................................................................

User Guide

FPSLIC STK594 User Guide

Table of Contents

Section 1Introduction ........................................................................................... 1-1

Section 2Using the STK594 Top Module............................................................. 2-1

2.1 Preparing the STK500 for Use with the STK594.......................................2-1

2.1.1 Adjusting VTARGET for the AT94K Devices......................................2-1

2.1.2 Connecting the STK594 to the STK500 Starter Kit ............................2-1

2.2 PORT Connectors.....................................................................................2-2

2.2.1 PORT E ..............................................................................................2-2

2.3 Programming the AT94K Devices.............................................................2-32.4 JTAG Connector .......................................................................................2-32.5 TOSC Switch.............................................................................................2-42.6 Universal Asynchronous Receiver Transmitter (UART)............................2-4

2.6.1 Second RS-232C Port ........................................................................2-4

2.7 Two-Wire Serial Interface (TWSI) .............................................................2-5

2.7.1 Description of Configuration Memory Pins .........................................2-5

2.8 External Interrupts.....................................................................................2-52.9 Split Power Supply Support ......................................................................2-62.10 XTAL Switch .............................................................................................2-62.11 Reset Switches .........................................................................................2-6

Section 3Installing System Designer ................................................................... 3-1

3.1 System Requirements...............................................................................3-13.3 Configuration Programming System (CPS) Installation ............................3-23.4 System Designer Licensing.......................................................................3-2

3.4.1 Requesting a System Designer License.............................................3-2

3.4.2 Configuring the System Designer License .........................................3-3

3.4.3 Testing the System Designer License ................................................3-3

3.4.4 Troubleshooting..................................................................................3-3

Section 4Using System Designer ........................................................................ 4-1

4.1 Preparing the Example Files .....................................................................4-14.3 Design Flow ..............................................................................................4-24.6 Synthesizing the FPGA Source File..........................................................4-84.8 FPGA Place and Route...........................................................................4-11

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Table of Contents

FPSLIC STK594 User Guide

4.10.1 Hardware Setup................................................................................4-15

4.10.2 Software Setup .................................................................................4-16

Section 5Technical Specifications ....................................................................... 5-1

Section 6Complete Schematics........................................................................... 6-1

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Section 1

Introduction

The STK594 board is a top module designed to add AT94K FPSLIC® support to theSTK500 development board. With this board the STK500 is extended to support all cur-rent AT94K FPSLIC devices in a single development environment.

The STK594 includes connectors, jumpers and hardware allowing full utilization of thenew features of the FPSLIC family, see Figure 1-1.

This user guide acts as a general getting started guide as well as a complete technicalreference for advanced users.

In addition to adding support for new devices, it also adds new support for peripheralspreviously not supported by the STK500. An additional RS-232 port and a Two-WireSerial Interface are among the new features.

Figure 1-1. STK594 Top Module for STK500

FPSLIC STK594 User Guide 1-1

Rev. 2819D–FPSLI–11/04

Introduction

1.1 Features STK500 Compatible

AVR Studio® and System Designer Compatible

Supports AT94KAL and AT94KAX Devices

Supports all Added Features in FPSLIC Devices

JTAG Connector for On-chip Debugging Using JTAG ICE

Additional RS-232C Port with Available RTS/CTS Handshake Lines

On-board 32 kHz Crystal for Easy RTC Implementations

1-2 FPSLIC STK594 User Guide

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Section 2

Using the STK594 Top Module

2.1 Preparing the STK500 for Use with the STK594

Prior to using the STK594 with the STK500, it is necessary to make a few adjustmentsto the STK500 Starter Kit to allow for proper operation of Atmel’s AT94K FPSLIC®

devices.

2.1.1 Adjusting VTARGET for the AT94K Devices

According to the AT94K Series datasheet, the VCC operating voltage is specified where{VCC | 3.0 < VCC = 3.6} Volts, with respect to ground. The STK594 board requires thatthe STK500 board supplies a VCC within the operating range for the AT94K devices.Prior to using the STK594 board, it is necessary to adjust the VTARGET to a valuebetween 3.0 and 3.6V. For more information on adjusting VTARGET from within AVRStudio®, consult section 5.3.5.1 of the STK500 User Guide, available on the Atmel website (www.atmel.com).Note: It may be necessary to adjust the VDD voltage, see “Split Power Supply Support”

on page 6 of this section for more information.

2.1.2 Connecting the STK594 to the STK500 Starter Kit

The STK594 should be connected to the STK500 expansion header 0 and 1. It is impor-tant that the top module is connected in the correct orientation as shown in Figure 2-1on page 2. The EXPAND0 written on the STK594 top module should match theEXPAND0 written beside the expansion header on the STK500 board.




Figure 2-1. Connecting the STK594 to the STK500 Board

Note: Connecting the STK594 with the wrong orientation may damage the boards.

Note: Do not mount the STK594 at the same time an AVR® is mounted on the STK500 board.

2.2 PORT Connectors

Since the AT94K devices have additional ports not available on the STK500, these portsare located on the STK594 board. The STK594 ports have the same pinout and func-tionality as the ports on the STK500 board. Since Port A to Port D are already presenton the STK500 board, they are not duplicated on the STK594.

2.2.1 PORT E Figure 2-2 shows the pinout for the I/O port headers Port E.

Figure 2-2. General I/O Ports

Note: Port E is also present on the STK500, but only PE0 to PE2 (3 least significant bits) are accessible. To access all Port E bits the connector on the STK594 must be used.

PE1PE3PE5PE7VTG

PE0PE2PE4PE6

GND

1 2

PORT E


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2.3 Programming the AT94K Devices

The FPSLIC configuration process involves configuring the FPGA, the AVR® programcode and the FPSLIC data memory. This configuration requires a single bitstream thatconfigures the FPGA, the embedded AVR Program SRAM and the FPSLIC DataSRAM. The combined bitstream is automatically generated by the Bitstream Generator,a System Designer software utility.

After a reset and the internal clearing of the configuration data, the FPSLIC device self-initiates configuration. The Master mode uses an internal oscillator to provide the Con-figuration Clock (CCLK) for clocking the external EEPROM (configurator), whichcontains the configuration data. After auto-configuration is complete, re-configurationcan be initiated manually by the user, if needed.

Note: The AT94K devices also support Self-Programming. For more information on this topic, refer to the “Code-Self Modify” application note available on the Atmel web site.

Note: The AT94K devices also support Cache Logic® Configuration. For more infor-mation on this topic, refer to the “Cache Logic Configuration” application note available on the Atmel web site.

For more details on programming procedures, refer to Section 4.10.

2.4 JTAG Connector The JTAG connector is intended for the AT94K devices that have a built-in JTAG inter-face. The pinout of the JTAG connector is shown in Figure 2-3 and is compliant with thepinout of the JTAG ICE available from Atmel. Connecting a JTAG ICE to this connectorallows On-chip Debugging of the AT94K devices.

More information about the JTAG ICE and On-chip Debugging can be found in the AVRJTAG ICE user guide, available on the Atmel web site.

Figure 2-3. JTAG Connector

Note: To determine if your AT94K device supports JTAG Debug, examine the date code. Any parts with a J after their date code support JTAG. Example, 4201J.

Figure 2-4 shows how to connect the JTAG ICE probe on the STK594 board.

Figure 2-4. Connecting JTAG ICE to the STK594

GNDVTGRSTN/CGND

TCKTDOTMSVTGTDI

1 2

JTAG


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2.5 TOSC Switch The AT94K device provides dedicated I/O pins for TOSC1 and TOSC2, rather thansharing with the general purpose I/O pins. The TOSC switch selects whether or not the32 kHz crystal is connected to the pins of the device.

Figure 2-5 shows a simplified block schematic on how this is implemented.

Figure 2-5. TOSC Block Schematic

2.6 Universal Asynchronous Receiver Transmitter (UART)

Unlike traditional AVR microcontrollers, the AT94K device provides the option of havingseparate I/O pins for the UARTs rather than sharing with the general purpose I/O pins.

Figure 2-6 shows the pinout of a header for the dedicated UART pins.

Figure 2-6. UART Header

2.6.1 Second RS-232C Port

The AT94K device has an additional UART. The RS-232 port on the STK594 board hasin addition to the RXD and TXD lines support for RTS and CTS flow control. Figure 2-7shows a simplified block schematic on how this is implemented.

Note: The UART in AT94K devices does not support hardware RTS or CTS control. If such functionality is needed, it must be implemented in software.

Figure 2-7. UART Block Schematic

This UART can also be used from devices placed in the STK500 board. Simply connectthe appropriate port pins to RXD and TXD on the STK594 board.

Note: If no software RTS/CTS flow control is implemented, a jumper shorting RTS and CTS will ensure correct communication with an external application that uses such flow control.

TOSC1

TOSC2

32 kHz

TOSCSwitch

FPSLIC

TX0TX1

RX0RX1

1 2

UART

RxD TxD

CTS RTS

RS-232/Logic LevelConverter

8

7

3

2

4

6

5RS

232

SPA

RE

2


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2.7 Two-Wire Serial Interface (TWSI)

The AT94K device includes dedicated I/O pins for the TWSI rather than sharing with thegeneral purpose I/O pins.

Figure 2-8 shows the pinout of a header for the dedicated TWSI pins.

Figure 2-8. TWSI Header

2.7.1 Description of Configuration Memory Pins

An AT17LV010-10CC 1-Mbit Configuration Memory is included on the STK594 for sup-plying the AT94K FPSLIC device with its configuration data, as well as for non-volatiledata storage. The configurator is a high-density EEPROM with a TWSI interface. Adetailed datasheet of the Configuration Memory can be obtained from the Atmel website.

The configurator can be connected to the I/O pins of the embedded AVR microcontrol-ler. The 4-pin header marked CONFIG can be used for connecting the TWSI interface ofthe configurator to the I/O pins of the target AVR microcontroller. Two-wire cables areincluded with the STK500 for connecting the configurator to the I/O pins.

Figure 2-9 shows the pinout of a header for the Configuration Memory pins.

Figure 2-9. Configuration Memory Header

2.8 External Interrupts

Unlike traditional AVR microcontrollers, the AT94K device provides the option of havingseparate I/O pins for the External Interrupts rather than sharing with the general purposeI/O pins.

Figure 2-10 shows the pinout of a header for the dedicated External Interrupt pins.

Figure 2-10. External Interrupt Header

SCLSDA1 2

TWSI

cSCLN/C

cSDAcSER_EN

1 2

CONFIG

INTP1INTP3

INTP0INTP2

1 2

EXT


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2.9 Split Power Supply Support

The AT94K FPSLIC devices exist in two different variations, the AL and AX. The ALvariation is a 3.3V device manufactured on a 0.35µ process, while the AX variation hasa 1.8V core manufactured on a 0.18µ process. The primary difference between the twovariations, is that the AX device requires a split power supply, as the I/Os are still pow-ered from a 3.3V supply, while the core operates at 1.8V.

The STK594 supports both AT94K variations. If an AX variant is being used it is neces-sary to supply the proper core to the AT94K device. Figure 2-11 shows how to set thejumper to select the core voltage.

Figure 2-11. AT94K Core Voltage Selector

2.10 XTAL Switch An oscillator is included on the STK594 for supplying an additional clock to the AT94KFPSLIC device. The XTAL switch selects if the oscillator is connected to the XTAL1 pin,or whether the clock is provided by the STK500.

Figure 2-12 shows a simplified block schematic on how this is implemented.

Figure 2-12. XTAL Block Schematic

2.11 Reset Switches The reset switch found on the STK594 is connected to the AT94K’s RESET pin. Whenpressed, the AT94K device will reset and initiate a configuration download from the con-figuration memory.

The reset switch found on the STK500 is connected to the AVRRESET. When pressed,the embedded AVR microcontroller resets and begins execution at location $0000.

AL

AX

AT94KAX

AL

AX

AT94KAL

VDD VDD

XTAL2

XTAL1 XT1

FPSLIC

XT2

OSC


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Section 3

Installing System Designer

System Designer is the ideal software platform for all AT94K FPSLIC® development. Itincludes an Editor, an Assembler and a Debugger as its development tools for theembedded AVR® development, and also includes a Simulator, Synthesizer and a Placeand Route tool for FPGA development. System Designer also includes a Co-Verificationsuite powered by Mentor Graphics®, allowing for step-by-step simulation of the FPGAand AVR design concurrently.

3.1 System Requirements

For a single-user system, System Designer requires a personal computer equipped asfollows:

CD-ROM Drive

250-Mbyte Minimum Hard Drive

128-Mbyte RAM

Parallel Interface Port

Windows® 95/98/2000/Me, or WindowsNT® 4.0

Network Interface Card or Security Dongle

The software security dongle is used to generate a unique HOSTID for systems withouta network interface card. The security dongle is connected to the PC through theparallel port interface. It is possible to configure a floating network license through thesecurity dongle. The security dongle allows users to use the software dongle on differentmachines by removing and placing the dongle on other machines.




3.2 System Designer Installation

This installation assumes that you have no previous version of System Designerinstalled in your machine. If you have a previous version of the software installed or youneed step-by-step installation instructions, please refer to the System Designer “Installa-tion, Licensing and Troubleshooting” tutorial available on the Atmel web site.

1. Insert the supplied System Designer CD-ROM into the computer. If the CD does not automatically start, execute SETUP.EXE from the CD.

2. From the CD Browser, select Install Products and select System Designer. The System Designer installation will perform a full installation, as there are no optional components.

Note: Do not install System Designer to a directory name that contains spaces, other-wise improper opperation will occur.

Note: When you reach the portion of the System Designer installation prompting about licensing, you should select one of two options, either Custom or Skip. Select Custom if you already have a valid license and follow the instructions outlined in Section 3.4.2 “Configuring the System Designer License”. Choose Skip if you do not have a license and follow the instructions in Section 3.4.1 “Requesting a System Designer License”.

Note: AVR Studio® version 3.2 or higher is required for STK500/STK594 support.

3.3 Configuration Programming System (CPS) Installation

From the CD Browser, select Install Products and select CPS for AT17 Devices. Thiswill install the CPS utility, which is used to program the AT17 and ATFS series configu-ration memories found on the STK594.

Note: When installing the CPS utility, it is necessary to install the software in an account with Administrator privileges if the operating system is WindowsNT or Windows 2000/XP.

3.4 System Designer Licensing

The licensing of System Designer is for the Mentor Graphics tools. You can use SystemDesigner without a valid license, however you will not be able to use ModelSim®,LeonardoSpectrum™ or Co-Verification.

The typical license is based on the hostID of your Network Interface Card (NIC). If youprefer to use a dongle-based license, it is necessary that you purchase a Security Don-gle from Atmel (Atmel Part Number: ATDH94DNG).

The instructions below describe the configuration of a NIC-based license. If you requesta dongle-based license, you will receive instructions on how to configure the license withthe dongle. If you wish to use a single license for multiple machines, it is necessary topurchase a Security Dongle.

3.4.1 Requesting a System Designer License

Prior to obtaining a license for System Designer, it is necessary to first install the SystemDesigner software suite. During installation, System Designer creates the fileLMUTIL.TXT, which is found in the C:\SystemDesigner\ETC directory, assuming adefault installation. The LMUTIL.TXT file contains the hostID of your NIC, and is com-posed of a combination of twelve alphanumeric characters.

Once you have installed System Designer, proceed to the FPSLIC section of the Atmelweb site and click on the Request License button, alternatively the direct link for thelicense request page is http://www.atmel.com/atmel/products/prod39r.htm.

Note: The Serial Number is located on the white sticker on the underside of the STK594 board or on the System Designer case.


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3.4.2 Configuring the System Designer License

1. Once you have received your System Designer license from Atmel, place the file in the C:\SystemDesigner directory.

2. Launch the Mentor Graphics License Configuration Utility from Start > Programs > Atmel > Mentor Graphics Licensing > Configure Licensing.

3. Follow the on-screen instructions. When it prompts you to select Configuration Option, choose 3.

4. Define the Product License Location and press Next. Use the full path and file-name when defining the license location, for example C:\SystemDesigner\fpslic.dat. If you used a different path and/or file-name, make the necessary changes.

Note: If you are using Windows 95/98/Me it is necessary to reboot the machine prior to running the System Designer software.

3.4.3 Testing the System Designer License

Once you have configured your license, you can test it by invoking the Mentor Graphicsprograms that require a license.

1. Launch ModelSim from Start > Programs > Atmel > ModelTech > ModelSim. If ModelSim launches without any licensing errors, the ModelSim license has been successfully installed.

2. Launch LeonardoSpectrum from Start > Programs > Atmel > Leonardo Spec-trum > Leonardo Spectrum. If LeonardoSpectrum launches without any licensing errors, then the LeonardoSpectrum license has been successfully installed.

3.4.4 Troubleshooting You can access the trouble shooting guide from Start > Programs > Atmel > TroubleShooting Guide.


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Section 4

Using System Designer

This tutorial will guide you through the required steps for designing and programmingAT94K series devices using System Designer.

4.1 Preparing the Example Files

Before starting the tutorial, a few preparations need to be performed:

1. Download STK594.ZIP from the FPSLIC® software page of the Atmel web site and copy STK594.ZIP to C:\SystemDesigner\Designs.

2. Extract the contents of the STK594.ZIP file to C:\SystemDesigner\Designs.The contents of the zip file are shown in Table 4-1.

Table 4-1. STK594.ZIP

File Description

AT94KDEF.INC Atmel AVR Assembler AT94K FPSLIC Include File

COUNTER.PIN FPGA Pin Lock File

COUNTER.V Top Level FPGA Verilog® Counter Source File

COUNTER.VHD Top Level FPGA VHDL Counter Source File

STK594.ASM Atmel AVR Assembler Source File

COUNTER.ATT FPGA I/O Attribute File




4.2 Description The design in this tutorial is composed of a simple AVR® microcontroller program and aloadable counter implemented in the FPGA. When the counter reaches the terminalvalue, an interrupt to the microcontroller will be generated using the counter’s carry-out(RCO) signal. The interrupt is active Low and must be held for three clock cycles prior toits acknowledgement by the microcontroller. During the Interrupt Service Routine (ISR)the microcontroller increments the count of interrupt occurrences and places the incre-mented data on PORTD and the AVR-FPGA Data Bus, triggering the counter’s LOADsignal. Once the counter has been loaded, counting will commence and the process willbe repeated. Figure 4-1 shows a simplified block diagram of the tutorial design.

Figure 4-1. Tutorial Design Block Diagram

4.3 Design Flow The design presented in this tutorial, only performs the required steps for designing andprogramming an AT94K series device. For more information on the optional steps (i.e.Simulation and Co-verification) please consult the FPSLIC application notes availableon the Atmel web site. Figure 4-2 outlines the design flow followed in this tutorial. Formore information on a specific step, consult the appropriate section within this tutorial.

Figure 4-2. Design Flow

IOSELA0

IOSEL A0

INTA0

GCLK5

AVRMicrocontroller

FPGA Interrupt 0

Global Clock 5

LOAD

ENABLE D[7:0]

RESET

Q

RCO

CLOCK

AVR Data Bus 8-bit

FPGA8-bit Counter

FIOWEAaWE AVR Write EnableFPGA I/O SELECT 0

PORTD

MicrocontrollerAssembly

HDL Synthesis

AVR <> FPGAInterface

FPGAPlace & Route

BitstreamGeneration


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4.4 Creating a Project

The New Project Wizard allows you to choose your Project Directory, Target Device,and desired Tool Flow.

1. Launch System Designer from the desktop icon, or by pointing to Start > Pro-grams > Atmel > SystemDesigner.

2. Create a new project by selecting New from the Project menu and then pressing the New Project Wizard button, see Figure 4-3.

Figure 4-3. New Project Wizard Window - Step 1 of 6

3. Press Next. The window to create a project file opens, see Figure 4-4.



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4. Set the Project Directory to C:\SystemDesigner\Designs\STK594, name the project TUTORIAL and press Next. The part selection window appears, see Figure 4-5.


5. Select AT94K10AL-25DQC(1) from the parts list as this is the part found on the STK594 development board, and press Next. The software tool flow window opens, see Figure 4-6.

Note: 1. Some boards use AT94K40AL-25DQC devices.



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6. Select either Mentor - VHDL or Mentor - Verilog as the Tool Flow and press Next. The add parts window opens, see Figure 4-7. For this tutorial, the instructions will assume Mentor - Verilog has been selected.



7. Press Finish to exit the New Project Wizard. The project window now contains the TUTORIAL design, see Figure 4-9.


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Figure 4-9. Project Window

8. From the System Designer desktop, click on the Part Graphic (see Figure 4-9) to switch to the Design Flow Manager, see Figure 4-10.


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Figure 4-10. Design Flow Manager

The Design Flow Manager shows the steps available for designing with Atmel FPSLICdevices. The red and blue arrows show the dependencies between the various stagesof development. This tutorial will only show the minimum steps in order to complete adesign. The remainder of the steps involves simulation and co-verification. For furtherinformation on simulation and co-verification, please consult the “Quick Start Tutorial”available on the Atmel web site.


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4.5 Assembling the Microcontroller Source Code

The Atmel AVR Assembler translates assembly source code into object code. The gen-erated object code can then be used as an input to a simulator, emulator such as theAtmel AVR JTAG In-Circuit Emulator (ICE), or used to program the target device. TheAssembler generates fixed code allocations, therefore no linking is necessary.

1. Press the SW Compiler button to open the Atmel AVR Studio®.

2. Click on N0 when prompted to create a new file. The window to open an existing file opens up.

3. Browse to the C:\SystemDesigner\Designs\STK594 directory and select STK594.ASM.

Figure 4-11. Open File stk594.asm

4. Press Build and close the Atmel AVR Studio if assembly was successful.

Note: If assembly was not successful, make sure the include file AT94KDEF.INC is in the design directory. Only AT94K devices with a “J” label support JTAG ICE debugging.

For design entry using assembly language, consult the AT94K datasheet for a summaryof instructions supported by the FPSLIC devices. The complete “AVR Instruction SetNomenclature” describes each instruction in detail and has been installed as part of theSystem Designer Tool. The AVR Instruction Set Nomenclature and FPSLIC datasheetcan be accessed from the Help menu (from the System Designer window) and choosingOnline Resources.

4.6 Synthesizing the FPGA Source File

1. Synthesis translates the VHDL or Verilog source code into gate-level technology-specific file for use with the target FPGA Place and Route tool.

2. Press the Synthesis Tool button. A dialog box to add VHDL files appears, see Figure 4-12.

Figure 4-12. Add VHDL Files Dialog Box


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3. Press yes. A file selection window appears.

4. Select COUNTER.V and press Open. LeonardoSpectrum opens.

5. Leonardo® automatically selects Atmel AT94K as the Technology and lists COUNTER.V under Input. Leonardo also lists COUNTER.edf under Output.

6. Press Run Flow. Figure 4-13 shows a successful synthesis.

Figure 4-13. Leonardo Spectrum, Successful Synthesis

7. Close Leonardo Spectrum, when prompted to save your project press No.


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4.7 AVR-FPGA Interface

The AVR-FPGA Interface dialog provides a means for making the connections betweenthe embedded FPGA and AVR microcontroller.

1. Press the AVR-FPGA Interface button.

2. Select counter and press OK when prompted for Top-Level Entity. The Select Ports dialog appears, see Figure 4-14.

Figure 4-14. Select Ports Dialog

3. Select the AVRIoSelects tab on the right-hand side of the dialog box.

4. Select the LOAD signal from the Input Design Ports and then select IOSELA0 from the AVRIoSelects.

5. Press Connect to connect the counter's LOAD signal to FPGA-AVR I/O Select 0.

6. Connect the remaining inputs and outputs as shown in Table 4-2.

7. Uncheck Generate Template Test Bench File on the bottom left-hand side of the Select Ports dialog. Since we are not performing co-verification, it is not neces-sary to generate the pre-layout test bench file.

8. Press OK.

Table 4-2. FPGA-AVR Interface Connections

FPGA I/O FPGA-AVR I/O Select Ports Tab

LOAD IOSELA0 AVRIoSelects

RCO INTA0 FPGAInterrupts

D(7:0) ADINA(7:0) DataFromAVR

aWE FIOWEA AVRControls

Clock GCLK5 FPGAClocks


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4.8 FPGA Place and Route

The Figaro Integrated Development System (IDS) is used as the FPGA Place & Routetool. Figaro takes the gate-level technology-specific file generated by the synthesis tooland partitions, places, and routes the FPGA design.

1. Press the Figaro IDS button to open the FPGA Place & Route Tools Settings dia-log, see Figure 4-15.

Figure 4-15. FPGA Place & Route Tools Settings Dialog

2. Select Open EDIF Netlist and Browse to select COUNTER.edf, then press OK. Figaro should open and complete the Open, Map, and Parts steps automatically, once completed the Figaro Batch Options dialog appears, see Figure 4-16.

Figure 4-16. Figaro Batch Options Dialog

The Figaro Batch Options allows for the setting of various Figaro FPGA compilerconstraints. This includes I/O Pin Locking, I/O Pad Attributes and Place & Routequality effort levels.


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Design Constraints

a. Press Import Constraints, this opens the Import Constraints window. Select Part/pinout(*.pin) from the List files of the Type drop-down list. (Alternatively, we could have used the Assign Pin Locks GUI to perform the pin locking, but it is not required for this design.)

b. Select COUNTER10.PIN and press OK.

Note: If the board is soldered with the AT94K40AL-25DQC device, select COUNTER40.PIN and press OK.

c. Press Import Constraints again, select IO Pad Attr (*.att) from the List files of the Type drop-down list and then select the COUNTER.ATT and press OK.

Place and Route

a. Use the default setting for Quality. Quality sets the trade-off between Figaro’s speed and the efficiency of the Place & Route result, see the online help for further information.

b. Use the default setting for Timing Driven Design. Checking the Timing Driven Design box allows Figaro to take account of critical paths when per-forming the Place & Route, see the online help for further information.

c. Press Compile, once completed the Figaro IDS Compile button will turn green.

d. Select Exit from the File menu, when prompted to save your design select Yes.


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4.9 Bitstream Generation

The Device Programming Utility takes the outputs from both the FPGA and AVR compil-ers, and generates a single programming file for use in configuring the AT94K device.

1. Press Device Programming Utility to open the programming utility. The FPSLIC Control Register Settings dialog opens, see Figure 4-17.

Figure 4-17. FPSLIC Control Register Settings Dialog

2. Check the Include FPGA Bitstream box and select COUNTER.BST by pressing Browse.

3. Check the Include AVR Hex File box and select STK594.HEX by pressing Browse.

4. Select the FPSLIC Control Register Settings tab and use the default settings, see Figure 4-18.

5. Be sure to uncheck the Program Configurator option under the Bitstream Down-load section of the FPSLIC Control Register Settings tab.


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Figure 4-18. Control Register Settings Dialog

6. Press OK to generate the combined bitstream file.

Note: It is possible to generate a bitstream for only the FPGA or AVR as you may only want to program that portion of the FPSLIC device. To include only the AVR HEX file, simply uncheck the Include FPGA Bitstream box. Programming only the FPGA portion can be done in a similar fashion.


2819D–FPSLI–11/04


4.10 Programming and Design Execution

The programming file generated by the Bitstream Generator is used to program the con-figuration memory. When the FPSLIC requests configuration data after a Reset orPower-On-Reset, the data is clocked out serially.

4.10.1 Hardware Setup Before programming the configurator and verifying the tutorial design, a few prepara-tions need to be performed prior to its execution on hardware.

1. Connect the PC’s parallel port to the 25-pin connector of the ATDH2225 Pro-gramming Dongle.

2. Connect the 10-pin ISP header on the STK594 to the 10-pin ribbon cable of the ATDH2225. The ATDH2225 is keyed to assure proper orientation, see Figure 4-19.

Figure 4-19. In-System Programming

3. Place the Programming switch in the PROG position.

4. Using a 10-wire ribbon cable from the STK500, connect PORTD to the LEDS.

5. Using a 2-wire cable from the STK500, connect SW0 and SW1 to FPSLIC pins 177 and 178, respectively.

6. Connect the Power Supply from an AC outlet to the power connector on the STK500 development board.

7. Turn on the STK500.

Note: Prior to providing power to the STK500 development board it is necessary to adjust the VTARGET supplied by the STK500 to the STK594, for more informa-tion on this adjustment please refer to Section 2.1.1.


2819D–FPSLI–11/04


4.10.2 Software Setup The CPS utility allows for the programming, reading, and verification of data. CPS sup-ports Atmel’s AT17F, ATFS and AT17LV series of configuration memories.

1. Launch CPS from Start > All Programs > Atmel > CPS8.xx (where xx represents the version).

Figure 4-20. CPS

2. Select /P: Partition, program, and verify from an Atmel file under Procedure.

3. Select FPSLIC_COUNTER.BST under Input File by browsing to C:\SystemDesigner\Designs\stk594.

4. Select OUT.BST under Output File.

5. Select AT17LV010(A) (1M) under Device.

6. Select Low under Reset Polarity.

7. Select AT40K/Cypress under FPGA Family.

8. Select LPT1 under COMM Port (assuming LPT1 is the parallel port connected to the ATDH2225 programming adapter).

9. Select Slow under Data Rate.

10. Select Low under A2 Bit Level.

11. Press Start Procedure. When finished a statistics report will be provided in the CPS log window.

Note: If the CPS utility is being launched for the first time, the clock calibration dialog will be displayed. Press Yes to proceed with calibration and select High for accurate calibration. The Checksum is the number of data bits found in the BST file, and it can be used to check if the data is corrupted during programming.


2819D–FPSLI–11/04


4.11 Running the Design

Once programming has completed, it is necessary to move the ProgrammingSwitch to the RUN position for configuration of the FPSLIC device to occur. If theLEDs on the STK500 begin to count, the configuration has occurred. If the configu-ration does not occur, press the RESET button found on the STK594 board toinitiate a configuration download. Alternatively, power-cycling the STK500 will alsoinitiate a configuration download.


2819D–FPSLI–11/04



2819D–FPSLI–11/04

Section 5

Technical Specifications

System UnitPhysical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5.125” x 2.75”

Weight . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 oz.

Operating ConditionsVoltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC = 3.3V, VDD = 1.8/3.3V

ConnectionsSerial Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-pin D-SUB Female

Serial Communications Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 kbps



Technical Specifications


2819D–FPSLI–11/04

Section 6

Complete Schematics

See the following pages the complete schematics and assembly drawings of theSTK594.



Co

mp

lete Sch

ematics

6-2

281

1

1

D

C

B

A

72 Rev A

Sheet 1of 6

FP

SL

IC S

TK

594 User G

uid

e

9D–F

PS

LI–11/04

5

5

4

4

3

3

2

2

D

C

B

A

CHW54

ATSTK594 : Clock Circuitry

Friday, April 26, 2002

Title

ASize Document Number

Date:

XTAL1

XTAL2

XT1

XT2

TOSC1

TOSC2

XTAL1

XTAL2

XT1

XT2

TOSC1

TOSC2

C227 pF

SW1

SW DPDT

21

3

54

6

SW2

SW DPDT

21

3

54

6

R2

10M

Y2

OSC8

5 OUT

C133 pF

R1200K

Y1

32.768 kHz

Complete Schematics

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

52 Pin connectors are double rows of Probe

pins, 26x2 on each side of the chip.

Add Labels to connectors

every 10 pins. Labels should match chip pin numbers

up to 208

GCK1

LCD

HCD

CH

W5

45

44

FP

SLI

C C

onne

ctio

ns

C

26

Thu

rsda

y, M

ay 2

3, 2

002

Aut

hor

= W

endy

Loc

khar

t

Tit

le

Siz

eD

ocum

ent

Num

ber

Rev

Dat

e:S

heet

of

GN

D GN

D

GN

DV

DD

GN

D

OT

S

GN

D

VCCGCK8

GND

VDDGND

GND

GND

CS1

VC

C

VD

DG

ND

GN

D

VC

C

RE

SE

T

XT

AL2

XT

AL1

TO

SC

1T

OS

C2

cSD

A

cSC

L

GCK7

INT

P3

TX1

RX

1

INT

P2

INT

P1

TX0

RX

0

INT

P0

SC

LS

DA

PE

T1

PE

T2

PE

T3

PE

T4P

ET5

PE

T6P

ET7

PE

T[7

..0]

PD

T6

PD

T5

PD

T4

PD

T3

PD

T7

PD

T2

PE

T0

PD

T1

PD

T0

PD

T[7

..0]

GC

K2

RS

T

GND

GCK3

CON

TDI

TCK

M0

INITVDD

TDO

GCK4

GND

VCC

GND

M2

TMS

GND

RS

T

TD

IT

DO

TM

ST

CK

INIT

CO

N

GC

K2

GC

K1

GC

K3

GC

K4

RE

SE

T

XT

AL2

XT

AL1

TO

SC

1T

OS

C2

cSC

L

cSD

A

GC

K7

GC

K8

INT

P3

INT

P2

INT

P1

INT

P0

RX

0TX

0

RX

1TX

1

SC

LS

DA

PE

T[7

..0]

PD

T[7

..0]

VC

C

VC

CV

CC

VC

CV

CC

VD

DV

DD

VD

DV

DD

U2

AT

94K

10-2

5DQ

C

6 7 10 11 51

606162

8 91 2 3 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 52

535455

575859

63

56

646566676869707172737475767778798081828384858687888990919293949596979899100101102103104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148

149

150

151

152

153

154

155

156

157

54

158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208

I/O

I/O

I/O

I/O

NC

I/OI/OLDC/TDO (I/O)

I/O

I/O

NC

GN

DN

C

I/O

I/O

GN

DF

CK

1 (I

/O)

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GN

DV

DD

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

FC

K2

(I/O

)G

ND

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

OT

S (

I/O

)G

CK

2 (I

/O)

AV

RR

ES

ET

GN

DM

0

NC

NCNCVCC

GCK3 (I/O)HDC/TDI (I/O)I/O

I/O

M2

I/OI/OI/OGNDI/OI/OTMS (I/O)TCK (I/O)I/OI/OI/OI/OI/OINIT (I/O)VDDGNDI/OI/OI/OI/OI/OI/OI/OI/OI/OI/OGNDI/OI/OI/OI/OI/OI/OI/OI/OI/OGCK4 (I/O)GNDNCCONNC

NC

VC

CN

CR

ES

ET

PE

0P

E1

PD

0P

D1

PE

2P

D2

NC

NC

NC

NC

NC

PD

3P

D4

PE

3C

S0

SD

AS

CL

PD

5P

D6

PE

4P

E5

VD

DG

ND

PE

6P

E7

(CH

EC

K)

PD

7IN

TP

0N

CN

CX

TA

L1X

TA

L2R

X0

TX

0G

ND

NC

NC

INT

P1

INT

P2

TO

SC

1T

OS

C2

RX

1T

X1

D0

INT

P3

(CS

OU

T)

CC

LKV

CC

NC

NC

NC

I/O

GC

K1

(I/O

)

NCTESTCLOCK

GNDI/O

GCK7 (I/O)I/OI/O

CS1 (I/O)I/OI/OI/OI/OI/O

GNDI/OI/OI/OI/OI/OI/OI/OI/OI/OI/O

GNDVDD

I/OI/OI/OI/OI/OI/OI/OI/OI/OI/O

GNDI/OI/OI/OI/OI/OI/OI/OI/OI/O

GCK8 (I/O)VCC

NCNCNC

C8

0.1

uF

CO

N52

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52

PIN

1P

IN2

PIN

3P

IN4

PIN

5P

IN6

PIN

7P

IN8

PIN

9P

IN10

PIN

11P

IN12

PIN

13P

IN14

PIN

15P

IN16

PIN

17P

IN18

PIN

19P

IN20

PIN

21P

IN22

PIN

23P

IN24

PIN

25P

IN26

PIN

27P

IN28

PIN

29P

IN30

PIN

31P

IN32

PIN

33P

IN34

PIN

35P

IN36

PIN

37P

IN38

PIN

39P

IN40

PIN

41P

IN42

PIN

43P

IN44

PIN

45P

IN46

PIN

47P

IN48

PIN

49P

IN50

PIN

51P

IN52

CO

N52

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152

PIN157PIN158PIN159PIN160PIN161PIN162PIN163PIN164PIN165PIN166PIN167PIN168PIN169PIN170PIN171PIN172PIN173PIN174PIN175PIN176PIN177PIN178PIN179PIN180PIN181PIN182PIN183PIN184PIN185PIN186PIN187PIN188PIN189PIN190PIN191PIN192PIN193PIN194PIN195PIN196PIN197PIN198PIN199PIN200PIN201PIN202PIN203PIN204PIN205PIN206PIN207PIN208

C4

0.1

uF

R3

2K7

CO

N52

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152

PIN53PIN54PIN55PIN56PIN57PIN58PIN59PIN60PIN61PIN62PIN63PIN64PIN65PIN66PIN67PIN68PIN69PIN70PIN71PIN72PIN73PIN74PIN75PIN76PIN77PIN78PIN79PIN80PIN81PIN82PIN83PIN84PIN85PIN86PIN87PIN88PIN89PIN90PIN91PIN92PIN93PIN94PIN95PIN96PIN97PIN98PIN99

PIN100PIN101PIN102PIN103PIN104

C5

0.1

uFC

30.

1 uF

C7

0.1

uFC

100.

1 uF

C9

0.1

uF

C6

0.1

uF


2819D–FPSLI–11/04

Complete Schematics

5 5

4 4

3 3

2 2

1 1

DD

CC

BB

AA

CH

W54

72

STK5

94 :

Hea

ders

Title

Siz

e B

Doc

umen

t Num

ber

Rev

A

Frid

ay, A

pril

26, 2

002

Dat

e:Sh

eet 3

of 6

GN

DG

ND

GN

DG

ND

PC

T[7.

.0]

TCK

GN

D

PE

T[7.

.0]

cSD

A

TXD

RXD

RTS

INTP

0IN

TP1

RX0

TX0

cSC

LcS

ER

_EN

SDA

SCL

TOS

C2

PET1

GN

D

PBT6

PET2

VA

DJ

PCM

1

PCM

7

PBT0

PBT4

GN

D

DC

KT

PCT4

PET0

PCT5

INTP

2

TX1

PDT2

PBM

2

XT1

PBM

1

PAT0

PCM

4

PDT4

PCT0

PCT6

PAT1

PCT1

VTG

VTG

TDI

DC

ST

GN

D

PBT7

PAT2

PCM

0

PCM

6AU

X_I0

PET7

PBM

0

PDT3

PBM

3

VTG

PE

T[2.

.0]

PB

T[7.

.0]

PBM

6

PDT1

PDT7

PBT5

GN

D

RST

GN

D

AR

EFT

PCT7

PCM

3

VTG

VTG

INTP

3

DS

IT

PET0

PET6

PET4

TMS

PDT0

PDT6

PDT5

PBT3

PBM

5

PAT7

PET5

GN

D

PBM

4

AUX_

O1

PET3

PET2

PBM

7

PCT2

PCM

2

RST

PB

M[7

..0]

GN

D

DSO

T

PAT6

GN

D

AUX_

O0

PD

T[7.

.0]

PA

T[7.

.0]

TDO

VTG

VTG

GN

D

PAT3

PAT5

PCT3

RX1

PBT2

GN

DPE

T1

PCM

5

PC

M[7

..0]

PBT1

PAT4

XT2

AUX_

I1

AU

X_O

[1..0

]

AU

X_I

[1..0

]

TOSC

1

CTS

RX

DTX

DR

TS

PE

T[7.

.0]

PE

T[2.

.0]

PC

M[7

..0]

PCT[

7..0

]

PA

T[7.

.0]

PDT[

7..0

]

PB

T[7.

.0]

PB

M[7

..0]

TOSC

2TO

SC1

SCL

SD

A

RS

T

TCK

TDO

TMS

TDI

AU

X_I

[1..0

]

AU

X_O

[1..0

]

cSC

L

CTS

cSD

AcS

ER

_EN

DS

OT

DC

STXT

2

DS

ITD

CKT

XT1

VA

DJ

RS

TA

RE

FT

INTP

1IN

TP3

INTP

0IN

TP2

TX0

TX1

RX0

RX1

VC

CV

CC

VC

CV

TG

VC

C

VC

C

J13

CO

N2A

12

J11

CO

N4A

1 32 4

J4 CO

N40

A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

C12

0.1

uF

J5 CO

N40

A

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39

2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

J10

CO

N4A

1 32 4

J12

CO

N2A

12

C13

0.1

uFC

110.

1 uF

J9 CO

N4A

1 32 4

J8 CO

N4A

1 32 4

J6 CO

N10

A

1 3 5 7 9

2 4 6 8 10

J7 CO

N10

A

1 3 5 7 9

2 4 6 8 10

R4

2K7


2819D–FPSLI–11/04

Co

mp

lete Sch

ematics

FP

1

1

D

C

B

A

ircuitry

Rev A

Sheet 4 of 6

VCC

J14

CON10A

13579

2468

10

SL

IC S

TK

594 User G

uid

e6-5

2819D–F

PS

LI–11/04

5

5

4

4

3

3

2

2

D

C

B

A

A

STK594 : In-System Programming CTitle

Size CHW5472Document Number

Friday, April 26, 2002Date:

CON

RESET

GND

cSCL

INIT

D0

SER_EN

CCLK

cSER_EN

cSDA cSDA

RESET

cSCL

INITcSER_EN

CONVCC

VCCVCC

VCC

SW4 C150.1 uF

SW3

SW 4PDT

11

65

4

12

3

98

21

7

10

U2

AT17LV010/LAP

12

3

4

67

DATACLK

RESET/OE

CE

CEOSER_EN

D1

1N4001

1 2

R52K7

R74K7

C140.003 uF

R62K7

CCLK D0

Co

mp

lete Sch

ematics

6-6

281

1

1

D

C

B

A

Rev A

Sheet 5 of 6

FP

SL

IC S

TK

594 User G

uid

e

9D–F

PS

LI–11/04

5

5

4

4

3

3

2

2

D

C

B

A

GND VCC VDD

VOUT

VCCVDD

VCC VOUTVCC VDD VOUT

TP1

T POINT F

1

J15

CON3

123

C1610 uF

TP2

T POINT F

1TP3

T POINT F

1

C1710 uF

U3

LT1117-1.8/SOT

1

23

ADJ/GND

VOUTVIN

A

STK594 : Split Power Rail CircuitryTitle



Co

mp

lete Sch

ematics

FP

1

1

D

C

B

A

GNDP1

CONNECTOR DB9

594837261

ircuitry

472 Rev A

Sheet 6 of 6

SL

IC S

TK

594 User G

uid

e6-7

2819D–F

PS

LI–11/04

5

5

4

4

3

3

2

2

D

C

B

A

CTSRXD

TXDRTS

CTSRXD

TXDRTS

VCC

VCC

C220.1 uF

U4

MAX3232

138

1011

1345

26

129

147

R1INR2IN

T2INT1IN

C1+C1-C2+C2-

V+V-

R1OUTR2OUT

T1OUTT2OUT

C210.1 uF

C180.1 uF

C200.1 uF

C190.1 uF

A

STK594 : RS-232 Spare #2 CTitle



Complete Schematics


2819D–FPSLI–11/04

ATMEL CONFIDENTIAL

2819D–FPSLI–11/04 /xM

Printed on recycled paper.

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to anyintellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORYWARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULARPURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUTOF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes norepresentations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specificationsand product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are notintended, authorized, or warranted for use as components in applications intended to support or sustain life.

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FPSLIC STK594 User Guide - Digi-Key Sheets/Atmel PDFs/ATSTK594 Use… · Introduction 1-2 FPSLIC...

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Transcript of FPSLIC STK594 User Guide - Digi-Key Sheets/Atmel PDFs/ATSTK594 Use… · Introduction 1-2 FPSLIC...