FPGA VALIDATION OF EVENT-DRIVEN...
Transcript of FPGA VALIDATION OF EVENT-DRIVEN...
![Page 1: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/1.jpg)
FPGA VALIDATION OF EVENT-DRIVEN ADPLL
1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING, UNIVERSITY COLLEGE DUBLIN, IRELAND
2LIP6, SORBONNE UNIVERSITY PARIS, FRANCE
Eugene Koskin1, Pierre Bisioux1, Dimitri Galayko2, and Elena Blokhina1
![Page 2: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/2.jpg)
Outline:
• Motivation
• The model of an event-driven PLL
• Structural blocks of the PLL
• Noise modeling
• Transient response
• Phase portraits
• Conclusions
![Page 3: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/3.jpg)
Motivation:
• Need for synchronisation in several fields of science and engineering, including power networks, IoT,
semiconductor laser arrays, brain networks, chemical oscillations and others.
• Clock generators in microprocessor engineering.
![Page 4: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/4.jpg)
Schematic diagram
Block diagram of an ADPLL that includes the digital time detector, the loop filter,the frequency divider, the reference clock and DCO.
![Page 5: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/5.jpg)
Digital Time Detector
Block diagram of the implemented DTD and the schematic of the 10-bit TDC.
![Page 6: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/6.jpg)
Digitally Controlled Oscillator
Block diagram of the inverter ring used as the DCO, with a 6-bit input DCOin and 5-bit output LOC.
![Page 7: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/7.jpg)
Noise measurements
DCO’s properties: (a) Dependence of period standard deviation on its average; (b) PDF for normalised periods.
![Page 8: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/8.jpg)
Measured step response of the ADPLL on the reference signal for several value of PIC parameters.
![Page 9: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/9.jpg)
Phase Portraits
![Page 10: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/10.jpg)
Phase Portraits
![Page 11: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/11.jpg)
Phase Portraits
![Page 12: FPGA VALIDATION OF EVENT-DRIVEN ADPLLecctd2020.eu/d8/sites/default/files/upload/presentations/...FPGA VALIDATION OF EVENT-DRIVEN ADPLL 1SCHOOL OF ELECTRICAL AND ELECTRONIC ENGINEERING,](https://reader036.fdocuments.us/reader036/viewer/2022081403/609c17371665fe573e751db5/html5/thumbnails/12.jpg)
Conclusions:
We studied dynamical properties of an event-driven ADPLL through FPGA modelling and compared the results with the theoretical model developed in recent works.
• We showed that the FPGA model stays in a very good agreements with theoretical predictions. This was supported by comparison of the ADPLL behaviour in the frequency acquisition and stationary regimes.
• We demonstrated that ADPLL is out of control when the ratio Ki/Kp > 0.5. Below that value, ADPLL locks to the reference signal having jitter depending on the control parameters.
• The measurements of the slope in the transient regime showed that the frequency acquisition rate depends mostly on Ki and does not depend on Kp. Such a frequency acquisition rate can be used as a constraint for an optimisation problem aimed to minimise the timing error.