FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Chapter 2: VLSI Technology...

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design

Transcript of FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR Chapter 2: VLSI Technology...

Page 1: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Chapter 2: VLSI Technology

Tahir Muhammad

Lecture 2

FPGA-Based System Design

Page 2: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Topics

Combinational logic functions. Static complementary logic gate structures. Switch logic. Non-standard gate structures.

Page 3: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Combinational logic expressions

Combinational logic: function value is a combination of function arguments.

A logic gate implements a particular logic function.

Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

Page 4: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Gate design

Why designing gates for logic functions is non-trivial:– may not have logic gates in the libray for all

logic expressions;– a logic expression may map into gates that

consume a lot of area, delay, or power.

Page 5: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Boolean algebra terminology

Function:f = a’b + ab’

a is a variable; a and a’ are literals. ab’ is a term. A function is irredundant if no literal can be

removed without changing its truth value.

Page 6: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Completeness

A set of functions f1, f2, ... is complete iff every Boolean function can be generated by a combination of the functions.

NAND is a complete set; NOR is a complete set; {AND, OR} is not complete.

Transmission gates are not complete. If your set of logic gates is not complete, you

can’t design arbitrary logic.

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Static complementary gates

Complementary: have complementary pullup (p-type) and pulldown (n-type) networks.

Static: do not rely on stored charge. Simple, effective, reliable; hence

ubiquitous.

Page 8: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Static complementary gate structure

Pullup and pulldown networks:

pullupnetwork

pulldownnetwork

VDD

VSS

outinputs

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Inverter

a out

+

Page 10: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

NAND gate

+

ba

out

Page 11: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

NOR gate

+

b

a

out

Page 12: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

AOI/OAI gates

AOI = and/or/invert; OAI = or/and/invert. Implement larger functions. Pullup and pulldown networks are compact:

smaller area, higher speed than NAND/NOR network equivalents.

AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

Page 13: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

AOI example

out = [ab+c]’:

symbol circuit

and

or

invert

Page 14: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Pullup/pulldown network design

Pullup and pulldown networks are duals. To design one gate, first design one

network, then compute dual to get other network.

Example: design network which pulls down when output should be 0, then find dual to get pullup network.

Page 15: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Dual network construction

dum

my

a

b c

dummy

a

b c

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Switch logic

Can implement Boolean formulas as networks of switches.

Can build switches from MOS transistors—transmission gates.

Transmission gates do not amplify but have smaller layouts.

Page 17: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Switch logic network

a

b

0

1

a b out

0 0 X

0 1 1

1 0 0

1 1 X

Page 18: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Another switch logic network

a

b

r

s

a b out

0 0 X

0 1 r

1 0 s

1 1 X

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Switch-based mux

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Types of switches

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Behavior of n-type switch

n-type switch has source-drain voltage drop when conducting:– conducts logic 0 perfectly;– introduces threshold drop into logic 1.

VDD

VDD

VDD - Vt

Page 22: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

n-type switch driving static logic

Switch underdrives static gate, but gate restores logic levels.

VDD

VDD

VDD - Vt

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

n-type switch driving switch logic

Voltage drop causes next stage to be turned on weakly.

VDD VDD - Vt

VDD

Page 24: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Behavior of complementary switch

Complementary switch products full-supply voltages for both logic 0 and logic 1:– n-type transistor conducts logic 0;– p-type transistor conducts logic 1.

Page 25: FPGA-Based System Design: Chapter 2 Copyright  2003 Prentice Hall PTR Chapter 2: VLSI Technology Tahir Muhammad Lecture 2 FPGA-Based System Design.

FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Charge sharing

Values are stored at parasitic capacitances on wires:

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

Charge sharing example

1

1

00 0

1 1

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

DCSL gate

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FPGA-Based System Design: Chapter 2 Copyright 2003 Prentice Hall PTR

MTCMOS gate