Four-Instruction CPUImplementing each instructionBelow are the RTN statements and the control sequences for each of the four instructions:

Fetch (for ALL instructions):T0: MAR PC PC_out, MAR_inT1: read, PC PC + 1 read, PCincrT2: IR MDR MDR_out, IR_inT3: NOP Time to decode the opcode

Load:T4: MAR IR IR_out, MAR_inT5: read readT6: ACC MDR MDR_out, ACC_in, reset timer to T0

Add:T4: MAR IR IR_out, MAR_inT5: read readT6: TEMP ACC+MDR aluaddT7: ACC TEMP TEMP_out, ACC_in, reset timer to T0

Store:T4: MAR IR IR_out, MAR_inT5: MDR ACC ACC_out, MDR_inT6: write write, reset timer to T0

Branch on 0:T4: if ACC=0 PC IR if acceq0 then IR_out, PC_inT5: reset timer to T0

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Review sample 4-instruction CPU from last class. See web pages for the data path and the Register Transfer Notation instructions for the four instructions.

If we look at the 14 control signals side-by-side, we have a 14-bit word that can be considered an "instruction" – a micro-instruction.The microinstructions for the fetch part of the instruction cycle would look like this:Fetch (for ALL instructions):

T0: MAR PC PC_out, MAR_inT1: read, PC PC + 1 read, PCincrT2: IR MDR MDR_out, IR_inT3: NOP Time to decode the opcode

1 2 3 4 5 6 7 8 9 10 11 12 13 14

ACC_

in

ACC_

out

Alua

dd

IR_in

IR_o

ut

MAR

_in

MDR

_in

MDR

_out

PC_in

PC_o

ut

PC_in

cr

Read

TEM

P_ou

t

Writ

e0 0 0 0 0 1 0 0 0 1 0 0 0 0

0 0 0 0 0 0 0 0 0 0 1 1 0 0

0 0 0 1 0 0 0 1 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0 0 0 0 0

We can consider each of the above 14-bit lines as an "instruction".We can write each one of these register-transfer "instructions" as a string of 14 0s and 1s.We can write the steps for each machine-language instruction as a series of 14-bit numbers (micro-instructions) and store them in a control memory in the CPU.If we derive ALL of the 14-bit numbers corresponding to ALL of the micro-instructions for all four instructions, we find that there are:

4 micro-instructions to implement the FETCH part of each instruction 3 micro-instructions to implement the LOAD instruction 4 micro-instructions to implement the ADD instruction 3 micro-instructions to implement the STORE instruction 2 micro-instructions to implement the BRZ instruction

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This is a total of 16 different micro-instructions. That means we can store all of the micro-instructions in a 16x14 memory. However, we are going to add 6 bits to each micro-instruction:

1 bit for a "branch via table" control signal 4 bits for the address of the next instruction 1 bit for "OR address with acceq"

How this is implemented:The "Control Store Address Register" is a 4-bit number that holds the address of a micro-instruction. The 4-bit address is passed through a 4x16 decoder that will select one of the 16 memory cells. This memory cell is copied into the Control Store Instruction Register.

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This micro-program never changes. Therefore, we will only read from the control memory. This can be implemented just like the memory cells from chapter 3, except that there are 4 select lines (to select 1 of 16 cells) at the bottom instead of 2 (to select 1 of 4 cells). And there are 20 Output lines instead of 3. Note that we do not need input lines because data cannot be written to this memory; it can only be read. So we also do not need a write-enable line.

The OUTPUT lines from this memory cell are always connected to the Control Store Instruction Register. And on each tick of the clock, the selected memory cell will be loaded into the Control Store Instruction Register. Each bit in the Control Store Instruction Register is connected to the corresponding control point (see the first figure). Since each bit in the Control Store Instruction Register is connected directly to the corresponding control point, the appropriate registers will have their data transferred.The four address bits of the instruction are connected to the Control Store Address Register, so the address of the next instruction is automatically loaded into the Control Store Address Register. So on each tick of the clock, the appropriate control signals are sent.

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