Flip-Flops & Latches*This presentation willReview sequential logic and the flip-flop.Introduce the D flip-flop and provide an excitation table and a sample timing analysis.Introduce the J/K flip-flop and provide an excitation table and a sample timing analysis.Review flip-flop clock parameters.Introduce the transparent D-latch.Discuss flip-flop asynchronous inputs.

Sequential Logic & The Flip-Flop*

D Flip-Flop: Excitation Table*

DCLK001110

: Rising Edge of Clock

D Flip-Flop: Example Timing*Q=D=1Q=D=1Q=D=0Q=D=1No ChangeQ=D=0No ChangeQ=D=0No ChangeQ=D=0

Q

D

CLK

J/K Flip-Flop: Excitation Table*

JKCLK00No Change010Clear101Set11Toggle

: Rising Edge of Clock

J/K Flip-Flop: Example Timing*SETCLEARTOGGLENOCHANGETOGGLENOCHANGESET

Q

J

K

CLK

Clock Edges*

1

0

1

0

POS & NEG Edge Triggered D*Positive Edge TriggerNegative Edge Trigger

DCLK001110

: Rising Edge of Clock

DCLK001110

: Falling Edge of Clock

POS & NEG Edge Triggered J/K*Positive Edge TriggerNegative Edge Trigger

JKCLK0001010111 : Rising Edge of Clock

JKCLK0001010111 : Rising Edge of Clock

Flip-Flop Timing*Setup Time (tS): The time interval before the active transition of the clock signal during which the data input (D, J, or K) must be maintained.

Hold Time (tH): The time interval after the active transition of the clock signal during which the data input (D, J, or K) must be maintained.

Data Input(D,J, or K)1

0tS Setup TimetH Hold TimePositive EdgeClock1

0

*Asynchronous InputsAsynchronous inputs (Preset & Clear) are used to override the clock/data inputs and force the outputs to a predefined state.The Preset (PR) input forces the output to:

The Clear (CLR) input forces the output to:

PRPRESETCLRCLEARCLKCLOCKDDATA110011111001XX10Asynchronous Preset10XX01Asynchronous Clear00XX11ILLEGAL CONDITION

D Flip-Flop: PR & CLR Timing*Q=1PresetQ=D=0ClockedQ=D=0ClockedQ=1PresetQ=D=0ClockedQ=0ClearQ=D=1ClockedQ=D=1ClockedQ=D=1Clocked

Q

PR

CLR

D

CLK

Transparent D-Latch*EN: Enable

END0X10011110

Transparent D-Latch: Example Timing*

Q

D

EN

Flip-Flop Vs. LatchThe primary difference between a D flip-flop and D latch is the EN/CLOCK input. The flip-flops CLOCK input is edge sensitive, meaning the flip-flops output changes on the edge (rising or falling) of the CLOCK input. The latchs EN input is level sensitive, meaning the latchs output changes on the level (high or low) of the EN input.

*

Flip-Flops & Latches*74LS74 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear, and Complementary Outputs74LS76 Dual Negative-Edge-Triggered J-K Flip-Flops with Preset, Clear, and Complementary Outputs74LS75 Quad Latch

74LS74: D Flip-Flop*

74LS76: J/K Flip-Flop*

74LS75: D Latch*

Flip-FLops and LatchesFlip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesIntroductory Slide / Overview of Presentation

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesDefinition of sequential logic. Sequential logic can have one or more, inputs and one or more outputs. However, the outputs are a function of both the present value of the inputs and also the previous output values. Thus, sequential logic requires memory to store these previous outputs values.

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesSchematic symbol and excitation table for the D flip-flop.Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesTiming diagram example for a D flip-flop.Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesSchematic symbol and excitation table for the J/K flip-flop.

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesTiming diagram example for a J/K flip-flop.

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesFlip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesSchematic symbol and excitation table for the positive edge triggered and negative edge triggered D flip-flops

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesSchematic symbol and excitation table for the positive edge triggered and negative edge triggered J/K flip-flops

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesDefinition of the Setup & Hold Time timing parameters for a flip-flop.Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesDefinition for the PR (preset) and CLR (clear) Asynchronous input for a D flip-flop.Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesTime diagram showing the effects of the synchronous inputs (D & CLK) and asynchronous inputs (PR & CLR).Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesSchematic symbol and excitation table for the D latch.

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesTime diagram example for a transparent D-latch.

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesThis slide details the primary difference between the often confused D flip-flop and D latch.Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesSummary of the two flip-flops and one latch that we will be using in this course.Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesDatasheet excerpts for a 74LS74 D flip-flop.Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesDatasheet excerpts for a 74LS76 J/K flip-flop.

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009Flip-FLops and LatchesDatasheet excerpts for a 74LS75 D latch.

Flip-FLops and LatchesDigital Electronics TM 3.1 Introduction to Flip-FlopsProject Lead The Way, Inc.Copyright 2009*Project Lead The Way, Inc.Copyright 2009