Brief Introduction:

A digital clock is a type of clock that displays the time digitally, i.e. in ciphers, as opposed to an analog clock, where the time is displayed by hands. Usually, digitally clocks are associated with electronic drives whereas; analog clocks are driven mechanically or electronically. Digital clocks typically use the 50 or 60 hertz oscillation of AC power or a crystal oscillator as in a quartz clock to keep time. Most digital clocks display the hour of the day in 24 hour format

23:59:59Problem Statement:

The main purpose is to simulate the working of digital clock over Modelsim or any other simulator using VHDL (VHSIC hardware description language. It consists of 6 seven segment displays. Each pair is used for second, minute and hour respectively. There is one MOD 60 synchronous counter for seconds, one MOD 60 synchronous counter for minutes and one MOD 24 synchronous counter for hour. MOD 60 counters consist of one MOD 10 counter and one MOD 6 counter. MOD 24 counter consists of one MOD 10 counter and one MOD 3 counter. Output of each counter is fed to seven segment display.

Alarm - The alarm is operated by comparing the output of the seven segment code to input given by the user. If both match, the alarm bit changes to 1.

Circuit Design –

1. Mod 10 Counter –

Output of a Mod 10 counter

2. Mod 6 Counter –

Output of a Mod 6 counter

3. Mod 3 Counter –

4. Basic Block diagram for digital clock –

Implementation Issues -

When second counter completes 60 stages it sends an enable signal to the minute counter and similarly when minute counter completes its 60 stages (ie.00 to 59) it enables the hour counter. When hour counter completes 24 stages (ie.00 to 23), it resets all counters to 00.

To actually see the seconds, then the output of the counters needs to drive a display. The two counters produce binary numbers. The divide-by-10 counter is producing a 0-1-2-3-4-5-6-7-8-9 sequence on its outputs, while the divide-by-6 counter is producing a 0-1-2-3-4-5 sequence on its outputs.

The alarm is activated by comparing the output of the clock [hours and minutes only] to input given by the user. If both match, the alarm bit changes to 1.

VHDL code for Mod 10 counter –

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mod10 is Port (clk : in STD_LOGIC; reset : in STD_LOGIC; y: inout STD_LOGIC_vector(3 downto 0)); end mod10;

architecture Behavioral of mod10 is

begin

process (reset, clk)

begin

if reset ='1' then y<="0000";

elsif clk'event and clk='0' then if y = "1001" then y<="0000" ; else y<=y+1; end if;

else y<=y; end if;end process;end Behavioral;

VHDL code for Mod 6 counter –

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mod6 is Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC; y : inout STD_LOGIC_VECTOR (2 downto 0)); end mod6;

architecture Behavioral of mod6 is

begin

process (clk,reset)

begin if reset ='1' then y<="000" ; elsif clk'event and clk ='0' then if y="101" then y<="000" ; else y<=y+1;

end if;

else y<=y;end if ;end process; end Behavioral;

VHDL code for Mod 3 counter –

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity mod3 is Port (clk : in STD_LOGIC; reset : in STD_LOGIC; y: inout STD_LOGIC_vector(1 downto 0)); end mod3;

architecture Behavioral of mod3 is

begin

process (reset, clk)

begin

if reset ='1' then y<="00";

elsif clk'event and clk='0' then if y = "11" then y<="00" ; else y<=y+1; end if;

else y<=y; end if;end process;end Behavioral;

VHDL code for seven segment display -

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;entity display is Port ( i : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (6 downto 0)); end display;

architecture Behavioral of display is

beginprocess (i)begin if i="0000" then y<="1111110" ;

elsif i= "0001" then y<="0110000" ; elsif i= "0010" then y<="1101101" ; elsif i="0011" then y<="1111001" ; elsif i="0100" then y<="0110011" ;

elsif i="0101" then y<="1011011" ; elsif i="0110" then y<="1011111" ; elsif i="0111" then y<="1110000" ; elsif i="1000" then y<="1111111" ; else y<="1111011" ; end if; end process;

end Behavioral;

VHDL Code for digital clock with alarm –

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity digitalalarmclock is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC;

insec1:in std_logic_vector(3 downto 0); insec2:in std_logic_vector(2 downto 0); inmin1:in std_logic_vector(3 downto 0); inmin2:in std_logic_vector(2 downto 0); inhour1:in std_logic_vector(3 downto 0); inhour2:in std_logic_vector(1 downto 0);

inminalrm1:in std_logic_vector(3 downto 0); inminalrm2:in std_logic_vector(2 downto 0); inhouralrm1:in std_logic_vector(3 downto 0); inhouralrm2:in std_logic_vector(1 downto 0);

sec1 : inout STD_LOGIC_VECTOR (3 downto 0); sec2 : inout STD_LOGIC_VECTOR (2 downto 0); min1 : inout STD_LOGIC_VECTOR (3 downto 0);

min2 : inout STD_LOGIC_VECTOR (2 downto 0); hour1 : inout STD_LOGIC_VECTOR (3 downto 0); hour2 : inout STD_LOGIC_VECTOR (1 downto 0); secd1 : out STD_LOGIC_VECTOR (6 downto 0); secd2 : out STD_LOGIC_VECTOR (6 downto 0); mind1 : out STD_LOGIC_VECTOR (6 downto 0); mind2 : out STD_LOGIC_VECTOR (6 downto 0); hourd1 : out STD_LOGIC_VECTOR (6 downto 0); hourd2 : out STD_LOGIC_VECTOR (6 downto 0); sout: out STD_LOGIC; output:out std_logic); end digitalalarmclock;

architecture Behavioral of digitalalarmclock is

component mod10 Port (clk : in STD_LOGIC; reset : in STD_LOGIC; y: inout STD_LOGIC_vector(3 downto 0)); end component;

component mod3 Port (clk : in STD_LOGIC; reset : in STD_LOGIC; y : inout STD_LOGIC_VECTOR (1 downto 0)); end component;

component mod6 Port (clk : in STD_LOGIC; reset : in STD_LOGIC; y : inout STD_LOGIC_VECTOR (2 downto 0)); end component; component display5 Port (i : in STD_LOGIC_VECTOR (2 downto 0); y : out STD_LOGIC_VECTOR (6 downto 0)); end component; component display Port (i : in STD_LOGIC_VECTOR (3 downto 0); y : out STD_LOGIC_VECTOR (6 downto 0)); end component;

component display2 Port (i : in STD_LOGIC_VECTOR (1 downto 0); y : out STD_LOGIC_VECTOR (6 downto 0)); end component;

signal s1,s2,s3,s4,s5,s6,s7:std_logic;

component and1 Port (a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end component;

component or1 Port (a : in STD_LOGIC; b : in STD_LOGIC; c : out STD_LOGIC); end component;

begin

a1:mod10 port map(clk,reset,sec1);

a2:mod6 port map(sec1(3),reset,sec2);

a3:mod10 port map(sec2(2),reset,min1);

a4:mod6 port map(min1(3),reset,min2);

a5:and1 port map(hour1(2),hour2(1),s1);

a6:or1 port map(s1,reset,s2);

a16:mod10 port map(min2(2),s2,hour1);

a7:mod3 port map(hour1(3),s2,hour2);

a8:display port map(sec1,secd1);

a9:display5 port map(sec2,secd2);

a10:display port map(min1,mind1);

a11:display5 port map(min2,mind2);

a12:display port map(hour1,hourd1);

a13:display2 port map(hour2,hourd2);

process(insec1,insec2,inmin1,inmin2,inhour1,inhour2,sec1,sec2,min1,min2,hour1,hour2 ,inminalrm1,inminalrm2,inhouralrm1,inhouralrm2) begin

if insec1=sec1 and insec2=sec2 and inmin1=min1 and inmin2=min2 and inhour1=hour1 and inhour2=hour2 then output<='1';else output<='0';end if; if inminalrm1=min1 and inminalrm2=min2 and inhouralrm1=hour1 and inhouralrm2=hour2 then sout<='1';

else sout<='0';

end if;end process;

end Behavioral;

Snapshots –

References –

Following is the list of books from which help has been taken for the completion of this project.

1 VHDL-PRIMER J.Bhasker

2 MODERN DIGITAL ELECTRONICS R.P.Jain

3 DIGITAL DESIGN MorisMano

Web References –

VHDL Tutorials - esd.cs.ucr.edu/labs/tutorial/

VHDL examples - www.vhdl.org/vhdlsynth/vhdlexamples/