FIFO Quiz 1

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2/16/15, 10:34 PM quiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design Page 1 of 4 https://sjsu.instructure.com/courses/1137028/quizzes/1060926 Attempt History Attempt Time Score LATEST Attempt 1 10 minutes 8.27 out of 10 quiz3 FIFOs and paths Due Feb 18 at 10pm Points 10 Questions 10 Available until Feb 18 at 10:30pm Time Limit 30 Minutes Allowed Attempts 2 Score for this attempt: 8.27 out of 10 Submitted Feb 16 at 10:33pm This attempt took 10 minutes. Take the Quiz Again 0.67 / 1 pts Question 1 Which of the following are important to ASIC product success? Select all that apply. Customer documentation Correct! Correct! performance Correct! Correct! Marketing definition Correct! Correct! Package color debug Correct Answer Correct Answer power Correct! Correct! factory yield Correct! Correct! simulation time schedule Correct! Correct! Internal documentation Correct Answer Correct Answer Test patterns Correct Answer Correct Answer 1 / 1 pts Question 2 Which terms are part of the long path equation? IH Skew Correct! Correct! LD Correct! Correct!

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FIFO Quiz EE287

Transcript of FIFO Quiz 1

  • 2/16/15, 10:34 PMquiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

    Page 1 of 4https://sjsu.instructure.com/courses/1137028/quizzes/1060926

    Attempt History Attempt Time ScoreLATEST Attempt 1 10 minutes 8.27 out of 10

    quiz3 FIFOs and pathsDue Feb 18 at 10pm Points 10 Questions 10 Available until Feb 18 at 10:30pm Time Limit 30 Minutes Allowed Attempts 2

    Score for this attempt: 8.27 out of 10Submitted Feb 16 at 10:33pmThis attempt took 10 minutes.

    Take the Quiz Again

    0.67 / 1 ptsQuestion 1

    Which of the following are important to ASIC product success? Select all that apply.

    Customer documentation Correct!Correct!

    performance Correct!Correct!

    Marketing definition Correct!Correct!

    Package color

    debug Correct AnswerCorrect Answer

    power Correct!Correct!

    factory yield Correct!Correct!

    simulation time

    schedule Correct!Correct!

    Internal documentation Correct AnswerCorrect Answer

    Test patterns Correct AnswerCorrect Answer

    1 / 1 ptsQuestion 2

    Which terms are part of the long path equation?

    IH

    Skew Correct!Correct!

    LD Correct!Correct!

  • 2/16/15, 10:34 PMquiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

    Page 2 of 4https://sjsu.instructure.com/courses/1137028/quizzes/1060926

    C->Q Correct!Correct!

    IS Correct!Correct!

    1 / 1 ptsQuestion 3

    Which terms are part of the race equation?

    Skew Correct!Correct!

    IH Correct!Correct!

    IS

    LD Correct!Correct!

    C->Q Correct!Correct!

    1 / 1 ptsQuestion 4

    Which edge of the clock is the best to use?

    The one everyone else is using Correct!Correct!

    The one with the best flip-flops

    Falling

    Rising

    Falling to construct ripple counters

    1 / 1 ptsQuestion 5

    A FIFO is typically constructed using a memory with how many ports?

    5

    2 Correct!Correct!

    3

    1

    4

  • 2/16/15, 10:34 PMquiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

    Page 3 of 4https://sjsu.instructure.com/courses/1137028/quizzes/1060926

    0 / 1 ptsQuestion 6

    A long path fails with only one clock pulse

    False

    True You AnsweredYou Answered

    0.6 / 1 ptsQuestion 7

    Other Incorrect Match Options:Mono-stable multi-vibratorslave-slavemaster-master

    Pick the best match for the list below:

    1/2 Flip Flop Mono-stable multi-vibratorYou AnsweredYou Answered

    Latch Correct AnswerCorrect AnswerCorrect Answer

    Flip Flop Master-Slave Correct AnswerCorrect!Correct!

    Reset Asynchronous Correct AnswerCorrect!Correct!

    Slave delay C->Q Correct AnswerCorrect!Correct!

    Glitch Memory Latch Correct AnswerYou AnsweredYou Answered

    J-K Flip Flop Correct AnswerCorrect AnswerCorrect Answer

    1 / 1 ptsQuestion 8

    A FIFO is a synchronizer.

    False

    True Correct!Correct!

  • 2/16/15, 10:34 PMquiz3 FIFOs and paths: SP15: EE-287 Sec 02 - ASIC CMOS Design

    Page 4 of 4https://sjsu.instructure.com/courses/1137028/quizzes/1060926

    1 / 1 ptsQuestion 9

    If all the transistors are the same sizes, which gate is faster?

    MUX

    XOR

    NOR

    NAND Correct!Correct!

    1 / 1 ptsQuestion 10

    In a CMOS NAND gate, the N transistors are arranged:

    Congruence

    In mirror image

    Binary weighted

    Series Correct!Correct!

    Parallel

    Quiz Score: 8.27 out of 10


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Gisselquist - ZipCPU · 2020-05-17 · Design Goal Lesson Overview Ź Design Goal What is a FIFO? Basic FIFO Design method FIFO Interface FIFO Memory Addresses Formal Verification

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FIFOs with BRAMs (FIFO 3) - University of Southern California · PDF filerepresent FULL or EMPTY. Or we use two (n+1)-bit ... and if the Register-based FIFO (the small FIFO) has extra

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