Digital Systems

Topic 13: An Example Design Problem

28/18/2010

Objectives• To work through an entire design problem:

– Review specifications– Derive state diagram– Build state table and assign states– Decide the number of state variables needed– Choose technology– Implement the design

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38/18/2010

Design Description/Specifications• Design a Sequence Detector:

– Implement the design as a Finite State Machine • Input (w) • Output (z)

– Z = 1 if the previous two values of w were 00 or 11– Z = 0 otherwise

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48/18/2010

FSM Design Steps1. Obtain the specifications of the desired circuit2. Derive the states of the machine and develop a state

diagram1. Should show all possible states2. Provide the conditions for which the circuit moves from one state to

the next

3. Develop the state table from the state diagram4. Decide on the number of state variables needed to

represent all states1. Minimize the number of states if possible

5. Choose the type of flip-flops that will be used in the implementation

1. Derive the next-state logic expressions to develop the Input Logic Circuit

2. Derive the logic expressions for the Output Logic Circuit

6. Implement the design

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58/18/2010

FSM Design Steps1. Obtain the specifications of the desired circuit2. Derive the states of the machine and develop a state

diagram1. Should show all possible states2. Provide the conditions for which the circuit moves from one state to

the next

3. Develop the state table from the state diagram4. Decide on the number of state variables needed to

represent all states1. Minimize the number of states if possible

5. Choose the type of flip-flops that will be used in the implementation

1. Derive the next-state logic expressions to develop the Input Logic Circuit

2. Derive the logic expressions for the Output Logic Circuit

6. Implement the design

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68/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

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78/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

In this state, the output must equal 0, because there have been no pulses detected on w

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88/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

w could be a 0 or a 1. Depending on which it is, the FSM should go to the next state (B or D).

Let B be the “start counting 0s state” and D be the “start counting 1s state. There have not been 2 0s or 2 1s, so z = 0.

z = 0 z = 0

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98/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

If the next w is 0, we go to state C. We now have 2 0s, so z should go high.

But, if w=1, we need to start counting 1s, so we go to state D

C

w = 1w = 0

z = 0 z = 0

z = 1

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108/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

From this point on, if w=0, we should stay in state C and z should be high

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

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118/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

From this point on, if w=0, we should stay in state C and z should be high

If w should go high, we need to start counting 1s (state D)

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1

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128/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

If at any point w=1, we want to start counting 1s (go to state D). If the next w is also 1, we go to state E and z should go high.

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

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138/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

If at any point w=1, we want to start counting 1s (go to state D). If the next w is also 1, we go to state E and z should go high.

But, if the next w = 0, then we need to start counting 0s (go to state B).

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

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148/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

If w continues to be 1, we need to stay in state E and z needs to remain high.

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

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158/18/2010

State Diagram• Start with the state diagram

– State A: Reset (or Starting) state

A

Reset

z = 0

B D

w = 1w = 0

If w continues to be 1, we need to stay in state E and z needs to remain high.

But, if w = 0, we need to start counting 0s (go to state B).

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

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168/18/2010

FSM Design Steps1. Obtain the specifications of the desired circuit2. Derive the states of the machine and develop a state

diagram1. Should show all possible states2. Provide the conditions for which the circuit moves from one state to

the next

3. Develop the state table from the state diagram4. Decide on the number of state variables needed to

represent all states1. Minimize the number of states if possible

5. Choose the type of flip-flops that will be used in the implementation

1. Derive the next-state logic expressions to develop the Input Logic Circuit

2. Derive the logic expressions for the Output Logic Circuit

6. Implement the design

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178/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

0

If we are in state A, z should be low, and w could be 0 or 1

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188/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

BD

0

If w = 0, we go to state B

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198/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

BD

0

If w = 1, we go to state D

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208/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

BD

B

0

0

If we are in state B, z should be 0, and w could be high or low

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218/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

BD

CD

B

0

0

If w = 0, we should go to state C

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228/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

BD

CD

B

0

0

If w = 1, we should go to state D

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238/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

01

BD

CD

B

C

0

0

1

If we are in state C, z should be high, and w could be 0 or 1

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248/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

01

BD

CD

B

C CD

0

0

1

If we are in state C, and w=0, we should stay in state C

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258/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

01

BD

CD

B

C CD

0

0

1

If we are in state C, and w=1, we should go to state D

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268/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

01

BD

CD

B

C CD

0

0

1

Hands-On: Complete the state table

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278/18/2010

State Table• Develop the state table from the state diagram

A

Reset

z = 0

B D

w = 1w = 0

C

w = 0

z = 0 z = 0

z = 1

w = 0

w = 1

w = 1 E

w = 1

z = 1

w = 0

w = 1

w = 0

PresentState

Inputw

NextState

Outputz

A 01

01

01

01

BD

CD

B

01

C

D

E

CD

BE

BE

0

0

1

0

1

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288/18/2010

FSM Design Steps1. Obtain the specifications of the desired circuit2. Derive the states of the machine and develop a state

diagram1. Should show all possible states2. Provide the conditions for which the circuit moves from one state to

the next

3. Develop the state table from the state diagram4. Decide on the number of state variables needed to

represent all states1. Minimize the number of states if possible

5. Choose the type of flip-flops that will be used in the implementation

1. Derive the next-state logic expressions to develop the Input Logic Circuit

2. Derive the logic expressions for the Output Logic Circuit

6. Implement the design

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298/18/2010

FPGA or CPLD vs. Discreet Components• The next step in the design process should

be to decide on the number of state variables

• But, if you are designing for FPGAs or CPLDs, the next step is writing the VHDL code– In other words: VHDL design allows us to skip

steps 4 & 5 and go directly to implementation

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308/18/2010

FPGA or CPLD vs. Discreet Components• The next step in the design process should

be to decide on the number of state variables

• But, if you are designing for FPGAs or CPLDs, the next step is writing the VHDL code– In other words: VHDL design allows us to skip

steps 4 & 5 and go directly to implementation– For this class, we’ll do both, but start with VHDL

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318/18/2010

VHDL CodeLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY sequence ISPORT ( Clock, Resetn, w: IN STD_LOGIC ;

z: OUT STD_LOGIC ) ;END sequence ;

ARCHITECTURE Behavior OF sequence ISTYPE State_type IS (A, B, C, D, E) ;SIGNAL y : State_type ;

BEGINPROCESS ( Resetn, Clock )

BEGINIF Resetn = '0' THEN y <= A ;ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y ISWHEN A =>

IF w = '0' THEN y <= B ;ELSE y <= D ; END IF ;

WHEN B =>IF w = '0' THEN y <= C ;ELSE y <= D ; END IF ;

WHEN C =>IF w = '0' THEN y <= C ;ELSE y <= D ; END IF ;

WHEN D =>IF w = '0' THEN y <= B ;ELSE y <= E ; END IF ;

WHEN E =>IF w = '0' THEN y <= B ;ELSE y <= E ; END IF ;

END CASE ;END IF ;

END PROCESS ;z <= '1' WHEN (y = C OR y = E) ELSE '0' ;

END Behavior ;

The VHDL code for the design

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328/18/2010

VHDL CodeLIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY sequence ISPORT ( Clock, Resetn, w: IN STD_LOGIC ;

z: OUT STD_LOGIC ) ;END sequence ;

ARCHITECTURE Behavior OF sequence ISTYPE State_type IS (A, B, C, D, E) ;SIGNAL y : State_type ;

BEGINPROCESS ( Resetn, Clock )

BEGINIF Resetn = '0' THEN y <= A ;ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y ISWHEN A =>

IF w = '0' THEN y <= B ;ELSE y <= D ; END IF ;

WHEN B =>IF w = '0' THEN y <= C ;ELSE y <= D ; END IF ;

WHEN C =>IF w = '0' THEN y <= C ;ELSE y <= D ; END IF ;

WHEN D =>IF w = '0' THEN y <= B ;ELSE y <= E ; END IF ;

WHEN E =>IF w = '0' THEN y <= B ;ELSE y <= E ; END IF ;

END CASE ;END IF ;

END PROCESS ;z <= '1' WHEN (y = C OR y = E) ELSE '0' ;

END Behavior ;

Compare the VHDL code to the state table

PresentState

Inputw

NextState

Outputz

A 01

01

01

01

BD

CD

B

01

C

D

E

CD

BE

BE

0

0

1

0

1

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338/18/2010

Synthesized Circuit

Xilinx synthesized the circuit below

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348/18/2010

SimulationBelow is the test bench created to simulate the FSM Design

The waveform for z is shown as “expected results”

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358/18/2010

SimulationBelow is the test bench created to simulate the FSM Design

Below are the simulated results

You can see that the simulated results match the expected results

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368/18/2010

FSM Design Steps1. Obtain the specifications of the desired circuit2. Derive the states of the machine and develop a state

diagram1. Should show all possible states2. Provide the conditions for which the circuit moves from one state to

the next

3. Develop the state table from the state diagram4. Decide on the number of state variables needed to

represent all states1. Minimize the number of states if possible

5. Choose the type of flip-flops that will be used in the implementation

1. Derive the next-state logic expressions to develop the Input Logic Circuit

2. Derive the logic expressions for the Output Logic Circuit

6. Implement the design

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378/18/2010

Discreet Component Design• You can design using discreet components:

– Go back to step 4:• Decide the number of state variables and assign states• Minimize the number of states if necessary

– To do this we must go back to the state table

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388/18/2010

State TableDecide the number of state variables and assign states

PresentState

Inputw

NextState

Outputz

A 01

01

01

01

BD

CD

B

01

C

D

E

CD

BE

BE

0

0

1

0

1

A minimum of 3 bits will be needed unless we decide to use one-hot encoding.

One way to choose state variables is to try to have only one bit change when changing from one state to the next. Let’s try this approach……

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398/18/2010

State TableDecide the number of state variables and assign states

PresentState

Inputw

NextState

Outputz

01

01

01

01

100101

110101

01

000

100

110

101

111

110101

100111

100111

0

0

1

0

1

It is not possible to have only one bit change from state to state, but I did choose to have the LSb always the same as w, and then only one bit change in going from state to state.

Note: The only time the FSM goes to state A is when the reset signal is asserted.

A

B

C

D

E

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408/18/2010

FSM Design Steps1. Obtain the specifications of the desired circuit2. Derive the states of the machine and develop a state

diagram1. Should show all possible states2. Provide the conditions for which the circuit moves from one state to

the next

3. Develop the state table from the state diagram4. Decide on the number of state variables needed to

represent all states1. Minimize the number of states if possible

5. Choose the type of flip-flops that will be used in the implementation

1. Derive the next-state logic expressions to develop the Input Logic Circuit

2. Derive the logic expressions for the Output Logic Circuit

6. Implement the design

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418/18/2010

Choose Flip-Flops• Choose the type of flip-flops to be used

Presentd2d1d0

Inputw

Nextd2d1d0

D2

01

01

01

01

100101

110101

01

000

100

110

101

111

110101

100111

100111

1

1

1

1

1

Let’s start with D

A

B

C

D

E

Outputz

0

0

1

0

1

D1 D0

w

w

w

w w

w

w

w

w0

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428/18/2010

Choose Flip-Flops• Choose the type of flip-flops to be used

Presentd2d1d0

Inputw

Nextd2d1d0

D2

01

01

01

01

100101

110101

01

000

100

110

101

111

110101

100111

100111

1

1

1

1

1

The inputs to D2 for the states shown are always 1. The states that are not shown are “-” (Don’t Cares).

So:

The inputs to D0 for the states shown are always w, except for the “-”.

So:

z is always the same as D1 (present state) so:

A

B

C

D

E

Outputz

0

0

1

0

1

D1 D0

w

w

w

w w

w

w

w

w0

D2 1=

D w0=

z D= 1

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438/18/2010

Choose Flip-Flops• Choose the type of flip-flops to be used

Presentd2d1d0

Inputw

Nextd2d1d0

D2

01

01

01

01

100101

110101

01

000

100

110

101

111

110101

100111

100111

1

1

1

1

1

But, the inputs to D1 have 0, w and /w, so we need to put this in a Karnaugh Map. A

B

C

D

E

Outputz

0

0

1

0

1

D1 D0

w

w

w

w w

w

w

w

w0

D2 1=

D w0=

z D= 1

D1=?

D1

0

- -

- ww

w w

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448/18/2010

Choose Flip-Flops• Choose the type of flip-flops to be used

Presentd2d1d0

Inputw

Nextd2d1d0

D2

01

01

01

01

100101

110101

01

000

100

110

101

111

110101

100111

100111

1

1

1

1

1

But, the inputs to D1 have 0, w and /w, so we need to put this in a Karnaugh Map. A

B

C

D

E

Outputz

0

0

1

0

1

D1 D0

w

w

w

w w

w

w

w

w0

D2 1=

D w0=

z D= 1

D wd wd d1 0 0 2= +

D1

0

- -

- ww

w w

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458/18/2010

D Flip-Flop Implementation

The D flip-flop implementation produced the same results as the VHDL code. But, this circuit could be simplified.

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468/18/2010

D Flip-Flop Implementation

The D flip-flop implementation produced the same results as the VHDL code. But, this circuit could be simplified.

D2 will always be high except in the reset state. If that is not important, D2could be eliminated.

The “always high” input to the AND gate can also be eliminated because:A*B*1=A*B

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478/18/2010

D Flip-Flop Implementation

This D flip-flop implementation also produced the same results as the VHDL code and the previous circuit.

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488/18/2010

Summary• In this topic we worked through an entire, if

simple, design problem:– Reviewed the specifications– Derived the state diagram– Built the state table and assign states– Decided the number of state variables needed– Chose the technology– Implemented the design

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