ESA ITT AO/1-3970/02/NL/ECemits.sso.esa.int/emits-doc/ESTEC/AO6131hybridlpresfinal.pdfESA ITT...

Radiometric performance enhancement of

Active Pixel Sensors

ESA ITT AO/1-3970/02/NL/EC

Koen

De Munck, Deniz

Sabuncuoglu

Tezcan, Kiki Minoglou,

Piet De Moor, Jean Roggen, Chris Van Hoof

IMEC

Jan Bogaerts

Fillfactory/Cypress

Iacopo

Ficai

Veltroni, Cinzia

Toccafondi

Galileo Avionica

Piet De Moor imec 2008 2

Outline

Introduction

CMOS APS/readout design

Technological developments

Characterization

Conclusions & outlook


ITT by the European Space Agency in 2002

Aim:

snapshot shutter CMOS APS demonstrator for high-performance spaceborne

imaging (BI CCD replacement)

Application:

Earth observation

Hyperspectral

imaging

Partners:

FillFactory/Cypress: design

IMEC: technology development

Galileo Avionica: radiometric characterization

Introduction: Aim & collaboration


Array size: 1024x1024

Pixel pitch: 22.5 micron

Filling Factor: > 0.95

Spectral range: 0.39

1 micron

Quantum efficiency:

> 80% in 0.39

0.80 micron

> 50% in 0.8

0.9 micron

Dark current < 1500 e-/(pix.s) @ -15C

Read noise < 50 e-

Full well capacity: > 8 105

e-

Non-linearity: < 1% p-p

Cross-talk < 10-4

Snapshot, windowing

Introduction: Requirements

backside illuminated imager

CMOS active pixel sensor


Introduction: Approach: monolithic & hybridMonolithic approach

backside thinned CMOS APS mounted on MCM substrate

using Au stud bumps MCM substrate

backside thinned diode arrayinterconnected pixel-by pixel

to CMOS ROICby In bumps

Hybrid approach

ROIC

CMOS APS (mono) = ROIC (hybrid):

designed by FF/Cypress, manufactured in XFAB 0.35 um technology

Diode array: manufactured in IMEC


Outline

Introduction:

CMOS APS/readout design:

Imager and pixel architecture

Readout modes

Output stage


Characterization



Design: ROIC architecture

synchronous pipelined shutter

22.5 m pixel pitch

stitched design:

512 x 512 pixels stitch blocks

up to 2048 x 2048 pixels

pseudo-differential output

per 256 columns

20 Mpixels/s

per output

SPI interface for upload:

addressing, gain & offset, NDR, non-linear amplifier,

etc.

radiation tolerant design


20

48

x 2

04

8

8 o

utp

uts

Design: Read-out speed

Frame rate is determined by output speed and window size

Multiple window read-out limited by row overhead time

frame time (ms)

Frame rate (/s)

Full frame 36.7 27.3

Horizontal band of 150 lines 2.87 3484

10 windows of 30x300 pixels 2.26 442

1 row read-out 0.0178 56180

Full frame 18.43 54.3

Horizontal band of 150 lines 2.07 348.4

10 windows of 30x300 pixels 2.83 354

1 row read-out 0.0178 5618010

24

x 1

02

4

4 o

utp

uts


Design: Pixel architecture

monolithic hybrid

in-pixel storage capacitance (fF) 350 350

full well charge (x 1000 electrons) (FWC)

> 200 > 950

read noise (electrons) < 38 < 180

dynamic range (FWC/dark noise) (dB)

75 75

maximum SNR (dB) 53 60

single pixel

sample capacitors

pad for hybridization

photodiode

Cph

determines

charge handling capacity (FWC) and conversion gain

C1,2,3 determine read noise and dynamic range


Design: Normal readout mode

synchronous shutter:all pixels integrate in parallel

pipelined:readout while integrate

correlated double sampling

In both cases:

C1 and C3: reset level

C2: signal level

Tint < Tread

Tint > Tread


Design: Optimized readout modes I

Non-destructive readout (NDR):

Using the three in-pixel capacitors

Read multiple times without resetting

Advantages: low noise, high dynamic range


Design: Optimized readout modes II

Line by line variable integration time:

Integration time selectable per line

Application:

Matching of useful/optimal swing to irradiance

i.e. observation of both bright and dark areas

Reference: J. Bogaerts

et al.: 2005 IEEE Workshop on CCD and Advanced Image Sensors, Nagano, Japan, June 2005


Design: Output stage

Non-linear compensation:

Provides inverse response of typical light-to-voltage signal

Programmable settings (knee points offset and slopes)

Gain stage:

16 different gain settings, scaling with 1.1x

Output driver:

20 pF at 20 Mpix/s

No ADCs on chip


Outline

Introduction:

CMOS APS/readout design:


Process flow

Thin wafer handling

Trenches

Backside surface treatment & anti reflection coating

Results

Characterization



Technological developments: Graded epi growth

growth of of

50 micron thick epitaxial Si with graded doping

aim: enhanced charge collection due to built-in electrical field

backside

frontside

built-in electric field 1x1016/cm3

1x1014/cm3

3x1015/cm3

3x1014/cm3

1x1015/cm3

start wafer (highly doped)

higher doping

lower doping

1x1016/cm3

1x1014/cm3

3x1015/cm3

3x1014/cm3

1x1015/cm3

start wafer (highly doped)

higher doping

lower doping


Technological developments: Imager processing

ROIC design: FillFactory/Cypress

Hybrid diode array design: IMEC

Different imager sizes possible through stitching

Different imager sizes on a 200 mm wafer

1x 20482

16x 10242

20x 5122

on reticle

on wafer

512 x 512 1024 x 1024 2048 x 2048


Technological developments: Imager/ROIC processing

Production:

@ XFAB

0.35 m technology

on 200 mm wafers


Technological developments: Hybrid diode array processing

Process in CMOS Pilot line IMEC (0.13 m technology baseline) on 200 mm wafers

n-

well implantation

n+ contacts

p+ substrate contacts

W plugs

Al metallization

bulk Si

graded doping epi

n-well p+ contact


Technological developments: Trenches for reduced cross-talk

Extra processing steps on hybrid diode arrays:

Trench etching using DRIE, doped poly-Si deposition

Aim: reduce electrical cross-talk

Top view

Cross-section of filled trenches

Cross-section of unfilled trenches

width :1.2 m depth: 50 m

Doped poly-Si filled trenches

np Built-in electric fields

22.5 m

>1e19 at/cm3


Technological developments: Imager post-processing: general approach

Challenge: thin wafers are fragile and flexible

Solution:

Use of temporary carriers (Si, glass)

Use of temporary glues

Allows use of standard equipment

50 micron thin 200 mm Si wafercarrier wafer

thin device wafertemporary glue layer


Technological developments: Imager post-processing: process flow 1

Process:

Temporary glue layer deposition

Wafer to wafer bonding

Challenges:

Uniform voidless wafer level bonding

Results otherwise in wafer damage during grinding

device wafer

carrier wafer

glue layer



Ground 300 mm

wafer

False color image:

TTV = 0.8 m

Ground 300 mm

wafer

False color image:

TTV = 0.8 m

Process:

Wafer thinning on carrier to a final thickness of ~35 micron

3 steps: grinding, dry RIE etch, wet etch

Challenges:

Minimized damage at backside, resulting in bad blue response of imager

Obtaining total thickness variation of < 2 micron on wafer level

Measurement of device wafer thickness on carrier



Process at backside of the wafer:

Backside surface shield in order to repel carriers from surface states:

B implantation at low energy

Laser annealing for low temperature activation

Aluminum shield around imager

Challenge:

Backside surface shield must be very thin in order not to block blue light

Through carrier alignment front -

back

backside of imager with Al shield



Challenge:

Process thin wafer at the (buried) front side

Solution= thin wafer flip:

Second glue layer (with different release properties) deposition

Second carrier wafer bonding

Release first carrier


Technological developments: Imager post-processing: process flow 5 (hybrid only)

Processing:

Under bump metallization (UBM) deposition & patterning

In deposition and patterning

Dicing (including carrier wafer)

Challenge:

In bump uniformity & yield

UBM

In b

um

ps

22.5 um


Technological developments: Imager post-processing: process flow 6 for monolithic

Monolithic integration:

Au stud bumping

Au bumps deposited on MCM substrate

Au thermo-compression on Al bonding pads of imager using flip-

chip bonder

Challenge:

Flip-chip of thin die

Solution:

Use carrier die + release

MCM substrate

imager

MCM substrate

imager

carrier

carrier

Au stud bump


Technological developments: MCM wafer process

1 metal layer interconnect between landing pad Au stud bump and bonding pad


Technological developments: Imager post-processing: process flow 6 for hybrid

Hybrid integration:

UBM & In processed on both diode array and ROIC side

Bumping using flip-chip bonder

Carrier die release

ROIC

carrier

diode array

ROIC

carrier

diode array

diode array

RO

IC



Mounting on COB board

Using wire bonding

ARC deposition

ZnS

+ MgF2

Using shadow mask


Technological developments: Results: monolithic imagers

Monolithic imagers:

1024 x 1024

40m

MCM

imager 40m

MCM

imager 40m

MCM

imager


Technological developments: Results: hybrid imagers

50 um

hybrid diode array

ROIC

50 um

hybrid diode array

ROIC

ROIC

hybrid diode array

Hybrid imagers:

512x512

1024x1024


Technological developments: Results: special devices

1024x1024 trenched hybrid imager

Unthinned

2kx2k read-out


Outline

Introduction



Characterization:

Functionality & yield

Response & non-linearity

Dark current & read noise

PRNU & Quantum efficiency

Cross talk

Radiation hardness



Characterization: functionality check

2048x2048 direct imaging of

hexagonal nut

2048 x 2048:

unthinned

read-out

front side illumination

high yield:

2 bad columns, 2 partial rows

> 99.8 %

1048 x 1048:

Hybrid thinned device

Monolithic thinned device

Trenched Hybrid thinned device

512 x 512:

Test devices: hybrid, thinned & unthinned

Hyb

rid 1

024x1

024


0.01

0.1

1

10

100C

umulative pixelcount (%

)

1.00.80.60.40.20.0Intensity (normalized scale)

80x103

60

40

20

0

#pix

els

(arb

. sca

le)

Characterization: Pixel yield analysis of Hybrid

Hybrid thinned 1024x1024 imager

Yield in terms of light sensitivity: 99.93% < Y < 99.99%

99.93%99.99%

Interconnect yield

Pixels with nominal dark

current

Analysis on differential image (Bright

Dark)


Characterization: Pixel yield analysis of Monolithic

Monolithic thinned 1024x1024 imager

Yield in terms of light sensitivity > 99.999 %

When removing 10 faulty lines (~ 1 %)

10-1100101102103104105

#pix

els

(arb

. sca

le)

0.300.200.100.00Intensity (normalized scale)

0.0001

0.001

0.01

0.1

1

10

100 Cumulative pixelcount(%

)


Characterization: Response conversion factor

Conversion factor CVF:

Dependent on gain and NLA settings

Mono: 6 -

12 uV/e-

Hybrid: 1.5

3 uV/e-

hybrid

Full well capacity FWC:

Mono: 1.8 105

e-

Hybrid: 7.57 105

e-

0.00

10.00

20.00

30.00

40.00

50.00

60.00

0 2 4 6 8 10 12 14 16

Gain settingC

onve

rsio

n ga

in [u

V/e]

1.05

1.07

1.09

1.11

1.13

1.15

1.17

Gai

n (x

+) /

Gai

n (x

)

mono


Characterization: Non-linearity of response

Non-linearity of monolithic device with non-linear amplifier OFF:

1% peak-peak in the range 20%

64% of full well capacity

mono

% d

evia

tion

from

line

ar fi

t


Characterization: Non-linearity of response

Non-linearity of monolithic device with non-linear amplifier ON, using optimized settings:

0.5% peak-peak in the range 8%

87% of full well capacity

Conclusion: excellent linearity using correction

mono

% FW

% d

evia

tion

from

line

ar fi

t


Characterization: Dark current

Dark current at -15C

Mono: 330 e-/pix.s, corresponding to 0.01 nA/cm2

Hybrid: 736 e-/pix.s, corresponding to 0.023 nA/cm2

Temperature dependence: *2 every 8-9C

Dark current non-uniformity: < 20

50 %

Temperature MonoDark current (e-/pix.s)

HybridDark current (e-/pix.s)

-20 218 875

-15 330 736

-10 484 1696

0 1404 3838

10 2552 9838

20 6766 19690

30 13513 45582

mono


Characterization: Read noise

Mono:

@ 25C: 88 e-

(715 uV)

@ -15C: 80 e-

(642 uV)

Hybrid @25C:

142

264 e-

(highest gain, unity gain)

Corresponding to 794, 249 uV

Remark on noise numbers:

Including system noise !

= upper limit

hybrid

hybrid


Characterization: Pixel response non-uniformity (PRNU)

Mono:

Zone A: 15.9 %

Zone B: 5.01 %

Zone C: 8.24 %

Zone A: 9.13 %

High frequency ~ 4.25 %

Hybrid:

Zone A: 11.8 %

Zone B: 8.49 %

Zone C: 8.23 %

Zone A: 8.54 %

High frequency ~ 7.4 %

High PRNU most probably related to residues of temporary glue on device backside

will be addressed in near future

hybrid

mono flat field


Characterization: Quantum efficiency: impact of backside passivation

QE measured without anti-refection coating

After backside passivation: increased blue response !

Effective non-sensitive thickness layer ~ 10

15 nm

0

10

20

30

40

50

60

70

80

300 400 500 600 700 800 900 1000 1100

Wavelength [nm]

Qua

ntum

effi

cien

cy [%

]

measured 22 m thick

15 nm

20 nm

100 nm

10 nm

50 nm

0 nm

dead layer thickness

before laser annealing

5 nm

2 nm


Characterization: Anti Reflective Coating (ARC)

Optimized broad band ARC

Reflectivity


Characterization: Quantum efficiency: backside passivation + ARC

Excellent broad band QE > 80% from 400 nm

850 nm

Similar results for both mono and hybrid devices

0

10

20

30

40

50

60

70

80

90

100

250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100

Wavelength [nm]

Qua

ntum

effi

cien

cy [%

]

measurement

simulation: plain Si0 nm

10 nm15 nm

simulation: ARC limited

0 nm15 nm simulation: ARC + implant

0 nm10 nm

15 nm

dead layer thickness

QE > 80 %


Characterization: Quantum efficiency: degradation of ARC

Reduction of QE as a function of time

= degradation of ARC probably due to humidity absorption

will be addressed in near future

0

10

20

30

40

50

60

70

80

90

100

250 300 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 1050 1100

Wavelength [nm]

Qua

ntum

effi

cien

cy [%

]

back_1k_dev4 with ARC (may 9)

back_1k_dev4 with ARC (june 19)

back_1k_dev4 no ARC (april 4)


Characterization: Quantum efficiency: trenched hybrid imager

QE of trenched hybrid imager is low after backside passivation

This is probably due to:

reduced fill factor

recombination at trench sidewalls

No trenches

Trenched Trenched compensated for fill factor loss No ARC


Characterization: Cross - talk

Knife edge measurement + MTF calculation

Good MTF for trenched hybrid imager: 0.5 at Nyquist

0

10

20

30

40

50

60

70

80

90

100

0 10 20 30 40 50 60 70 80 90 100

Knife edge position [um]

Rel

ativ

e pi

xel r

espo

nse

[%]

1k trenched - 550 nm1k trenched - 650 nm1k trenched - 450 nm512 no trench - 550 nm512 no trench - 650 nm512 no trench - 450 nmideal curvepixel border

effect of trenches

0.00 0.02 0.04 0.06 0.08 0.100.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

MTF

spatial Frequency lp/um

ampl

itude


0.000 0 .0 05 0.01 0 0 .015 0.0 200.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency (lp/um)

MT

FCharacterization: Cross - talk

Point source illumination + MTF calculation

Bad MTF for monolithic device:

Close to 0 at Nyquist

mono

60x Microscope objective

x-y-z translation stage

Neutral density filter assembly

Low power beam

HeNe lasercollimator

60x Microscope objective

x-y-z translation stage

Neutral density filter assembly

Low power beam

HeNe laserHeNe lasercollimatorcollimator

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1


Characterization: Cross - talk

Monolithic device:

Signal leakage to neigbouring

pixels = 88 %

Caused by diffusion of carriers

Trenched hybrid device:

Signal leakage to neigbouring

pixels = 0 %

Diffusion of carriers to neigbouring

pixels is

blocked

12

3

S1

S2

S3

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1

2

3

4

5

S1S2

S3S4

S5

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1


Characterization: Radiation tests

Proton irradiation

5 x 1010

60 MeV

protons/cm2

Additional 60Cogamma irradiation

50 krad(Si)

Dark current measured before and after irradiation:

512x512 hybrid device:

Increase of dark current by factor 2.5 after proton irradiations

Additional increase of dark current by a factor of 17 after gamma radiation

512x512 mono device, unthinned, front side illumination

No increase of dark current after proton irradiation, # dark current spikes increases

Increase of dark current by a factor of 4 after gamma radiation

0.001

0.01

0.1

1

10

100

0 200 400 600 800 1000 1200 1400 1600

Dark current [mV/s]

Cum

ulat

ive

freq

uenc

y [%

]

device 2 pre

device 2 post 5x10^10protons/cm^2device 2 post 50 krad(Si)

device 4 pre

device 4 post 5x10^10protons/cm^2device 4 post 50 krad(Si)

device 3 pre


Outline

Introduction



Characterization


Conclusions

Outlook


Conclusions

Thinned backside illuminated imagers realized:

Hybridized and monolithic

CMOS APS: synchronous pipelined shutter with true CDS

3D process technology for thin wafer handling and processing:

Use of temporary carriers and glues

200 mm thin wafer processing on carrier with standard equipment

Performance enhancing concepts implemented:

Graded EPI lower cross-talk and improved QE

Poly-Si filled pixel separating trenches zero cross-talk (but QE )

Results:

Excellent broadband QE (but AR ageing )

Zero cross-talk for trenched hybrid device


Outlook

Further investigations planned

Low cross talk while maintaining high QE

Stabilize ARC

Improve PRNU

Process optimizations (i.e. monolithic imager yield)

CCN on this contract under discussion

Performance enhancement using 3D integration technology: through Si vias

detection layer

analog ROIC

digital signal processing

memory

output drivers


Radiometric performance enhancement ofActive Pixel SensorsOutlineIntroduction:Aim & collaborationIntroduction:RequirementsIntroduction:Approach: monolithic & hybridOutlineDesign:ROIC architectureDesign:Read-out speedDesign:Pixel architectureDesign:Normal readout modeDesign:Optimized readout modes IDesign:Optimized readout modes IIDesign:Output stageOutlineTechnological developments:Graded epi growthTechnological developments:Imager processingTechnological developments:Imager/ROIC processingTechnological developments:Hybrid diode array processingTechnological developments:Trenches for reduced cross-talkTechnological developments:Imager post-processing: general approachTechnological developments:Imager post-processing: process flow 1Technological developments:Imager post-processing: process flow 2Technological developments:Imager post-processing: process flow 3Technological developments:Imager post-processing: process flow 4Technological developments:Imager post-processing: process flow 5 (hybrid only)Technological developments:Imager post-processing: process flow 6 for monolithicTechnological developments:MCM wafer processTechnological developments:Imager post-processing: process flow 6 for hybridTechnological developments:Imager post-processing: process flow 7Technological developments:Results: monolithic imagersTechnological developments:Results: hybrid imagersTechnological developments:Results: special devicesOutlineCharacterization:functionality checkCharacterization:Pixel yield analysis of HybridCharacterization:Pixel yield analysis of MonolithicCharacterization:Response conversion factorCharacterization:Non-linearity of responseCharacterization:Non-linearity of responseCharacterization:Dark currentCharacterization:Read noiseCharacterization:Pixel response non-uniformity (PRNU) Characterization:Quantum efficiency: impact of backside passivationCharacterization:Anti Reflective Coating (ARC)Characterization:Quantum efficiency: backside passivation + ARCCharacterization:Quantum efficiency: degradation of ARCCharacterization:Quantum efficiency: trenched hybrid imagerCharacterization:Cross - talkCharacterization:Cross - talkCharacterization:Cross - talkCharacterization:Radiation testsOutlineConclusionsOutlookSlide Number 55

ESA ITT AO/1-3970/02/NL/ECemits.sso.esa.int/emits-doc/ESTEC/AO6131hybridlpresfinal.pdfESA ITT...

Documents

Transcript of ESA ITT AO/1-3970/02/NL/ECemits.sso.esa.int/emits-doc/ESTEC/AO6131hybridlpresfinal.pdfESA ITT...