EPC2055 – Enhancement Mode Power Transistor · 2020. 12. 16. · Figure Typica O C aac te a DS...
Transcript of EPC2055 – Enhancement Mode Power Transistor · 2020. 12. 16. · Figure Typica O C aac te a DS...
eGaN® FET DATASHEET EPC2055
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 1
EFFICIENT POWER CONVERSION
HAL
EPC2055 – Enhancement Mode Power Transistor
VDS , 40 VRDS(on) , 3.6 mΩID , 29 A
Maximum Ratings
PARAMETER VALUE UNIT
VDS
Drain-to-Source Voltage (Continuous) 40V
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150 °C) 48
ID
Continuous (TA = 25°C) 29A
Pulsed (25°C, TPULSE = 300 µs) 161
VGSGate-to-Source Voltage 6
VGate-to-Source Voltage -4
TJ Operating Temperature -40 to 150°C
TSTG Storage Temperature -40 to 150
Thermal Characteristics
PARAMETER TYP UNIT
RθJC Thermal Resistance, Junction-to-Case 1
°C/W RθJB Thermal Resistance, Junction-to-Board 2.5
RθJA Thermal Resistance, Junction-to-Ambient (Note 1) 64Note 1: RθJA is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.See https://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
# Defined by design. Not subject to production test.
Static Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITBVDSS Drain-to-Source Voltage VGS = 0 V, ID = 0.5 mA 40 V
IDSS Drain-Source Leakage VGS = 0 V, VDS = 32 V 0.01 0.4
mAIGSS
Gate-to-Source Forward Leakage VGS = 5 V 0.01 0.8
Gate-to-Source Forward Leakage# VGS = 5 V, TJ = 125°C 0.1 5
Gate-to-Source Reverse Leakage VGS = -4 V 0.01 0.4
VGS(TH) Gate Threshold Voltage VDS = VGS, ID = 7 mA 0.7 1.1 2.5 V
RDS(on) Drain-Source On Resistance VGS = 5 V, ID = 15 A 3 3.6 mΩ
VSD Source-Drain Forward Voltage IS = 0.5 A, VGS = 0 V 1.9 V
Gallium Nitride’s exceptionally high electron mobility and low temperature coefficient allows very low RDS(on), while its lateral device structure and majority carrier diode provide exceptionally low QG and zero QRR. The end result is a device that can handle tasks where very high switching frequency, and low on-time are beneficial as well as those where on-state losses dominate.
EPC2055 eGaN® FETs are supplied only in passivated die form with solder bars. Die Size: 2.5 mm x 1.5 mm
Applications• DC-DC Converters• Isolated DC-DC
Converters• Sync rectification• High frequency (2 MHz) Ultra-thin Point of Load Converters with Input 12 V – 24 V
• Lidar• USB-C Battery Chargers• LED Lighting• 12 V – 24 V Input Motor Drivers
Benefits• Ultra High Efficiency• No Reverse Recovery• Ultra Low QG
• Small Footprint
G
D
S
eGaN® FET DATASHEET EPC2055
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 2
160
140
120
100
80
60
40
20
00 0.5 1.0 1.5 2.0 2.5 3.0
I D –
Drai
n Cu
rrent
(A)
Figure 1: Typical Output Characteristics at 25°C
VDS – Drain-to-Source Voltage (V)
VGS = 5 VVGS = 4 VVGS = 3 VVGS = 2 V
I D –
Drai
n Cu
rrent
(A)
VGS – Gate-to-Source Voltage (V) 1.00.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 2: Transfer Characteristics
25˚C125˚C
VDS = 3 V
25˚C125˚C
VDS = 3 V
160
140
120
100
80
60
40
20
0
12
10
8
6
4
2
02.5 3.02.0 3.5 4.0 4.5 5.0
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ)
VGS – Gate-to-Source Voltage (V)
Figure 3: RDS(on) vs. VGS for Various Drain Currents
ID = 7 AID = 15 AID = 22 AID = 30 A
2.0 2.5 3.0 3.5 4.0 4.5 5.0
Figure 4: RDS(on) vs. VGS for Various Temperatures
R DS(o
n) –
Dra
in-to
-Sou
rce R
esist
ance
(mΩ
)
VGS – Gate-to-Source Voltage (V)
25˚C125˚C
VDS = 3 V
25˚C125˚C
ID = 15 A
12
10
8
6
4
2
0
Dynamic Characteristics (TJ = 25°C unless otherwise stated)
PARAMETER TEST CONDITIONS MIN TYP MAX UNITCISS Input Capacitance#
VDS = 20 V, VGS = 0 V
841 1111
pF
CRSS Reverse Transfer Capacitance 8.8
COSS Output Capacitance# 408 612
COSS(ER) Effective Output Capacitance, Energy Related (Note 2)VDS = 0 to 20 V, VGS = 0 V
574
COSS(TR) Effective Output Capacitance, Time Related (Note 3) 668
RG Gate Resistance 0.4 Ω
QG Total Gate Charge# VDS = 20 V, VGS = 5 V, ID = 15 A 6.6 8.5
nC
QGS Gate-to-Source Charge
VDS = 20 V, ID = 15 A
2.3
QGD Gate-to-Drain Charge 0.7
QG(TH) Gate Charge at Threshold 1.6
QOSS Output Charge# VDS = 20 V, VGS = 0 V 13 20
QRR Source-Drain Recovery Charge 0# Defined by design. Not subject to production test.Note 2: COSS(ER) is a fixed capacitance that gives the same stored energy as COSS while VDS is rising from 0 to 50% BVDSS. Note 3: COSS(TR) is a fixed capacitance that gives the same charging time as COSS while VDS is rising from 0 to 50% BVDSS.
eGaN® FET DATASHEET EPC2055
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 3
Capa
citan
ce (p
F)
0 10 20 30 40
Figure 5a: Capacitance (Linear Scale)
VDS – Drain-to-Source Voltage (V)
1000
800
600
400
200
0
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Capa
citan
ce (p
F)
1000
100
10
10 10 20 30 40
Figure 5b: Capacitance (Log Scale)
VDS – Drain-to-Source Voltage (V)
COSS = CGD + CSD
CISS = CGD + CGS
CRSS = CGD
Figure 6: Output Charge and COSS Stored Energy
Q OSS
– O
utpu
t Cha
rge (
nC)
E OSS
– C O
SS St
ored
Ener
gy (µ
J)25
20
15
10
5
00 5 10 15 20 25 30 35 40
VDS – Drain-to-Source Voltage (V)
0.35
0.28
0.21
0.14
0.07
0.00
Figure 7: Gate Charge
V GS –
Gate
-to-S
ourc
e Vol
tage
(V)
5
4
3
2
1
00 5 6 74321
QG – Gate Charge (nC)
ID = 15 A
VDS = 20 V
0.50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
I SD –
Sour
ce-to
-Dra
in Cu
rrent
(A)
VSD – Source-to-Drain Voltage (V)
Figure 8: Reverse Drain-Source Characteristics160
140
120
100
80
60
40
20
0
25˚C
VGS = 0 V
125˚C
Figure 9: Normalized On-State Resistance vs. Temperature
Norm
alize
d On
-Sta
te R
esist
ance
RDS
(on)
2.0
1.8
1.6
1.4
1.2
1.0
0.80 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 15 AVGS = 5 V
eGaN® FET DATASHEET EPC2055
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 4
Figure 12: Transient Thermal Response Curves
Figure 10: Normalized Threshold Voltage vs. Temperature
Norm
alize
d Th
resh
old
Volta
ge
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6 0 25 50 75 100 125 150
TJ – Junction Temperature (°C)
ID = 7 mA
1000
100
10
1
0.10.1 1 10 100
I D – D
rain
Curre
nt (A
)
VDS - Drain-Source Voltage (V)
Limited by RDS(on)
Pulse Width 1 ms 100 µs
10 µs
Figure 11: Safe Operating Area
tp, Rectangular Pulse Duration, seconds
Z θJB
, Nor
mal
ized T
herm
al Im
peda
nce
0.50.2
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
Junction-to-Board
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJB x RθJB + TB
PDM
t1
t2
10-5 10-4 10-3 10-2 10-1 1 10+1
1
0.1
0.01
0.001
tp, Rectangular Pulse Duration, seconds
Z θJC
, Nor
mal
ized T
herm
al Im
peda
nce 0.5
Junction-to-Case
Notes:Duty Factor: D = t1/t2
Peak TJ = PDM x ZθJC x RθJC + TC
PDM
t1
t2
10-6 10-5 10-4 10-3 10-2 10-1 1
1
0.1
0.01
0.001
0.0001
0.2
0.050.02
Single Pulse
0.01
0.1
Duty Cycle:
TJ = Max Rated, TC = +25°C, Single Pulse
eGaN® FET DATASHEET EPC2055
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 5
DIE MARKINGS
DIE OUTLINESolder Bump View
Pad 1 is Gate;Pads 2 ,4, 6 are Source;Pads 3, 5 are Drain
DIM
Micrometers
MIN Nominal MAX
A 2470 2500 2530B 1470 1500 1530
c 1175
d 1350
e 500
f 250
g 300
h 825
j 787.5
k 225Side View
YYYY2055
ZZZZ
TAPE AND REEL CONFIGURATION4 mm pitch, 8 mm wide tape on 7” reel
7” inch reel Dieorientationdot
Gate solder baris under thiscorner
Die is placed into pocketsolder bump side down(face side down)
Loaded Tape Feed Direction
a
d
e f
g
h
c
b
DIM Dimension (mm)EPC2204 (Note 1) Target MIN MAX
a 8.00 7.90 8.30b 1.75 1.65 1.85c (Note 2) 3.50 3.45 3.55d 4.00 3.90 4.10e 4.00 3.90 4.10f (Note 2) 2.00 1.95 2.05g 1.50 1.50 1.60h 0.50 0.45 0.55
Note 1: MSL 1 (moisture sensitivity level 1) classified according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket, not the pocket hole.
Part Number
Laser Markings
Part #Marking Line 1
Lot_Date CodeMarking Line 2
Lot_Date CodeMarking Line 3
EPC2055 2055 YYYY ZZZZ
2055YYYY ZZZZ Die orientation dot
Gate Pad bump isunder this corner
518 ±
-25
Seating plane
638
120 ±
12
A
d
jk
hg
B
e
c
f
2
3 4 5 6
1
eGaN® FET DATASHEET EPC2055
EPC – POWER CONVERSION TECHNOLOGY LEADER | EPC-CO.COM | ©2020 | | 6
RECOMMENDEDLAND PATTERN (units in µm)
RECOMMENDEDSTENCIL DRAWING (units in µm)
Recommended stencil should be 4 mil (100 µm) thick, must be laser cut, openings per drawing.
The corner has a radius of R60.
Intended for use with SAC305 Type 3 solder, reference 88.5% metals content.
Split stencil design can be provided upon request, but EPC has tested this stencil design and not found any scooping issues.
Additional assembly resources available at https://epc-co.com/epc/DesignSupport/AssemblyBasics.aspx
Efficient Power Conversion Corporation (EPC) reserves the right to make changes without further notice to any products herein to improve reliability, function or design. EPC does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others.
eGaN® is a registered trademark of Efficient Power Conversion Corporation.EPC Patent Listing: epc-co.com/epc/AboutEPC/Patents.aspx
Information subject to change without notice.
Revised December, 2020
Land pattern is solder mask definedSolder mask opening is 180 µmIt is recommended to have on-Cu trace PCB vias
Pad 1 is Gate;Pads 2 ,4, 6 are Source;Pads 3, 5 are Drain
DIM Nominal
A 2500B 1500c1 1155d1 1330e 500f1 230g1 280h1 805j 787.5k 225
DIM Nominal
A 2500B 1500c1 1155d1 1330e 500f1 230g1 280h1 805j 787.5k 225
A
d1
jk
h1g1
B
e
c1
f1
2
3 4 5 6
1
Ad1
h1g1
B
e
c1
f1R60
jk