End-to-end Real-time Guarantees in Wireless Cyber-physical ...

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End-to-end Real-time Guarantees in Wireless Cyber-physical Systems Romain Jacob Pengcheng Huang Lothar Thiele RTSS 16 - IoT and Networking Session December 1, 2016 Marco Zimmerling Jan Beutel

Transcript of End-to-end Real-time Guarantees in Wireless Cyber-physical ...

Page 1: End-to-end Real-time Guarantees in Wireless Cyber-physical ...

End-to-end Real-time Guarantees in Wireless Cyber-physical Systems

Romain JacobPengcheng Huang Lothar Thiele

RTSS 16 - IoT and Networking SessionDecember 1, 2016

Marco ZimmerlingJan Beutel

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Predictability is key!

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A Cyber-physical System goes beyond a real-time wireless network

Real-time guarantees > Deadlines are met

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Wireless network Low-power Multi-hop

Network deadline

Predictability

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A Cyber-physical System goes beyond a real-time wireless network

Real-time guarantees > End-to-end deadlines are met

Buffer management > No buffer overflow

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Wireless network Low-power Multi-hop

Controller

Actuator

Sensor

End-to-end deadline

Network deadline

Predictability

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A Cyber-physical System goes beyond a real-time wireless network

Real-time guarantees > End-to-end deadlines are met

Buffer management > No buffer overflow

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Predictability

Local interference

Application

Communication

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Predicatability

Design goals

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network

Blink

Device

?

Bolt

System

?

?

?

?

DRP

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First A predictable and adaptivepiece wireless network

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Wireless network Low-power Multi-hop

Controller

Actuator

Sensor

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First A predictable and adaptivepiece wireless network

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Wireless network Low-power Multi-hop

Controller

Actuator

Sensor

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State-of-the-art wireless protocolsare predictable or adaptive

Splash, RAP EfficientAdaptive> not Predictable

WirelessHART PredictableEfficient> not Adaptive

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Blink A real-time, reliable and[1] adaptive wireless protocol

Adaptive Based on Glossy> Flooding primitive

Reliable Average 99.97% reception rate> Multiple testbeds> Tested up to 94 nodes

Real-time Online scheduling> EDF-based Lazy Scheduling

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[1] Zimmerling M. et al., Adaptive Real-time Communication for Wireless Cyber-physical SystemsTo appear in ACM Transactions on Cyber-Physical Systems, 2016

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Blink A real-time, reliable and[1] adaptive wireless protocol

Abstraction Low-power Wireless Bus (LWB)> MAC protocol

Communication TDMA-basedin rounds > Sleep between rounds

> Wireless yields sync!

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𝑇𝑛𝑒𝑑

𝐢𝑛𝑒𝑑

𝑑

𝑑

𝑑

Node 1

Node 2

Node N

…

M slots

……

…

[1] Zimmerling M. et al., Adaptive Real-time Communication for Wireless Cyber-physical SystemsTo appear in ACM Transactions on Cyber-Physical Systems, 2016

Variable!

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Sched(n+1)

Blink A real-time, reliable and[1] adaptive wireless protocol

Abstraction Low-power Wireless Bus (LWB)> MAC protocol

Communication TDMA-basedin rounds > Sleep between rounds

> Wireless yields sync!

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𝑇𝑛𝑒𝑑

𝐢𝑛𝑒𝑑

𝑑

𝑑

𝑑

Node 1

Node 2

Node N

…

M slots

……

…

[1] Zimmerling M. et al., Adaptive Real-time Communication for Wireless Cyber-physical SystemsTo appear in ACM Transactions on Cyber-Physical Systems, 2016

Variable!

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Design goals

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

na

na

?

?

?

?

?

Blink Bolt DRP

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Second A dual-processor architecturepiece to mitigate local interference

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Wireless network Low-power Multi-hop

Controller

Actuator

Sensor

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Second A dual-processor architecturepiece to mitigate local interference

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Wireless network Low-power Multi-hop

Controller

Actuator

Sensor

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Bolt A dual-processor architecture [2] to mitigate local interference

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BOLTBOLT

APIBOLT

API

…

…Receive Buffer

flush

read

write

…

Wireless Comm. Tasks

ApplicationTasks

Communication Processor (CP)

…

Receive Buffer

flush

read

write

Application Processor (AP)

Incoming

Outgoing

Real-time Formally verifiedbehavior Implemented, tested, deployed

Efficient πœ‡π‘Š > sleepπ‘šπ‘Š > active

Composable Hardware/Softwarefree composition

[2] Sutton F. et al., Bolt: A Stateful Processor Interconnect, SenSys’15, 2015

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Design goals

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

?

?

?

?

?

Blink Bolt DRP

na

na

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Design goals β†’ How can we fill the blanks?

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

?

?

?

?

?

Blink Bolt DRP

? na

na

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Third Distributed Real-time Protocol (DRP)piece

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

?

?

?

?

?

?

Blink Bolt DRP

na

na

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DRP is based on three main concepts

Communication is constrained within registered flows only

Global requirements are splitedacross distributed components

Interaction between componentsis based on contracts

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DRP is based on three main concepts

Communication is constrained within registered flows only

Global requirements are splitedacross distributed components

Interaction between componentsis based on contracts

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Communication is constrained within registered flows only

Flow 𝑖 𝐹𝑖 = ( 𝑛𝑖𝑠, 𝑛𝑖

𝑑 , 𝑇𝑖 , 𝐽𝑖 , 𝐃𝑖 )

Release model Sporatic with jitter

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SourceDestinationMin. release intervalJitterEnd-to-end deadline

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DRP is based on three main concepts

Communication is constrained within registered flows only

Global requirements are splitedacross distributed components

Interaction between componentsis based on contracts

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Global requirements are splitedacross distributed components

DRP : 𝐷𝑖𝑠 + 𝐷𝑖

𝑛𝑒𝑑 + 𝐷𝑖𝑑 = 𝐃

end-to-end deadline : 𝐃

𝐷𝑖𝑠 𝐷𝑖

𝑛𝑒𝑑 𝐷𝑖𝑑

Wireless protocolSource Destination

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Real-timeguarantee

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DRP is based on three main concepts

Communication is constrained within registered flows only

Global requirements are splitedacross distributed components

Interaction between componentsis based on contracts

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Interaction between componentsis based on contracts

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> Node ↔ Network

> Max resource demandMin service delivered

>

Contract

CONSTRAINTS

ON LOCAL

SCHEDULES

BB

AA

Predictability Performance

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Example

Scheduling of Communication Processors (CP)

Real-time Participate in rounds guarantees > 𝑇𝑛𝑒𝑑 Blink schedule

Flush before roundsWrite after rounds> 𝑇𝑛𝑒𝑑 Blink schedule

Buffer Flush Bolt regularlymanagement > 𝑇𝑓

𝑠 Comm. Processorschedule

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Example

Scheduling of Communication Processors (CP)

How can we guarantee that all tasks are schedulable?

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𝐢𝑓 𝐢𝑀

Participate in rounds

Flush before rounds

Write after rounds

Flush Bolt regularly

𝑇𝑓𝑠

𝑑

𝐢𝑛𝑒𝑑

𝑇𝑛𝑒𝑑

𝑑

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Example

Scheduling of Communication Processors (CP)

How can we guarantee that all tasks are schedulable?

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𝐢𝑓 𝐢𝑀

Participate in rounds

Flush before rounds

Write after rounds

Flush Bolt regularly

𝑇𝑓𝑠

𝑑

Variable!

Variable!

𝐢𝑛𝑒𝑑

𝑇𝑛𝑒𝑑

𝑑

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𝐢𝑛𝑒𝑑

𝑇𝑛𝑒𝑑

Example

Scheduling of Communication Processors (CP)

How to guarantee that all tasks are schedulable?

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𝐢𝑓 𝐢𝑀

𝑑

Participate in rounds

Flush before rounds

Write after rounds

Flush Bolt regularly

Variable!

Variable! Conflict!𝑇𝑓𝑠

𝑑

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Example

Scheduling of Communication Processors (CP)

How to guarantee that all tasks are schedulable?

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𝐢𝑓 𝐢𝑀𝐢𝑛𝑒𝑑

𝑇𝑛𝑒𝑑

Participate in rounds

Flush before rounds

Write after rounds

Flush Bolt regularly

𝐢𝐢𝑃 β‰œ 𝐢𝑓 + 𝐢𝑛𝑒𝑑 + 𝐢𝑀> 𝑇𝑛𝑒𝑑 β‰œ π‘˜ β‹… 𝐢𝐢𝑃

Solution TDMA approach

Variable!

Variable!

𝑑𝑇𝑓𝑠

𝑑

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Example

Scheduling of Communication Processors (CP)

How to guarantee that all tasks are schedulable?

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𝐢𝑓 𝐢𝑀

Participate in rounds

Flush before rounds

Write after rounds

Flush Bolt regularly

𝑑𝑇𝑓𝑠

𝐢𝐢𝑃 β‰œ 𝐢𝑓 + 𝐢𝑛𝑒𝑑 + 𝐢𝑀> 𝑇𝑓

𝑠 β‰œ 𝐢𝐢𝑃> 𝑇𝑛𝑒𝑑 β‰œ π‘˜ β‹… 𝐢𝐢𝑃

Fixed to min

Solution TDMA approach

Variable!

𝐢𝑛𝑒𝑑

𝑇𝑛𝑒𝑑

𝑑

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Example

Scheduling of Communication Processors (CP)

How to guarantee that all tasks are schedulable?

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𝐢𝑓 𝐢𝑀𝐢𝑛𝑒𝑑

𝑇𝑛𝑒𝑑

Participate in rounds

Flush before rounds

Write after rounds

Flush Bolt regularly

𝑑𝑇𝑓𝑠

𝐢𝐢𝑃 β‰œ 𝐢𝑓 + 𝐢𝑛𝑒𝑑 + 𝐢𝑀> 𝑇𝑓

𝑠 β‰œ 𝐢𝐢𝑃> 𝑇𝑛𝑒𝑑 β‰œ π‘˜ β‹… 𝐢𝐢𝑃

Variable but constrained

Solution TDMA approach

𝑑

Fixed to min

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+ Predictability of Network + Predictability of Devices + DRP contracts

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End-to-end latencyBuffer size

Flush interval 𝑇𝑓𝑠

Flush interval 𝑇𝑓𝑑

Network deadline 𝐷𝑖𝑛𝑒𝑑

End-to-end deadlineMemory space≀

= System predictability Worst-Case Analysis

= 𝑓( Local parameters )

Can we set localparameters such that…

If YES System predictabilityby design

Ultimately

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Design goals

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

?

?

?

?

?

?

Blink Bolt DRP

na

na

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Predicatability

Design goals

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

?

?

?

?

?

?

Blink Bolt DRP

na

na

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From there, adaptability is one (close) step away

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End-to-end latencyBuffer size

End-to-end deadlineMemory space≀

Can we set localparameters such that…

ADMISSION

TESTS

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From there, adaptability is one (close) step away

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ADMISSION

TESTS

Depends only on local parameters!

Example

Communication Processor

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Adaptability is achieved via a distributed registration scheme

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LOGICAL LAYER

PHYSICAL LAYER

request : 𝑇𝑖 , 𝐽𝑖𝐷𝑖 , 𝐃i YES Y

APs CPsBOLT APdBOLTCPdBLINKPacket

flow

Bolt buffer andlocal memory OK?

Abort

Register flow

Abort

Register flow

Abort

Register flow and update schedule

YES

Abort

Register flow andupdate schedule

Abort

Register flow and update schedule

Compute 𝐷𝑖

𝑇𝑖 , 𝐽𝑖𝐃i

Networkschedule OK?

Local memory OK?

update : 𝑇𝑓𝑑

YES

nack

ack

end-to-end latency ≀ 𝐃i

YES

REGISTRATION

SCHEMEADMISSION

TESTS

NO NO NO NO

𝑓(𝑇𝑓𝑠, 𝐷𝑖) 𝑔(𝑇𝑓

𝑑)

Bolt buffer

and 𝑇𝑓𝑑 OK?

nack

ack

nack

ack

nack

ack

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Predicatability

Design goals

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

?

?

Blink Bolt DRP

na

na

Adaptability

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The detailed system analysis allows for performance optimization

Minimal admissible end-to-end deadline

πƒπ‘šπ‘–π‘› = π›Ώπ‘“π‘π‘œπ‘›π‘ π‘‘ + π‘‡π‘šπ‘–π‘› + π‘‡π‘šπ‘–π‘› + 𝛿𝑔

π‘π‘œπ‘›π‘ π‘‘ + 𝑇𝑓,π‘šπ‘–π‘›π‘‘

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PacketflowAPs CPsBOLT APdBOLTCPdBLINK

end-to-end latency β‰₯ πƒπ‘šπ‘–π‘›

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The detailed system analysis allows for performance optimization

Minimal admissible end-to-end deadline

πƒπ‘šπ‘–π‘› = π›Ώπ‘“π‘π‘œπ‘›π‘ π‘‘ + π‘‡π‘šπ‘–π‘› + π‘‡π‘šπ‘–π‘› + 𝛿𝑔

π‘π‘œπ‘›π‘ π‘‘ + 𝑇𝑓,π‘šπ‘–π‘›π‘‘

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PacketflowAPs CPsBOLT APdBOLTCPdBLINK

end-to-end latency β‰₯ πƒπ‘šπ‘–π‘›Bolt delays

Source delay> Message release by the source> Available for communication

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The detailed system analysis allows for performance optimization

Minimal admissible end-to-end deadline

πƒπ‘šπ‘–π‘› = π›Ώπ‘“π‘π‘œπ‘›π‘ π‘‘ + π‘‡π‘šπ‘–π‘› + π‘‡π‘šπ‘–π‘› + 𝛿𝑔

π‘π‘œπ‘›π‘ π‘‘ + 𝑇𝑓,π‘šπ‘–π‘›π‘‘

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PacketflowAPs CPsBOLT APdBOLTCPdBLINK

end-to-end latency β‰₯ πƒπ‘šπ‘–π‘›

Network delay: Waiting time > Message available> Message processed by the network

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The detailed system analysis allows for performance optimization

Minimal admissible end-to-end deadline

πƒπ‘šπ‘–π‘› = π›Ώπ‘“π‘π‘œπ‘›π‘ π‘‘ + π‘‡π‘šπ‘–π‘› + π‘‡π‘šπ‘–π‘› + 𝛿𝑔

π‘π‘œπ‘›π‘ π‘‘ + 𝑇𝑓,π‘šπ‘–π‘›π‘‘

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PacketflowAPs CPsBOLT APdBOLTCPdBLINK

end-to-end latency β‰₯ πƒπ‘šπ‘–π‘›

Network delay: Transmission > Message processed by the network> Message transmitted to the destination node

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The detailed system analysis allows for performance optimization

Minimal admissible end-to-end deadline

πƒπ‘šπ‘–π‘› = π›Ώπ‘“π‘π‘œπ‘›π‘ π‘‘ + π‘‡π‘šπ‘–π‘› + π‘‡π‘šπ‘–π‘› + 𝛿𝑔

π‘π‘œπ‘›π‘ π‘‘ + 𝑇𝑓,π‘šπ‘–π‘›π‘‘

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PacketflowAPs CPsBOLT APdBOLTCPdBLINK

end-to-end latency β‰₯ πƒπ‘šπ‘–π‘›

Destination delay: Bolt > Message transmitted to the destination node> Message available in the Bolt queue

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The detailed system analysis allows for performance optimization

Minimal admissible end-to-end deadline

πƒπ‘šπ‘–π‘› = π›Ώπ‘“π‘π‘œπ‘›π‘ π‘‘ + π‘‡π‘šπ‘–π‘› + π‘‡π‘šπ‘–π‘› + 𝛿𝑔

π‘π‘œπ‘›π‘ π‘‘ + 𝑇𝑓,π‘šπ‘–π‘›π‘‘

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PacketflowAPs CPsBOLT APdBOLTCPdBLINK

end-to-end latency β‰₯ πƒπ‘šπ‘–π‘›

Destination delay: Application > Message available in the Bolt queue> Message retrieved by the destination application

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The detailed system analysis allows for performance optimization

Minimal admissible end-to-end deadline

πƒπ‘šπ‘–π‘› = π›Ώπ‘“π‘π‘œπ‘›π‘ π‘‘ + π‘‡π‘šπ‘–π‘› + π‘‡π‘šπ‘–π‘› + 𝛿𝑔

π‘π‘œπ‘›π‘ π‘‘ + 𝑇𝑓,π‘šπ‘–π‘›π‘‘

Given Packet size 32 Bytes

𝐢𝑛𝑒𝑑 1 𝑠

𝑇𝑓,π‘šπ‘–π‘›π‘‘ 0.1 𝑠

> πƒπ‘šπ‘–π‘› 3.46 𝑠Max data rate 29.7 𝐡𝑝𝑠 per flow

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Predicatability

Design goals

Real-time guarantees

Buffer management

Adaptability

Efficiency

Composability

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Network Device System

?

Blink Bolt DRP

na

na

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Using flooding primitives

enables the design of both

adaptive AND predictable

Wireless Cyber-Physical Systems

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End-to-end Real-time Guarantees in Wireless Cyber-physical Systems

Romain JacobPengcheng Huang Lothar Thiele

RTSS 16 - IoT and Networking SessionDecember 1, 2016

Marco ZimmerlingJan Beutel

Page 51: End-to-end Real-time Guarantees in Wireless Cyber-physical ...

Simulation correlates closely with the analysis

Typical simulation trace result

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