End-to-end Real-time Guarantees in Wireless Cyber-physical ...
Transcript of End-to-end Real-time Guarantees in Wireless Cyber-physical ...
End-to-end Real-time Guarantees in Wireless Cyber-physical Systems
Romain JacobPengcheng Huang Lothar Thiele
RTSS 16 - IoT and Networking SessionDecember 1, 2016
Marco ZimmerlingJan Beutel
Predictability is key!
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A Cyber-physical System goes beyond a real-time wireless network
Real-time guarantees > Deadlines are met
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Wireless network Low-power Multi-hop
Network deadline
Predictability
A Cyber-physical System goes beyond a real-time wireless network
Real-time guarantees > End-to-end deadlines are met
Buffer management > No buffer overflow
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Wireless network Low-power Multi-hop
Controller
Actuator
Sensor
End-to-end deadline
Network deadline
Predictability
A Cyber-physical System goes beyond a real-time wireless network
Real-time guarantees > End-to-end deadlines are met
Buffer management > No buffer overflow
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Predictability
Local interference
Application
Communication
Predicatability
Design goals
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network
Blink
Device
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Bolt
System
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DRP
First A predictable and adaptivepiece wireless network
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Wireless network Low-power Multi-hop
Controller
Actuator
Sensor
First A predictable and adaptivepiece wireless network
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Wireless network Low-power Multi-hop
Controller
Actuator
Sensor
State-of-the-art wireless protocolsare predictable or adaptive
Splash, RAP EfficientAdaptive> not Predictable
WirelessHART PredictableEfficient> not Adaptive
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Blink A real-time, reliable and[1] adaptive wireless protocol
Adaptive Based on Glossy> Flooding primitive
Reliable Average 99.97% reception rate> Multiple testbeds> Tested up to 94 nodes
Real-time Online scheduling> EDF-based Lazy Scheduling
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[1] Zimmerling M. et al., Adaptive Real-time Communication for Wireless Cyber-physical SystemsTo appear in ACM Transactions on Cyber-Physical Systems, 2016
Blink A real-time, reliable and[1] adaptive wireless protocol
Abstraction Low-power Wireless Bus (LWB)> MAC protocol
Communication TDMA-basedin rounds > Sleep between rounds
> Wireless yields sync!
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ππππ‘
πΆπππ‘
π‘
π‘
π‘
Node 1
Node 2
Node N
β¦
M slots
β¦β¦
β¦
[1] Zimmerling M. et al., Adaptive Real-time Communication for Wireless Cyber-physical SystemsTo appear in ACM Transactions on Cyber-Physical Systems, 2016
Variable!
Sched(n+1)
Blink A real-time, reliable and[1] adaptive wireless protocol
Abstraction Low-power Wireless Bus (LWB)> MAC protocol
Communication TDMA-basedin rounds > Sleep between rounds
> Wireless yields sync!
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ππππ‘
πΆπππ‘
π‘
π‘
π‘
Node 1
Node 2
Node N
β¦
M slots
β¦β¦
β¦
[1] Zimmerling M. et al., Adaptive Real-time Communication for Wireless Cyber-physical SystemsTo appear in ACM Transactions on Cyber-Physical Systems, 2016
Variable!
Design goals
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
na
na
?
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Blink Bolt DRP
Second A dual-processor architecturepiece to mitigate local interference
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Wireless network Low-power Multi-hop
Controller
Actuator
Sensor
Second A dual-processor architecturepiece to mitigate local interference
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Wireless network Low-power Multi-hop
Controller
Actuator
Sensor
Bolt A dual-processor architecture [2] to mitigate local interference
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BOLTBOLT
APIBOLT
API
β¦
β¦Receive Buffer
flush
read
write
β¦
Wireless Comm. Tasks
ApplicationTasks
Communication Processor (CP)
β¦
Receive Buffer
flush
read
write
Application Processor (AP)
Incoming
Outgoing
Real-time Formally verifiedbehavior Implemented, tested, deployed
Efficient ππ > sleepππ > active
Composable Hardware/Softwarefree composition
[2] Sutton F. et al., Bolt: A Stateful Processor Interconnect, SenSysβ15, 2015
Design goals
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
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?
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Blink Bolt DRP
na
na
Design goals β How can we fill the blanks?
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
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Blink Bolt DRP
? na
na
Third Distributed Real-time Protocol (DRP)piece
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
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Blink Bolt DRP
na
na
DRP is based on three main concepts
Communication is constrained within registered flows only
Global requirements are splitedacross distributed components
Interaction between componentsis based on contracts
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DRP is based on three main concepts
Communication is constrained within registered flows only
Global requirements are splitedacross distributed components
Interaction between componentsis based on contracts
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Communication is constrained within registered flows only
Flow π πΉπ = ( πππ , ππ
π , ππ , π½π , ππ )
Release model Sporatic with jitter
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SourceDestinationMin. release intervalJitterEnd-to-end deadline
DRP is based on three main concepts
Communication is constrained within registered flows only
Global requirements are splitedacross distributed components
Interaction between componentsis based on contracts
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Global requirements are splitedacross distributed components
DRP : π·ππ + π·π
πππ‘ + π·ππ = π
end-to-end deadline : π
π·ππ π·π
πππ‘ π·ππ
Wireless protocolSource Destination
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Real-timeguarantee
DRP is based on three main concepts
Communication is constrained within registered flows only
Global requirements are splitedacross distributed components
Interaction between componentsis based on contracts
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Interaction between componentsis based on contracts
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> Node β Network
> Max resource demandMin service delivered
>
Contract
CONSTRAINTS
ON LOCAL
SCHEDULES
BB
AA
Predictability Performance
Example
Scheduling of Communication Processors (CP)
Real-time Participate in rounds guarantees > ππππ‘ Blink schedule
Flush before roundsWrite after rounds> ππππ‘ Blink schedule
Buffer Flush Bolt regularlymanagement > ππ
π Comm. Processorschedule
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Example
Scheduling of Communication Processors (CP)
How can we guarantee that all tasks are schedulable?
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πΆπ πΆπ€
Participate in rounds
Flush before rounds
Write after rounds
Flush Bolt regularly
πππ
π‘
πΆπππ‘
ππππ‘
π‘
Example
Scheduling of Communication Processors (CP)
How can we guarantee that all tasks are schedulable?
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πΆπ πΆπ€
Participate in rounds
Flush before rounds
Write after rounds
Flush Bolt regularly
πππ
π‘
Variable!
Variable!
πΆπππ‘
ππππ‘
π‘
πΆπππ‘
ππππ‘
Example
Scheduling of Communication Processors (CP)
How to guarantee that all tasks are schedulable?
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πΆπ πΆπ€
π‘
Participate in rounds
Flush before rounds
Write after rounds
Flush Bolt regularly
Variable!
Variable! Conflict!πππ
π‘
Example
Scheduling of Communication Processors (CP)
How to guarantee that all tasks are schedulable?
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πΆπ πΆπ€πΆπππ‘
ππππ‘
Participate in rounds
Flush before rounds
Write after rounds
Flush Bolt regularly
πΆπΆπ β πΆπ + πΆπππ‘ + πΆπ€> ππππ‘ β π β πΆπΆπ
Solution TDMA approach
Variable!
Variable!
π‘πππ
π‘
Example
Scheduling of Communication Processors (CP)
How to guarantee that all tasks are schedulable?
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πΆπ πΆπ€
Participate in rounds
Flush before rounds
Write after rounds
Flush Bolt regularly
π‘πππ
πΆπΆπ β πΆπ + πΆπππ‘ + πΆπ€> ππ
π β πΆπΆπ> ππππ‘ β π β πΆπΆπ
Fixed to min
Solution TDMA approach
Variable!
πΆπππ‘
ππππ‘
π‘
Example
Scheduling of Communication Processors (CP)
How to guarantee that all tasks are schedulable?
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πΆπ πΆπ€πΆπππ‘
ππππ‘
Participate in rounds
Flush before rounds
Write after rounds
Flush Bolt regularly
π‘πππ
πΆπΆπ β πΆπ + πΆπππ‘ + πΆπ€> ππ
π β πΆπΆπ> ππππ‘ β π β πΆπΆπ
Variable but constrained
Solution TDMA approach
π‘
Fixed to min
+ Predictability of Network + Predictability of Devices + DRP contracts
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End-to-end latencyBuffer size
Flush interval πππ
Flush interval πππ
Network deadline π·ππππ‘
End-to-end deadlineMemory spaceβ€
= System predictability Worst-Case Analysis
= π( Local parameters )
Can we set localparameters such thatβ¦
If YES System predictabilityby design
Ultimately
Design goals
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
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?
?
?
?
?
Blink Bolt DRP
na
na
Predicatability
Design goals
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
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?
?
?
?
?
Blink Bolt DRP
na
na
From there, adaptability is one (close) step away
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End-to-end latencyBuffer size
End-to-end deadlineMemory spaceβ€
Can we set localparameters such thatβ¦
ADMISSION
TESTS
From there, adaptability is one (close) step away
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ADMISSION
TESTS
Depends only on local parameters!
Example
Communication Processor
Adaptability is achieved via a distributed registration scheme
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LOGICAL LAYER
PHYSICAL LAYER
request : ππ , π½ππ·π , πi YES Y
APs CPsBOLT APdBOLTCPdBLINKPacket
flow
Bolt buffer andlocal memory OK?
Abort
Register flow
Abort
Register flow
Abort
Register flow and update schedule
YES
Abort
Register flow andupdate schedule
Abort
Register flow and update schedule
Compute π·π
ππ , π½ππi
Networkschedule OK?
Local memory OK?
update : πππ
YES
nack
ack
end-to-end latency β€ πi
YES
REGISTRATION
SCHEMEADMISSION
TESTS
NO NO NO NO
π(πππ , π·π) π(ππ
π)
Bolt buffer
and πππ OK?
nack
ack
nack
ack
nack
ack
Predicatability
Design goals
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
?
?
Blink Bolt DRP
na
na
Adaptability
The detailed system analysis allows for performance optimization
Minimal admissible end-to-end deadline
ππππ = πΏπππππ π‘ + ππππ + ππππ + πΏπ
ππππ π‘ + ππ,ππππ
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PacketflowAPs CPsBOLT APdBOLTCPdBLINK
end-to-end latency β₯ ππππ
The detailed system analysis allows for performance optimization
Minimal admissible end-to-end deadline
ππππ = πΏπππππ π‘ + ππππ + ππππ + πΏπ
ππππ π‘ + ππ,ππππ
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PacketflowAPs CPsBOLT APdBOLTCPdBLINK
end-to-end latency β₯ ππππBolt delays
Source delay> Message release by the source> Available for communication
The detailed system analysis allows for performance optimization
Minimal admissible end-to-end deadline
ππππ = πΏπππππ π‘ + ππππ + ππππ + πΏπ
ππππ π‘ + ππ,ππππ
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PacketflowAPs CPsBOLT APdBOLTCPdBLINK
end-to-end latency β₯ ππππ
Network delay: Waiting time > Message available> Message processed by the network
The detailed system analysis allows for performance optimization
Minimal admissible end-to-end deadline
ππππ = πΏπππππ π‘ + ππππ + ππππ + πΏπ
ππππ π‘ + ππ,ππππ
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PacketflowAPs CPsBOLT APdBOLTCPdBLINK
end-to-end latency β₯ ππππ
Network delay: Transmission > Message processed by the network> Message transmitted to the destination node
The detailed system analysis allows for performance optimization
Minimal admissible end-to-end deadline
ππππ = πΏπππππ π‘ + ππππ + ππππ + πΏπ
ππππ π‘ + ππ,ππππ
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PacketflowAPs CPsBOLT APdBOLTCPdBLINK
end-to-end latency β₯ ππππ
Destination delay: Bolt > Message transmitted to the destination node> Message available in the Bolt queue
The detailed system analysis allows for performance optimization
Minimal admissible end-to-end deadline
ππππ = πΏπππππ π‘ + ππππ + ππππ + πΏπ
ππππ π‘ + ππ,ππππ
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PacketflowAPs CPsBOLT APdBOLTCPdBLINK
end-to-end latency β₯ ππππ
Destination delay: Application > Message available in the Bolt queue> Message retrieved by the destination application
The detailed system analysis allows for performance optimization
Minimal admissible end-to-end deadline
ππππ = πΏπππππ π‘ + ππππ + ππππ + πΏπ
ππππ π‘ + ππ,ππππ
Given Packet size 32 Bytes
πΆπππ‘ 1 π
ππ,ππππ 0.1 π
> ππππ 3.46 π Max data rate 29.7 π΅ππ per flow
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Predicatability
Design goals
Real-time guarantees
Buffer management
Adaptability
Efficiency
Composability
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Network Device System
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Blink Bolt DRP
na
na
Using flooding primitives
enables the design of both
adaptive AND predictable
Wireless Cyber-Physical Systems
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End-to-end Real-time Guarantees in Wireless Cyber-physical Systems
Romain JacobPengcheng Huang Lothar Thiele
RTSS 16 - IoT and Networking SessionDecember 1, 2016
Marco ZimmerlingJan Beutel
Simulation correlates closely with the analysis
Typical simulation trace result
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