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As geometries shrink and clock frequencies increase, timing-clean designs could fail on silicon due to lowered operating voltage caused by static and instantaneous IR drop, increased leakage, and temperature variation. Cadence® Encounter® Power System enables designers to analyze and debug power and IR drop across multimillion-gate designs with significant gains in productivity. It provides a complete signoff solution in combination with Encounter Timing System and Encounter Library Characterizer, delivering comprehensive timing, signal integrity, thermal, power, power grid, and statistical characterization and analysis with a common user interface, constraints, commands, debug, and reporting.

ENCOUNTER POWER SYSTEM

EncountEr PowEr SyStEmEncounter Power System offers designers a complete and accurate view of gate and grid power, IR drop, electromigration, and statistical and thermal analysis – for all technology nodes – delivering the utmost in productivity, precision, and performance for the most complex advanced node designs.

Encounter Power System and its native production-proven VoltageStorm® signoff engines have been in use for more than a decade with thousands of successful tapeouts for both analysis and in-design optimization. It is used across the implementation flow, spanning floorplanning, power planning, design optimization, and signoff, to provide consistent, converging results at every step of the flow. Encounter Power System helps front-end logic designers looking for high-quality early rail analysis and ease of use, as well as back-end physical designers looking for comprehensive signoff analysis and silicon correlation.

comPlEtE PowEr intEgrity analySiS

Encounter Power System provides a comprehensive static and dynamic power, IR drop, and electromigration analysis solution with advanced debugging capabilities, easy Power Grid View (PGV) library generation, and input data validation. Designed for optimal usability, accuracy, and runtime, it enables designers to rapidly check that the power rails can supply the amount of power needed by the design. Designers can use it for accurate power estimation, optimal I/O placement, study of package impact on IR drop, power stripe size, and pitch correction, and via and connection problem identification.

The Encounter Power System power estimation engine enables Verilog®-based early gate-level power estimation, as well as DEF-based signoff power calculation. It leverages the Encounter Timing System signoff timing engine for accurate slew and arrival windows needed during power estimation. With hierarchical vectorless

and vector-based dynamic analysis, Encounter Power System helps designers identify areas of high dynamic current caused by simultaneously switching logic. Encounter Power System identifies the amount of de-coupling capacitance needed to fix such dynamic IR drop violations. It also allows de-coupling capacitance and power-switch optimization, rush-current and turn-on-time analysis for shut-off blocks, clock jitter and skew analysis, and package/die co-design.

An essential part of any deep sub-micron design, Encounter Power System is available in L and XL configurations. An Encounter Power System Advanced Analysis Option is also available.

2www.cadence.com ENCOUNTER POWER SYSTEM

BEnEfitS• Deliversconsistent,integratedpower

and IR drop analysis across the implementation flow, from floorplanning through optimization and signoff

– Early rail analysis (ERA) at floor/power planning stages allows correct-by-construct power-grid design

– Consistent Encounter-integrated and standalone use model improves productivity

– Integration with Encounter platform technologies allows access to physical database and on-the-fly engineering change orders (ECOs)

• Providesaunifiedsignoffanalysissolution

– Integration with Encounter Timing System enables analysis of IR drop-induced delay variability across data and clock networks, such as clock jitter and skew analysis

– Provides consistent engines, interface, and commands across the flow

• Performscomprehensivefull-chipandpackage IR drop analysis

– Power grid views of analog, mixed-signal, custom-digital, or full digital blocks allow true full-chip IR drop analysis

– Supports chip/package co-design through package and die model exchange with Allegro® Package Designer

• Boostsproductivityandshavesweeksoff tapeout schedules

– Multi-CPU support ensures high performance

– Pipelined methodology ensures high capacity and throughput

– Performs incremental and what-if analysis and exploration

– Supports the Common Power Format (CPF)

– Provides a GUI-driven and interactive Tcl command interface

• Allowseasydebugging

– Global Power Debug speeds up root cause analysis

– Integrated waveform and layout viewers enable fast power and IR debugging

• Offersadvancednodeanalysiscapabilities

– Performs manufacturing-aware extraction for advanced nodes

– Performs thermal and statistical leakage power analysis

– SupportsBlechLengthforaccurateelectromigration analysis

• Supportedbymajorfoundries,ASICand IP vendors, and integrated device manufactures

fEaturES

comPrEhEnSivE PowEr and PowEr grid vErification

• Flexible,consistentpowerengineusedfor power estimation across the implementation flow

• Gate-levelpowerestimationusingVerilog as input for early power estimation, with full RTL and gate-level VCD and SAIF support

• Accuratepost-placementandroutingpower estimation for power grid optimization and signoff

EaSy liBrary gEnEration

• DetailedPowerGridView(PGV))generation using easily available Spice sub-circuits

• DetailedPGVgenerationusingindustry-standard LVS rule decks

• On-the-flydeviceandcouplingcapacitance characterization using the embedded Spectre® SIMI

• Pass/Failreportcapabilitiestoanalyzecontents of PGVs with guidance on causes of failure

• Layout-awarePowerSystemViewer(PSViewer) for graphically viewing and debugging PGVs

• Automaticspawningoflibrarygenerationjobs for macros and memories

SEamlESS data imPort and inPut data Sanity chEcking

• FlexibledesignimportsusingEncounterdatabase, OpenAccess, or third-party designs

Figure 1: Power and IR drop cross probing and waveforms

3www.cadence.com ENCOUNTER POWER SYSTEM

• Embeddeddesignsanitycheckssuchascompleteness of LEF library data, timing library data, physical and logical netlist annotation, and SPEF annotation

• Faststructuralpowergridverificationtoidentify missing vias and disconnected power pins

• AccesstotheEncounterTimingSystemsignoff timing engine, enabling fast timing database queries for slews and arrival times

PowErful gui

• CommandconsolewithfullTclsupport,command completion, history, and context highlighting

• Scripteditortoevaluatescriptswithability to crosslink and expand Tcl procedures

EaSy dEBugging

• GlobalPowerDebugforanalyzingpower consumption at different levels of hierarchy, cell type, power net, power domain, clock domain, etc., with pie charts and histograms

• Integratedfull-featuredwaveformviewer enables study of dynamic power and IR drop waveforms, with composite waveform creation capabilities across design hierarchies and clock domains

• EmbeddedEncounterlayoutviewerwith ability to cross-probe power and IR drop information

• Instance-basedeffectiveresistanceplotswith automatic least-resistive path highlighting

• HTMLreportingforeasyresultnavigation

• Fastwhat-ifanalysisenablingquickexperimentation

Early rail analySiS (Era)

Floorplanning and power planning designers can use Encounter Power System engines to rapidly prototype their I/O placement, macro placement, and power grid structure early in the design. Consistency of the engines between early rail analysis and Encounter Power System removes correlation risks, improves productivity, and speeds design closure.

vEctor Profiling

Encounter Power System includes multiple vector profiling options to help designers study VCD profiles textually and graphically. Activity-based vector profiling enables fast identification of high activity regions of VCDs. A fast vector power-profiling option calculates switching power of the design over time. The accurate vector power-profiling option allows full power estimation of a VCD, with activity propagation capabilities for non-annotated nodes.

Figure 2: Global Power Debug

Figure 3: Effective resistance plots with automatic least-resistive path highlighting

Effective resistance Plots

highlighting weak connections

automatic least resistive

path highlighting

4www.cadence.com ENCOUNTER POWER SYSTEM

automatic dE-couPling caPacitancE oPtimization

Encounter Power System can calculate and recommend the amount of additional de-coupling capacitance necessary to limit the dynamic IR drop to user-specified limits. This recommended additional de-coupling capacitance can then drive an automated optimization flow throughout the Encounter Platform, where filler cells are swapped with de-coupling capacitance cells. For low-power designs, this flow can be used to remove extra de-coupling capacitance cells in the design, improving leakage and yield.

PackagE/diE co-dESign

Encounter Power System integration with Allegro Package Designer enables easy hand-off of package and die models. Encounter Power System enables chip designers to create an abstract parasitics and dynamic current profile of the die for package designers. It also takes in 2 or n-port package models to enable accurate IR drop analysis, taking into account the package effects.

analySiS of ir droP imPact on timing and Signal intEgrity

Encounter Power System calculates instance operating voltages based on the switching windows associated with each instance. It then provides this

information to Encounter Timing System, which calculates the impact of IR drop on delay- and signal integrity-generated noise. Encounter Power System can also generate dynamic IR drop and ground-bounce waveforms for critical paths, allowing Encounter Timing System to accurately trace and analyze such paths.

analySiS of ir droP-inducEd dElay variaBility on clock and data nEtworkS

The delay variation introduced by instantaneous rail voltage changes on the clock network can cause set-up and hold violations in a design. The different delays seen on the clock and data networks could introduce further set-up and hold violations.Bymonitoringtheeffectiveoperating voltage of the clock and data network elements, Encounter Power System enables Encounter Timing System to more accurately analyze clock jitter, skew, and delay variability across clock and data networks. This analysis allows Encounter Timing System to identify problematic clock network elements and to create and run a complete jitter-sensitized Spice trace.

PowEr-Switch oPtimization

Today, many low-power designs include switched blocks through the use of power switches. These blocks are only turned on when needed, saving leakage power

while the blocks are not in use. Encounter Power System analyzes power-on and power-off scenarios of these blocks, creating engineering change orders (ECOs) to optimize power switch size and location. This ensures the block’s rush current during power-up will not impact the neighboring logic, and that the static and dynamic IR drop within the block is within expected budgets.

comPrEhEnSivE ir droP analySiS Solution

Encounter Power System uses Power Grid Views (PGVs) as the building blocks for hierarchical power grid analysis. The VoltageStorm family of products, such as VoltageStorm Transistor and Virtuoso® Analog VoltageStorm Option, analyze IR drop across custom-digital and analog/mixed-signal blocks accordingly. After this analysis, both products create PGVs for use in Encounter Power System during full-chip static and dynamic runs. This allows study of IR drop across the entire chip, taking into account digital, custom block, and analog domains’ power grid interactions.

thErmal and StatiStical analySiS

Designed for advanced nodes, Encounter Power System allows designers advanced analysis features such as thermal and statistical leakage power analysis (SLPA). Worst-case leakage has a very low probability of occurring across the entire chip, and leakage distributions have long tails that make worst-corner analysis very pessimistic. Using SLPA, designers can capture a more realistic picture of their design’s leakage power distribution. SLPA accounts for global, within-the-die, and random variation. It enables designers to spend less time fixing leakage problems that are very unlikely to occur. Thermal analysis allows users to study the impact of power on temperature variations across the die, which in turn impact leakage and power consumption, and hence IR drop. It also helps designers ensure proper cooling of the die to avoid thermal runaways.

Figure 4: HTML reports

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for more information, contact cadence sales at:1.800.746.6223Email us at:info@cadence.com or log on to:www.cadence.com

Standard intErfacE SuPPort• Mandatorydesigndata

– Timing libraries

– Verilog

– SDC

– LEF

– DEF

– SPEF

– Spice Subckts and GDS for design components

– Power pad location

– Extraction tech file for QRC or process file

• Optionaldesigndata

– Common Power Format (CPF) file

– Package model

– VCD

SPEcificationS

PlatformS

•SunSolaris8or9(32-bit,64-bit)

•HP-UX11.0(32-bit,64-bit)

•OpteronLinuxRHEL3.0(64-bit)

•RedHatLinuxRHEL2.1(32-bit)

•IBMAIX5.1(32-bit,64-bit)

cadEncE SErvicES and SuPPort•Cadenceapplicationengineerscan

answer your technical questions by telephone, email, or internet — they can also provide technical assistance and custom training

•SourceLink® online customer support gives you answers to your technical questions—24hoursaday,7daysaweek — including the latest in quarterly software rollups, product release information, technical documentation, software updates, and more

•Cadence-certifiedinstructorsteachmorethan80coursesandbringtheirreal-world experience into the classroom

•Morethan25InternetLearningSeries(iLS) online courses allow you the flexibility of training at your own computer via the Internet

EncounterPowerSystem

DEF Verilog

= Required Input= Input for Library Generation

TimingLibraries

PowerPads

Package

SDC

VCD

LEF

GDS SpiceSubckts

SPEF

PowerReports

IRdrop/EMReports

IRdropWaveforms

IRdrop/EMPlots

PowerPlots

PowerWaveforms

= Optional Input= Output

Figure 5: Encounter Power System inputs and outputs