ELEN468 Advanced Logic Design
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ELEN468 Lecture 1 1 ELEN468 Advanced Logic Design Lecture 1 Introduction
description
ELEN468 Advanced Logic Design. Lecture 1 Introduction. Chips Everywhere!. What are inside a chip?. A chip may include: Hundreds of millions of transistors ~Mb embedded SRAM DSP, IP cores PLL, ADC, DAC… 100+ internal clocks … … Design issues: Speed Power Area Signal integrity - PowerPoint PPT Presentation
Transcript of ELEN468 Advanced Logic Design
ELEN468 Lecture 1 1
ELEN468 Advanced Logic Design
Lecture 1 Introduction
ELEN468 Lecture 1 2
Chips Everywhere!
ELEN468 Lecture 1 3
What are inside a chip?A chip may include:
Hundreds of millions of transistors ~Mb embedded SRAM DSP, IP cores PLL, ADC, DAC… 100+ internal clocks … …
Design issues: Speed Power Area Signal integrity Process variation Manufacturing yield … … Source: Byran Preas
ELEN468 Lecture 1 4
Technology Roadmap for Semiconductors
109-109-10987-8Wiring levels
288251218190160140Power (W)
287511934811511673939902317Clock freq. (MHz)
2854M1427M714M357M178M112M# transistors
201620132010200720042002Year
2232456590115Technology (nm)
Technology minimal transistor feature size
ELEN468 Lecture 1 5
Chip Design Productivity Crisis
xxx
xxx
x
21%/Yr. Productivity growth rate
x
58%/Yr. Complexity growth rate
1
10
100
1,000
10,000
100,000
1,000,000
10,000,000
199810
100
1,000
10,000
100,000
1,000,000
10,000,000
100,000,000
Tra
nsi
stor
s/C
hip
(K
)
Tra
nsi
stor
/Sta
ff-M
onth
2003
Source NTRS’97
ELEN468 Lecture 1 6
Solutions
Apply CAD tools High level abstraction
Learn VerilogVerilog !
ELEN468 Lecture 1 7
Basic Design Flow System design
Instruction set for processor Hardware/software partition Memory, cache
Logic design Logic synthesis Logic optimization Technology mapping
Physical design Floorplanning Placement Routing
System/Architectural Design
Logic Design
Physical Design/Layout
Fabrication
ELEN468 Lecture 1 8
Design CyclesSystem/Architectural Design
Logic Design
Physical Design/Layout
Fabrication
HDL
Verification/Simulation
Parasitic Extraction
Testing
ELEN468 Lecture 1 9
Design and Technology Styles
Custom design Mostly manual design, long design cycle High performance, high volume Microprocessors, analog, leaf cells, IP …
Standard cell Pre-designed cells, CAD, short design cycle Medium performance, ASIC
FPGA/PLD Pre-fabricated, fast automated design, low
cost Prototyping, reconfigurable computing
ELEN468 Lecture 1 10
Why do we need HDLs ?
HDL can describe both circuit structure and behavior Schematics describe only circuit structure C language describes only behaviors
Provide high level abstraction to speed up design High portability and readability Enable rapid prototyping Support different hardware styles
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What do we need from HDLs ?
Describe Combinational logic Level sensitive storage devices Edge-triggered storage devices
Provide different levels of abstraction and support hierarchical design
System level RTL level Gate level Transistor level Physical level
Support for hardware concurrency
ELEN468 Lecture 1 12
Two major HDLs
Verilog Slightly better at gate/transistor level Language style close to C/C++ Pre-defined data type, easy to use
VHDL Slightly better at system level Language style close to Pascal User-defined data type, more flexible
Equally effective, personal preference
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Schematic Design
a
b
Add_half
sum
c_out
sum = a b
c_out = a • b
a
b sum
c_out
c_out_bar
ELEN468 Lecture 1 14
Module portsModule name
Verilog keywords
Taste of Verilog
module Add_half ( sum, c_out, a, b ); inputa, b;output sum, c_out;wire c_out_bar;
xor (sum, a, b);nand (c_out_bar, a, b);not (c_out, c_out_bar);
endmodule
Declaration of port modes
Declaration of internal signal
Instantiation of primitive gates
c_out
a
b sum
c_out_bar
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Behavioral Description
module Add_half ( sum, c_out, a, b ); inputa, b;output sum, c_out;reg sum, c_out;always @ ( a or b ) begin
sum = a ^ b; // Exclusive or
c_out = a & b; // And end
endmodule
a
b
Add_half
sum
c_out
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Example of Flip-flopmodule Flip_flop ( q, data_in, clk,
rst );input data_in, clk, rst;output q;reg q;
always @ ( posedge clk ) begin
if ( rst == 1) q = 0;else q = data_in;
endendmodule
data_in
q
rst
clk
Declaration of synchronous behavior
Procedural statement
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Conclusion
VLSI Chips Chip design flow Chip design styles Why do we need HDLs ? What do we need from HDLs ? Examples of Verilog HDL
