Advanced Digital Logic Design

EE365Adv. Digital Circuit DesignClarkson University

Lecture #3Combinational Logic

Combinational-Circuit AnalysisCombinational circuits -- outputs depend only on current inputs (not on history).Kinds of combinational analysis:exhaustive (truth table)algebraic (expressions)simulation / test bench (example in lab #2)Write functional description in HDLDefine test conditions / test vecors, including corner casesCompare circuit output with functional description (or known-good realization)Repeat for random test vectors

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Combinational-Circuit DesignSometimes you can write an equation or equations directly using logic (the kind in your brain).Example (alarm circuit):

Corresponding circuit:Rissacher EE365Lect #3

Alarm-circuit transformationSum-of-products formUseful for programmable logic devices (next lec.)

Multiply out:Rissacher EE365Lect #3

Sum-of-products formRissacher EE365Lect #3

Product-of-sums formP-of-S preferred in CMOS, TTL (NAND-NAND)Rissacher EE365Lect #3

Brute-force designTruth table --> canonical sum (sum of minterms)Example: prime-number detector4-bit input, N3N2N1N0row N3 N2 N1 N0 F 0 0 0 0 0 0 1 0 0 0 1 1 2 0 0 1 0 1 3 0 0 1 1 1 4 0 1 0 0 0 5 0 1 0 1 1 6 0 1 1 0 0 7 0 1 1 1 1 8 1 0 0 0 0 9 1 0 0 1 010 1 0 1 0 011 0 0 1 1 112 1 1 0 0 013 1 1 0 1 114 1 1 1 0 015 1 1 1 1 0F = SN3N2N1N0(1,2,3,5,7,11,13)Rissacher EE365Lect #3

Minterm list --> canonical sumRissacher EE365Lect #3

Algebraic simplificationTheorem T8,

Reduce number of gates and gate inputsRissacher EE365Lect #3

Resulting circuitRissacher EE365Lect #3

Visualizing T10 -- Karnaugh mapsRissacher EE365Lect #3

3-variable Karnaugh mapRissacher EE365Lect #3

Example: F = S(1,2,5,7)Rissacher EE365Lect #3

Karnaugh-map usagePlot 1s corresponding to minterms of function.Circle largest possible rectangular sets of 1s.# of 1s in set must be power of 2OK to cross edgesRead off product terms, one per circled set.Variable is 1 ==> include variableVariable is 0 ==> include complement of variableVariable is both 0 and 1 ==> variable not includedCircled sets and corresponding product terms are called prime implicantsMinimum number of gates and gate inputsRissacher EE365Lect #3

Prime-number detector (again)Rissacher EE365Lect #3

Prime-number detector (again)When we solved algebraically, we missed one simplification -- the circuit below has three less gate inputs.Rissacher EE365Lect #3

Another exampleRissacher EE365Lect #3

Yet another example

Distinguished 1 cellsEssential prime implicantsRissacher EE365Lect #3

POS

Circle 0sUse DeMorgans to invert the equation Rissacher EE365Lect #3F = (WYX)+(XZ)F = ((WYX)+(XZ))F = (WYX)(XZ)F = (W+Y+X)(X+Z)

POSNote that the textbook author likes to draw the Karnaugh map for the F function, thus you would circle the 1s (where my examples show the F function and 0s are cirlced).Rissacher EE365Lect #3

In-Class Practice ProblemUsing Karnaugh maps, find the minimal SOP and POS terms for:F=W,X,Y,Z(0,2,5,7,8,10,13,15)


In-Class Practice ProblemRissacher EE365Lect #3SOP:POS:Z XX Z

Quine-McCluskey algorithmThis process can be made into a program, using appropriate algorithms and data structures.Guaranteed to find minimal solutionRequired computation has exponential complexity (run time and storage)-- works well for functions with up to 8-12 variables, but quickly blows up for larger problems.Heuristic programs (e.g., Espresso) used for larger problems, usually give minimal results.Rissacher EE365Lect #3

Lots of possibilitiesCan follow a dual procedure to find minimal products of sums (OR-AND realization)Can modify procedure to handle dont-care input combinations.Can draw Karnaugh maps with up to six variables.Rissacher EE365Lect #3

Real-World Logic DesignSome applications have lots more than 6 inputscant use Karnaugh mapsDesign correctness more important than gate minimizationUse higher-level language to specify logic operationsUse programs to manipulate logic expressions and minimize logic.PALASM, ABEL, CUPL -- developed for PLDsVHDL, Verilog -- developed for ASICsRissacher EE365Lect #3

VHDLWe will be using VHDL for all design projectsWe generally wont be using VHDL to help with minimization, rather as a method to simulate simple logic circuits built with MSI componentsThe following slides will cover the basic syntax of using VHDL for our purposesProgram usage (e.g., Xilinx Modelsim) and program/circuit testing will be covered in a separate tutorial


VHDL TopicsObjectivesVHDL HistoryApplication AreasDesign UnitsEntity DescriptionsArchitecture DescriptionsPackage and Package BodyConfigurationA Range of Design ExamplesRissacher EE365Lect #3

VHDL TopicsLevels of AbstractionArchitecture TypesModeling BehaviorModeling StructureExamplesTest BenchesDesign Process overview and summary


ObjectivesIntroduce the basics of VHDL.Gain a level of understanding that allows you to write VHDL code for any design that you could enter using a schematic editor and standard parts.Develop an appreciation for the ability of VHDL to handle mixed designs (structural, dataflow, and behavioral).Learn VHDL at a level that would allow you to realize your designs in CPLD or FPGA circuits and to test them.Rissacher EE365Lect #3

VHDL HistoryVHSIC Hardware Design LanguageVery High Speed Integrated CircuitDoD sponsored development, thus non-proprietary languageStandardized by the IEEE in 1987IEEE Standard Logic Package (1164) added to handle simulation of practical digital signal values (e.g. high impedance, pull-ups, etc.)VHDL standard extended in 1993Additional standards and enhancements continueRissacher EE365Lect #3

Application Areas for VHDLSystem SpecificationDesign Entry (capture)SimulationSynthesis (and fitting)Test DevelopmentTiming VerificationDocumentationRissacher EE365Lect #3

VHDL Design UnitA set of VHDL statements that can be compiled separately and stored in a library for later use.Five types of design units:Entity descriptionArchitecture descriptionPackagePackage bodyConfigurationRissacher EE365Lect #3

Entity DescriptionDescribes the input and output of one module in a system.Hides the detailed inner workings of the moduleMay be used to describe modules at a very low level (e.g. gate level) as well as an entire system, and all levels in betweenRissacher EE365Lect #3

Modeling InterfacesEntity declarationdescribes the input/output ports of a moduleentity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end entity reg4;entity nameport namesport mode (direction)port typereserved wordspunctuationRissacher EE365Lect #3

VHDL-87Omit entity at end of entity declarationentity reg4 is port ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit ); end reg4;Rissacher EE365Lect #3

Architecture DescriptionProvides a functional or structural description of an entity.Each architecture is bound to only one entity but an entity may be associated with multiple architectures (only one during any given simulation or synthesis).Multiple architectures allow for early descriptions of module performance without having to design everything in order to begin functional testing.Rissacher EE365Lect #3

Package and Package BodyProvides a common place to gather globally used declarations of constants, signals, functions, procedures, components, etc. Package body contains the VHDL code for any functions or procedures declared in the package.Contents of a package are made available to other design units via the use statement.Rissacher EE365Lect #3

ConfigurationSpecifies which architectures are to be used for entities.Always optional; a default configuration is always provided.Generally not used for synthesis, but for functional simulation.Rissacher EE365Lect #3

A Range of Design ExamplesA simple, single part design:One VHDL source file with an entity architecture pair and a reference to a standard library (e.g. IEEE Standard Logic).A more complex design:Multiple source files, each with an entity architecture pair or with a package declaration.User as well as standard libraries.May include a configuration file.Rissacher EE365Lect #3

Levels of AbstractionAn important characteristic of VHDL that is not shared by earlier, PLD type languages (such as ABEL, CUPL, etc.) is the ability to represent designs at multiple levels of abstraction.Example a 16 bit adder could be represented as:Interconnections of gatesInterconnections of modules (e.g. full adder or 4-bit adder)A function that performs binary addition on two vectors of bitsRissacher EE365Lect #3

Architecture TypesBehavioralDescribes module performance over time, typically in the form of an algorithm.Ability to synthesize directly is limited.Dataflow (Register Transfer)Specifies registers and combinational logic in terms of data flowing from one function to another.StructuralSpecifies the components and their interconnectionsHDL equivalent of a schematicRissacher EE365Lect #3

Modeling BehaviorArchitecture bodydescribes an implementation of an entitymay be several per entityBehavioral architecturedescribes the algorithm performed by the modulecontainsprocess statements, each containingsequential statements, includingsignal assignment statements andwait statementsRissacher EE365Lect #3

Behavior Examplearchitecture behav of reg4 is beginstorage : process is variable stored_d0, stored_d1, stored_d2, stored_d3 : bit; begin if en = '1' and clk = '1' then stored_d0 := d0; stored_d1 := d1; stored_d2 := d2; stored_d3 := d3; end if; q0

VHDL-87Omit architecture at end of architecture bodyOmit is in process statement headerarchitecture behav of reg4 is beginstorage : process ... begin ... end process storage;end behav;Rissacher EE365Lect #3

Modeling StructureStructural architectureimplements the module as a composition of subsystemscontainssignal declarations, for internal interconnectionsthe entity ports are also treated as signalscomponent instancesinstances of previously declared entity/architecture pairsport maps in component instancesconnect signals to component portswait statementsRissacher EE365Lect #3

Structural ArchitectureComponents declared in an architecture must be defined elsewhere.Components may defined as:an entity-architecture pair in the same VHDL source file,an entity-architecture pair in another VHDL source file,an object in another design tool and supplied in a standard file format,an object in a technology library


Structural ArchitectureEach component type must be declared using a component declaration. The component declaration must match the entity declaration of the module being used.component component-nameport ( signal-names : mode signal-type; signal-names : mode signal-type; signal-names : mode signal-type );end component;Rissacher EE365Lect #3

Structural Architecture Each instance of a component must be instantiated by a component statement. First form uses order of signals matched to the component declaration.Second form uses port names as listed in the component declaration.label: component-name port map (signal1, signal2, , signaln);ORlabel: component-name port map (port1=>signal1, port2=>signal2, portn=>signaln):Rissacher EE365Lect #3

Structure ExampleRissacher EE365Lect #3

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Structure ExampleInclude component declarations in structural architecture bodytemplates for entity declarationsinstantiate componentswrite a configuration declarationoptional, only if more than one architecture is specified for a given entity.binds entity/architecture pair to each instantiated componentRissacher EE365Lect #3

Structure ExampleFirst declare D-latch and and-gate entities and architecturesentity d_latch is port ( d, clk : in bit; q : out bit ); end d_latch;

architecture basic of d_latch is beginlatch_behavior : process begin if clk = 1 then q

Structure ExampleDeclare corresponding components in register architecture bodyarchitecture struct of reg4 iscomponent d_latch port ( d, clk : in bit; q : out bit ); end component;component and2 port ( a, b : in bit; y : out bit ); end component;signal int_clk : bit;...Rissacher EE365Lect #3

Structure ExampleNow use them to implement the register...beginbit0 : d_latch port map ( d0, int_clk, q0 );bit1 : d_latch port map ( d1, int_clk, q1 );bit2 : d_latch port map ( d2, int_clk, q2 );bit3 : d_latch port map ( d3, int_clk, q3 );gate : and2 port map ( en, clk, int_clk );end struct;Rissacher EE365Lect #3

Mixed Behavior and StructureAn architecture can contain both behavioral and structural partsprocess statements and component instancescollectively called concurrent statementsprocesses can read and assign to signalsExample: register-transfer-level modeldata path described structurallycontrol section described behaviorallyRissacher EE365Lect #3

In-Class Practice ProblemWe want to write VHDL code for a buffer.Write an Entity for an Architecture that would take a single binary value, A, as an input, then pass it to the output, W, after 20ns.Rissacher EE365Lect #3

In-Class Practice Problementity buffer isport (A : in bit;W: out bit);end buffer;Rissacher EE365Lect #3

In-Class Practice ProblemNow write the behavioral ArchitectureWrite an Architecture that would take a single binary value, A, as an input, then pass it to the output, W, after 20ns.


In-Class Practice Problemarchitecture basic of buffer isbeginW

In-Class Practice ProblemNow create another instance of the same entity by writing a similar Architecture that only has a 5ns delay.


In-Class Practice Problemarchitecture fast of buffer isbeginW

Test BenchesTesting a design by simulationUse a test bench modelan architecture body that includes an instance of the design under testapplies sequences of test values to inputsmonitors values on output signalseither using simulatoror with a process that verifies correct operationRissacher EE365Lect #3

Test Bench Exampleentity test_bench is end entity test_bench;architecture test_reg4 of test_bench issignal d0, d1, d2, d3, en, clk, q0, q1, q2, q3 : bit;begindut : entity work.reg4(behav) port map ( d0, d1, d2, d3, en, clk, q0, q1, q2, q3 );stimulus : process is begin d0

Regression TestingTest that a refinement of a design is correctthat lower-level structural model does the same as a behavioral modelTest bench includes two instances of design under testbehavioral and lower-level structuralstimulates both with same inputscompares outputs for equalityNeed to take account of timing differencesRissacher EE365Lect #3

Design ProcessingAnalysisElaborationSimulationSynthesisRissacher EE365Lect #3

AnalysisCheck for syntax and semantic errorssyntax: grammar of the languagesemantics: the meaning of the modelAnalyze each design unit separatelyentity declarationarchitecture bodybest if each design unit is in a separate fileAnalyzed design units are placed in a libraryin an implementation dependent internal formcurrent library is called workRissacher EE365Lect #3

ElaborationFlattening the design hierarchycreate portscreate signals and processes within architecture bodyfor each component instance, copy instantiated entity and architecture bodyrepeat recursivelybottom out at purely behavioral architecture bodiesFinal result of elaborationflat collection of signal nets and processesRissacher EE365Lect #3

Elaboration ExampleRissacher EE365Lect #3

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Elaboration ExampleRissacher EE365Lect #3

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SimulationExecution of the processes in the elaborated modelDiscrete event simulationtime advances in discrete stepswhen signal values changeeventsA processes is sensitive to events on input signalsspecified in wait statementsresumes and schedules new values on output signalsschedules transactionsevent on a signal if new value different from old value


Simulation AlgorithmInitialization phaseeach signal is given its initial valuesimulation time set to 0for each processactivateexecute until a wait statement, then suspendexecution usually involves scheduling transactions on signals for later timesRissacher EE365Lect #3

Simulation AlgorithmSimulation cycleadvance simulation time to time of next transactionfor each transaction at this timeupdate signal valueevent if new value is different from old valuefor each process sensitive to any of these events, or whose wait for time-out has expiredresumeexecute until a wait statement, then suspendSimulation finishes when there are no further scheduled transactionsRissacher EE365Lect #3

SynthesisTranslates register-transfer-level (RTL) design into gate-level netlistRestrictions on coding styleSome constructs are not synthesizableSome constructs are synthesized in inefficient ways better to force the design to a lower, simpler levelRissacher EE365Lect #3

Basic Design MethodologyRissacher EE365Lect #3

How well SimulateRissacher EE365Lect #3We wont worry about writing test benchsWell be using a program called Wave (within Xilinx Modelsim) to look at inputs and outputs of the systems we buildA GUI is provided to edit input patterns

More VHDL HelpLink on course websiteRissacher EE365Lect #3Rissacher EE365Lect #3

Next timeVHDL tutorial in Computer LabQuiz

Transistor-Level Logic CircuitsCMOSTTLRissacher EE365Lect #3Rissacher EE365Lect #3

Advanced Digital Logic Design

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