Electrical characteristics and infrared absorbance of ... · Electrical characteristics and...

i

2012 Bachelor Thesis

Electrical characteristics and infrared

absorbance of reactively formed La-silicate for

gate dielectrics applications

Takuya Seki

Department of Electrical and Electronic Engineering

Tokyo Institute of Technology

Supervisor: Prof. Hiroshi Iwai

Prof. Kuniyuki Kakushima

February, 2012

ii

Abstract of Bachelor Thesis

Electrical characteristics and infrared absorbance of reactively

formed La-silicate for gate dielectrics applications

Supervisor: Prof. Hiroshi Iwai

Prof. Kuniyuki Kakushima

MOS device technology has been developed based on device scaling. Among various device parameters, thickness-scaling of gate oxide consisting of SiO2 has faced the fundamental limit. To overcome this limit high-k(dielectric constant) gate dielectrics have been investigated. One of the promising high-k materials is La2O3 because direct contact of high-k dielectric with Si substrate is possible by forming a La-silicate as a result of interfacial reaction. However, La-silicate is not clearly characterized from the view points of interface state density, oxide trap, and network structure. In this study interface and oxide trap are examined by conductance method, while network structure is examined by fourier transform infrared (FTIR) spectroscopy. Moreover, the influence of thermal annealing on the composition of La and Si has been investigated by x-ray photoelectron spectroscopy (XPS). The shift of conductance peak caused by annealing was confirmed. This result

provides the novel interpretation that traps are located at La-silicate/La2O3 interface. Moreover, interfacial state density can be reduced by annealing. A red-shift of the infrared absorption spectrum arising from longitudinal optical

phonon related with Si-O-Si bonds is observed. It indicates that strain inside La-silicate layer can be relaxed by annealing at high temperature thereby increasing thickness of La-silicate layer, which is confirmed by the analysis of X-ray photoelectron spectra. Annealing at high temperature modifies La-silicate network to approach an ideal one. The findings described above gives useful insights for gate dielectrics, which will

be used future MOS devices. February, 2012

Tokyo Institute of Technology

Department of Electrical and Electronic Engineering

08_13341 Takuya Seki

iii

Contents

Chapter 1. Introduction

1.1 Introduction of high-k materials as gate dielectrics............................1

1.2 Carrier trapping states at high-k dielectric/Si substrate interface......2

1.3 Density of interface states and oxide traps..........................................4

1.4 Purpose of this study……………………….......................................6

1.5 Conclusion………………………………….......................................6

References…………………………………………………………...……6

Chapter 2. Experiment and measurement procedures

2.1 Experimental procedures.....................................................................7

2.1.1 Wafer cleaning…………………………………………………..9

2.1.2 Deposition of La2O3 dielectristic by MBE………………….....10

2.1.3 RF magnetron sputtering………………………………………11

2.1.4 Patterning of resist by photo lithography……………………...11

2.1.5 Dry etching by RIE……………..……………………………..12

2.1.6 Post metallization annealing in F.G. ambient………………..13

2.1.7 Deposition of aluminum by vacuum evaporation……………14

2.2 Electrical measurement and physical analysis

2.2.1 Estimation of interface state density by conductance method

.............................................................................................................14

2.2.2 Fourier transform infrared spectroscopy (FTIR)........................16

2.2.3 X-ray photoelectron spectroscopy (XPS)...................................18

iv

2.3 Conclusion………………………………….....................................18

References…………………………………………………………..….. 20

Chapter 3. Electrical characteristics of La-silicate

gate dielectrics

3.1 Dependence of interface state density on annealing time ................21

3.2 Dependence of interface state density on annealing temperature.....26

3.3 Conclusion………………………………….....................................26

References…………………………………………………………..…...31

Chapter 4. Characterization of La-silicate gate

dielectrics by FTIR and XPS

4.1 FTIR spectrum of La-silicate gate dielectrics...................................32

4.2 XPS spectrum of La-silicate gate dielectrics….................................40

4.3 Conclusion………………………………….....................................41

References…………………………………………………………..….. 41

Chapter 5. Conclusion................................................................43

Acknowledgement........................................................................44

1

1.Introduction

1.1 Introduction of high-k materials as gate dielectrics

Metal-oxide-semiconductor field effect transistor (MOSFET) is one of the most

essential elements for very large scale integration (VLSI), which is commonly used

in most of the electronic equipments in PC, smart phone, and TV and so on.

Miniaturization of MOSFETs have been promoted by device scaling. Among various

device parameters, the physical thickness with gate dielectrics plays vital role in the

miniaturization. As SiO2 gate dielectrics has became thinner and thinner, leakage

current has increased to result in large amount of power consumption. One of the

solutions is to introduce high-k(dielectric constants) dielectrics with the same

capacitance enable to decrease leakage currents compared with SiO2 gate dielectrics

as illustrated in fig. 1.1.

High-k materials make it possible to thicken physical thickness with the same

equivalent oxide thickness (EOT). The EOT can be written as

oxhigh

SiO tEOTκκ

κ

−

= 2 , (1.1)

where κSiO2 and κhigh-κ are the permittivity of SiO2 and that of high-k materials,

respectively.

2

Fig. 1.1 High-k dielectrics make it possible to get larger physical

thickness than SiO2 with same gate capacitance.

1.2 Carrier trapping states at high-k dielectric/Si substrate interface High-k dielectrics have been extensively studied in recent years. Most of the high-k

materials require SiO2 dielectrics at the interface between high-k gate electrics and Si-substrate because of extremely low defect densities at SiO2/Si-substrate interface. However, by using interfacial layer of SiO2, it is impossible to realize EOT of 0.55 nm, which is required in near future, in fig. 1.2 [1.1], because of the scaling limit caused by the thickness of the interfacial layer.

Fig. 1.2 ITRS road map 2011 EOT versus YEAR plots in planer bulk MOSFETs.

EOT = 0.55 nm is required in 2016 [1.1]. One of the high-k dielectrics which does not form SiO2 at the surface is La2O3.

La2O3 is one of the promising material as high-k gate dielectrics because it has a

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2010 2011 2012 2013 2014 2015 2016 2017 2018

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ＥＯＴ

(nm

)

Year

Planer bulk MOS FET

0.55 nm

0.88 nm

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Planer bulk MOS FET

0.55 nm

0.88 nm

Si

SiO2

Gate

Gate

Si

High-k

S D S D

Same EOT and gate capacitance

Si

SiO2

Gate

Gate

Si

High-k

S D S D

Same EOT and gate capacitance

Si-substrate Si-substrate

3

high-k value and wide band gap. By using the La2O3 as a gate dielectrics, direct contact of high-k dielectric with Si-substrate can be obtained because La-silicate is formed as a result of interfacial reaction, as shown in fig.1.3 and fig.1.4 [1.2].

La-silicates are composed of La,Si,and O atoms. The composition of La-silicate is mainly dependent on annealing temperature and diffusion of oxygen from metal. La-silicate has higher dielectric constants than SiO2.

Si-substrate

La-Silicate

La2O3

Metal

Si-substrate

La2O3

Metal

Annealing

Fig. 1.3 The schematic illustration of La-silicate formed by interfacial reaction.

La2O3

La-silicate

W

500 oC, 30 min

1 nm

k=8~1

k=

PMA 500oC, 30min

Fig. 1.4 Cross sectional TEM image of high-k interfacial layer consisting of

La-silicate and La2O3 formed on Si substrate [1.2].

1.3 Density of interface states and oxide traps There is carrier trapping states at gate dielectric/Si interface [1.3]. The electrons which captured at the interface state do not contribute readily to electrical conduction current. The carrier mobility decreases because of the coulomb scattering, and the

4

Fig. 1.5 C–V characteristics of MOS capacitors with La-silicate gate dielectrics. The samples were annealed for 2 s in forming gas ambient at 500 ◦C. surface potential changes to result in additional capacitance component.. Fig. 1.5 shows the C-V characteristics of MOS capacitors with La-silicate gate dielectrics. Humps accompanying large frequency dispersion in C – V characteristics appear at an annealing temperature of 500 ◦C, as shown in fig. 1.5. It is reported that these humps are found to decrease with increasing annealing temperature, and the frequency dispersion disappears at an annealing temperature of 800 ◦C [1.4].

0.0E+00

5.0E-01

1.0E+00

1.5E+00

2.0E+00

-1.5 -1.0 -0.5 0.0 0.5

2

1.5

1.0

0.5

0

Cap

acita

nce

(µF/

cm2 )

-1.5 -1.0 -0.5 0 0.5

1kHz10kHz100kHz1MHz

20 x 20 µm2

0.0E+00

5.0E-01

1.0E+00

1.5E+00

2.0E+00

-1.5 -1.0 -0.5 0.0 0.5

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1.0

0.5

0

Cap

acita

nce

(µF/

cm2 )

-1.5 -1.0 -0.5 0 0.50.0E+00

5.0E-01

1.0E+00

1.5E+00

2.0E+00

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1.5

1.0

0.5

0

Cap

acita

nce

(µF/

cm2 )

0.0E+00

5.0E-01

1.0E+00

1.5E+00

2.0E+00

-1.5 -1.0 -0.5 0.0 0.50.0E+00

5.0E-01

1.0E+00

1.5E+00

2.0E+00

-1.5 -1.0 -0.5 0.0 0.5

2

1.5

1.0

0.5

0

Cap

acita

nce

(µF/

cm2 )

-1.5 -1.0 -0.5-1.5 -1.0 -0.5 0 0.5

1kHz10kHz100kHz1MHz

20 x 20 µm2

5

Fig. 1.6 Equivalent parallel conductance over angular frequency (GP/ω) versus

frequency plots. Solid and open dots indicate the experimental data obtained for La2O3 gate dielectric and SiO2 gate dielectric, respectively.

In fig.1.6, Gp/ω spectrum of La2O3/Si structure and SiO2/Si structure is measured

by conductance method. From the local maximum of each curve, the magnitude of interface state density (Dit) can be estimated. The spectrum has two distinct peaks in fig.1.6. One of the peaks is observed in the high frequency region. Another peak is observed in low frequency region. The former one, which is considered to be caused by the interface trap, is observed in both spectrums of SiO2 layer and La2O3 layer. The latter one is observed only in the case of La2O3, and its magnitude at the peak is much larger than the former one. The peak in low frequency region is not still interpreted clearly. It is discussed that oxide trap contributes to the peak. Oxide traps are located inside the oxide layer. Oxide traps cause the change in gate voltage. The mobility decreases and reliability

is low due to the scattering at oxide trap. However, oxide properties are still not clear. Thus, it is important to examine the interface state and the oxide traps in detail.

101 102 103 104 105 106 107

2.5

2

1.5

0.5

1

0

3 5

4

3

2

1

0

Frequency (Hz)

Gp

/ω(F

/cm

2 )系列2系列1

(x 10-9)(x 10-6)

SiO2

La2O3

E-Ei = 0.12 eVVamp = 100 mV

6

1.4 Purpose of this study The purpose of this study is to form ideal La-silicate layer which has low density of interface state and oxide trap, and to clarify its dependence on annealing temperature. Then, we will provide forideal La-silicate from the view points of electrical and physical characteristics. Chapter 1 summarizes the background and the purpose of this study. Chapter 2

explains the electrical measurement and physical analysis. In chapter 3, the electrical analysis of interface and oxide trap is reported. In chapter 4, fourier transform infrared (FTIR) spectra and x-ray photoelectron spectroscopy (XPS) analysis of La-silicate layer are observed. Chapter 5 summarizes this study. 1.5 Conclution In this chapter, we stated that the background about high-k dielectrics, issues of interface states and oxide states, and purpose of this study. It is important to evaluate La-silicate dielectric gates from the point of electrical and physical view. In this study, we provide the physical image of formation of La-silicate layer structure for gate dielectric applications.

References [1.1] ITRS, “INTERNATIONAL TECHNOLOGY ROADMAP FOR

SEMICONDUCTORS 2011 EDITION FRONT END PROCESSES”, http://www.itrs.net/Links/2011ITRS/2011Chapters/2011FEP.pdf [1.2] K. Kakushima et al.: “Further EOT Scaling below 0.4 nm for High-k Gated

MOSFET”, IWDTF (2008). [1.3] Y.Taur, T.H. Ning: ”Fundamentals of MODERN VLSI DEVICES”, p.99-102,

Cambridge University Press (1998).

[1.4] T. Kawanago, Y. Lee, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N.

Sugii, K. Natori, T. Hattori, and H. Iwai.: “EOT of 0.62 nm and High Electron

Mobility in La-silicate /Si Structure Based nMOSFETs Achieved by Utilizing

Metal-Inserted Poly-Si Stacks and Annealing at High Temperature”, IEEE

TRANSACTIONS ON ELECTRON DEVICES Vol.59 Issue:2 pp. 269 – 276

7

Chapter 2. Experimental procedures and experimental details

2.1 Experimental procedures

Figure 2.1 shows the fabrication flow of capacitor. MOS capacitors were

fabricated on n-type Si (100) substrates. A 4-nm-thick La2O3 layer were deposited

by molecular beam epitaxy followed by in situ deposition of 6-nm-thick W layer by

magnetron sputtering thereby avoiding any moisture or carbon-related contamination

on La2O3 layer. A 45-nm-thick TiN layer is subsequently deposited by RF magnetron

sputtering. The gate electrodes consisting of W and TiN were patterned by

reactive-ion etching (RIE) with SF6 chemistry and photolithography. Post

metallization annealing (PMA) is performed in forming gas (N2 :H2 =97 : 3) ambient

at 400, 500, and 600 oC, respectively. In this study, the properties of samples treated

under the different annealing conditions, such as annealing time (2 s or 30 min), and

at different annealing temperature are examined. Finally, 50-nm-thick Al contact

layer on backside of substrates were deposited by evaporation in vacuum.

8

Fig. 2.1 Fabrication procedure of MOS capacitor.

Next, the fabrication procedure of samples for FTIR study are explained. In fig.2.2

shows the fabrication procedure of samples for FTIR study. A 5-nm-thick La2O3

layer were deposited by MBE followed by in situ deposition of 10-nm-thick Ge layer

by magnetron sputtering. PMA is performed in F.G. ambient. These samples were

subjected to RTA under different annealing temperatures (from 200 to 800 oC) for 2 s

or 30 min.

Gate electrode and resist etching by RIE

PMA in F.G. for 30min

Al deposition by vacuum evaporation method

Measurement

SiO2SiO2

TiN

W

Si-substrate

La2O3

RadicalCation

SiO2SiO2

TiN

W

Si-substrate

La2O3

Si Si SiSi

H2

N2

SiO2SiO2

TiN

W

Si-substrate

La2O3

SiO2SiO2

TiN

W

Si-substrate

La2O3

Si Si SiSiHH H

SiO2SiO2

TiN

W

Si-substrate

La2O3

Al

SPM cleaning and HF treatment

n-Si (100) substrate

La2O3 (4 nm) deposition by MBE

W (5 nm) deposition and TiN(45 nm)by RF magnetron sputtering

SiO2SiO2

Si-substrate

La2O3

SiO2SiO2

W

Si-substrate

La2O3 SiO2SiO2

TiN

W

Si-substrate

La2O3

Photo lithography

SiO2SiO2

TiN

W

Si-substrate

La2O3

Particle Metal ionParticle Metal ion

H2O2+ H2SO4 = (1:4)

SiO2

Si-substrate

SiO2 SiO2SiO2

Si-substrate

SiO2SiO2

Si-substrate

SiO2 SiO2

1%HF

SiO2

Si-substrate

SiO2 SiO2SiO2

Si-substrate

SiO2 SiO2

Chemical OxideChemical Oxide

9

Fig. 2.2 Fabrication procedure of FTIR samples. 2.1.1 Wafer cleaning

First of all, it is important to clean the surface of Si-substrate because particles and metal ions in fabrication processes affect the performance, reliability, and yield of the devices [2.1]. Treatment in mixed solution of sulfuric acid and hydrogen peroxide (H2O2:H2SO4 = 1:4) (SPM) and treatment in hydrofluoric acid (HF) give the effective cleaning procedures. Figure 2.3 illustrates SPM cleaning and HF treatment. SPM cleaning remove particles and metal ions thereby cleaning the surface of Si-substrate. Partices and metal ions are taken in chemical oxide formed during SPM cleaning. Thus, 1% HF is used to etch the chemical oxide. By this cleaning procedure the surface of Si substrate is cleaned and not affected by contamination.

SPM cleaning and HF treatment

n-Si (100) substrate

La2O3 (5nm) deposition by MBE

Ge (10nm) depositionby RF magnetron sputtering

PMA in F.G. at 200~800oC for 2s-30min

Measurement

Si-substrate

La2O3

Ge

Si-substrate

La2O3

Si-substrate

Particle Metal ion

Si-substrate

Particle Metal ion

H2O2+H2SO4(1:4)

1%HF

Si-substrate


10

Fig. 2.3 Schematic illustration of SPM cleaning and HF treatment.

2.1.2 Deposition of La2O3 dielectric by MBE

Molecular beam epitaxy is one of the vacuum evapotration methods. Figure 2.4 shows schematic illustration of MBE [2.2]. Since ultra high vacuum (~10-6 Pa) is created inside of the chamber, the source molecule is not scattered by residual molecules. E-beam emitted from hot-filament is accelerated, and bended by magnetic field and then it hits on the source material. As a result source material is heated to result in the evaporation of the source material onto the Si substrate.

Substrate

Molecularbeam

Source

ultra high vacuum (~10-6 Pa) Substrate heater

Shutter

E-beam

Fig. 2.4 Schematic illustration of MBE.

2.1.3 RF magnetron sputtering

Gate electrodes in this study were deposited by radio frequency (RF) magnetron sputtering. Figure 2.5 shows schematic illustration of RF magnetron sputtering. The

Particle Metal ionParticle Metal ion

H2O2+ H2SO4 = (1:4)

Si-substrate

SiO2SiO2 SiO2

Si-substrate

SiO2SiO2 SiO2

1%HF

SiO2

Si-substrate

SiO2 SiO2SiO2

Si-substrate

SiO2 SiO2


SiO2

Si-substrate

SiO2 SiO2SiO2

Si-substrate

SiO2SiO2

Si-substrate

SiO2 SiO2

Field oxide

11

high voltage is applied between a substrate and a target. A magnet is set under the target to prevent plasma damage. Then, Ar gas is supplied into the chamber to produce plasma chamber to be ionized. Ar ions hit the target atoms to be deposited on the substrate. The advantage of this method is that better adhesion between suppered atoms and substrate.

Fig. 2.5 Schematic illustration of RF magnetron sputtering.

2.1.4 Patterning of resist by photo lithography Resist-patterning is the method to eliminate needless parts of metal to obtain the gate electrode. In order to measure infrared absorption on the surface and in the oxide the gate metal is not deposited on the samples used for FTIR study.

First, the gate electrode is covered with positive resist, a part of which exposed to light is removed by the solvent. In order to make thickness of the resist uniform, Si-substrates covered with resist are revolved using spinner. After the resist on the substrates are heated (“Pre-bake”)., the position of substrates are adjusted with respct to photo mask for patterning of resist. Then, they are soaked into the developer, and the resist covered with the mask is remained. Finally, they are heated to fix the resist(“Post-bake”).

Substrate

Ar+

Targetmaterial

Plasma

Atom oftarget material

Substrate

Ar+

Targetmaterial

Plasma

Atom oftarget material

12

Fig. 2.6 Schematic illustration of photolithography. 2.1.5 Dry etching by RIE

Reactive ion etching (RIE) is one of the methods to etch for patterning. Figures 2.7 and 2.8 show schematic illustrations. Etching gases used for etching metal electrodes of W and TiN are SF6 and O2, respectively . In SF6 plasma W reacts with F- to form WF6, which is in gas phase at room temperature, followed by the ashing process, that is, the elimination of resist in O2 plasma. These RIEs use both physical and chemical reaction. Physical reaction is ascribed to electric field enhanced collision of cations with the substrate. Vertically incident cations has a advantage to enhance anisotropic etching. Chemical reaction is caused by radicals absorbed on the substrate, and the compounds are sublimated from the substrate.

Si-substrate

SiO2 SiO2

Si-substrate

SiO2 SiO2

Gate Dielectric

Gate Electrode

Mask

Resist

Si-substrate

SiO2 SiO2

Si-substrate

SiO2 SiO2

After soaking into developper

Mask

13

Fig. 2.7 Schematic illustration of RIE.

Fig. 2.8 Schematic illustration of etching and ashing.

2.1.6 Post metallization annealing in F.G. ambient

Post metallization annealing (PMA) is important to improve the performance of devices, as shown in fig. 2.9. After evacuation the chanber is filled with the forming gas (F. G. ) (N2:H2 = 97:3) for annealing. One of the main purposes of PMA is to terminate the dangling bonds with hydrogen at the La2O3 dielectrics/Si interface.

Si-substrate

SiO2 SiO2

RadicalO2

Si-substrate

SiO2 SiO2

Si-substrate

SiO2 SiO2

RadicalO2

Si-substrate

SiO2 SiO2

Si-substrate

SiO2 SiO2

Si-substrate

SiO2 SiO2

Si-substrate

SiO2 SiO2

Si-substrate

SiO2 SiO2

Gate DielectricGate Electrode

SF6

RadicalCation RadicalCation

Si-Substrate

Plasma(SF6 or O2)

Vacuumpomp

14

SiO2SiO2

TiN

W

Si-substrate

La2O3

Si Si SiSiHH HSiO2SiO2

TiN

W

Si-substrate

La2O3

Si Si SiSi

H

N

Fig. 2.9 Schematic illustration of forming gas annealing (FGA).

2.1.7 Deposition of Al by vacuum evaporation

Vacuum evaporation is performed to deposit Al, as shown in the fig. 2.10. First, Al is set on the W boat followed by Joule heating of W. By heating Al up to its melting point, which is smaller than that of W, as a result of large current flow through W boat, Al is vaporized and deposited on the substrate.

Fig. 2.10 Schematic illustration of vacuum evaporation

2.2 Electrical measurement and physical analysis

2.2.1 Estimation of interface state density by Conductance method In this study, conductance method is used to evaluate interface state density (Dit). In

the conductance method, the equivalent circuit of MOS capacitor is used. AC voltage is applied to the device, and the frequency of that changes, and Dit can be measured.

Fig.2.11 (a) shows an equivalent circuit model of MOS capacitor [2.3], where Cox is the oxide thickness per unit area, Cs is the silicon substrate capacitance per unit area,

Back side of substrate

W boat

Heated Aluminium

15

Fig. 2.11 Equivalent circuits of MOS capacitor; (a) an equivalent circuit model of the

MOS capacitor, (b) an equivalent parallel circuit, (c) the measured circuit. The circuit of (a) can be simplified to (b).

Rit and Cit are the resistance and capacitance components per unit area related to

interface trap, and Gt is tunnel conductance per unit area related to leakage current. And then, the equivalent circuit converts to the equivalent parallel circuit. Fig. 2.12(b) shows the equivalent parallel circuit, where Cp and Gp are the equivalent parallel capacitance and conductance per unit area, respectively. Cp and Gp are given by

( )21 it

itsp

qDCC

ωτ++= , (2.1)

( )21 it

ititp DqGωτ

ωτω +

= , (2.2)

where Cit = qDit, and τit = CitRit. Dit is interface state density and τit is interface trap time constant here. These equations estimate that interface trap is single energy level, but interface traps actually are continuously distributed. Therefore, these two equations are rewritten as [2.4]

( )itit

itsp

qDCC ωτωτ

1tan −+= , (2.3)

( )[ ]21ln2 it

it

itp qDGωτ

ωτω+= , (2.4)

These two equations are for interface traps considered the continuum level. However, there is serious error between continuum level and measurement data. We

Gp

Gt

Cox

Cp Gp

Gt

Cox

Cp Ｃm GmRit

Gt

Cox

CsCit

(a) (b) (c)

Gp

Gt

Cox

Cp Gp

Gt

Cox

Cp Ｃm GmRit

Gt

Cox

CsCit

Gp

Gt

Cox

Cp Gp

Gt

Cox

Cp Ｃm GmRit

Gt

Cox

CsCit

(a) (b) (c)

16

also have to consider the effect of surface potential fluctuations. This is generated by inhomogeneities in oxide charge and interface charge. Therefore, we assume surface

potential fluctuations follow normal distribution, where ψs is surface potential, Sψ

and σ are mean and standard variation of the surface potential, respectively. When τ becomes larger, the peak value becomes lower, and width of the curves becomes broader.

( )[ ] ( )⎮⌡⌠ +=

∞

∞−SSit

it

itp dPDqGψψωτ

ωτω21ln

2, (2.5)

( ) ( )⎟⎟

⎠

⎞

⎜⎜

⎝

⎛ −−= 2

2

2 2exp

21

σψψ

πσψ SS

SP , (2.6)

Then, we consider the measurement equation. Fig.2.11 (b) must be converted to

the fig. 2.11(c). Compared with the Eq. (2.5), Gp/ω of fig.2.11 (c) is given by

( )( ) ( )222

2

mOXtm

OXtmp

CCGGCGGG

−+−−

=ω

ωω

. (2.7)

The measurement data can be obtained from Eq. (2.7), where the capacitance and conductance are Cm and Gm ,respectively.

2.2.2 Fourier transform infrared spectroscopy (FTIR) Fourier transform infrared spectroscopy (FTIR) is one of the optical spectroscopy.

This method gives information concerning molecules structure bonding configuration. Spectra are obtained which are dependent on particular bonds, but chemical elements cannot be determined by this method. Compounds and crystals have their own intrinsic vibration to absorb and resonate. The transverse axis means wave number, which is more important than vertical axis. Qualitative analysis is made by comparing spectrum with the reference library which is known of till now. The vertical axis is the absorption of infrared rays. It is proportional to the density of substrate and the thickness. In this study, we measure the infrared spectrum by fourier transform infrared

attenuated total reflectance (FTIR-ATR). The measurement method uses total reflection phenomenon. When infrared light enters from crystal prism with a higher

17

reflective index to a sample with a lower reflective index, total reflection occurs. The light penetrates a little from the surface of prism crystal to the sample. Fig.2.12 shows the schematic illustration of total reflection. Infrared light enters from a Germanium (Ge) prism with high reflective index to a sample with low reflective index, where incident angle θ is higher than critical angle. The light penetrates into the sample slightly at the reflection interface. This light is called evanescent wave. Evanescent wave has the characteristics that light intensity exponentially decreases with penetrating depth. In fig.2.12, Dp is the depth from interface and given by

2

1

22 )(sin21 n

nnDp

−=

θπ

λ (2.10)

where λ is wave number, θ is incident angle, n1 is Ge prism reflective index, n2 is sample reflective index. (n1 > n2 where n1 and n2 are higher and lower refractive index) [2.5]. In this study, Dp is shown in fig.2.13.

Fig. 2.12 Schematic illustration of FTIR-ATR principle.

n2

n1

θ

Ge Prism

Sample

Dp

Infrared light

Evanescent wave

18

Fig. 2.13 Penetrating depth versus wavenumber.

The measurement procedure is discussed below. Before sample measurements

absorption, background absorption is measured when sample is not put on the Ge prism. The sample is set on the Ge prism, and sample spectrum measured. The sample spectrum divided by background spectrum gives a transmittance. The transmittance T is given by

oIIT = , (2.8)

where I0 is the intensity of the incident beam, and I is the intensity of the light transmitted. The absorbance is given by

oIIAbsorbance log−=

Tlog−= (2.9) The spectra were taken at room temperature in the 700 – 3000 cm-1 under a dry nitrogen ambient with a resolution of 8 cm-1 in this study.

2.2.3 X-ray photoelectron spectroscopy (XPS)

X-ray photoelectron Spectroscopy (XPS) is one of the spectroscopic technique, which can measures elements. It concerns itself with the energy spectrum of electrons emitted from atoms of the material being studied. It uses high energy x-ray as exciting light to excite a core electron which strongly bound to an atom, and to emit photoelectron. By irradiating x-ray to the thin sample, the electrons obtain the

0.E+00

1.E-07

2.E-07

3.E-07

4.E-07

5.E-07

6.E-07

7.E-07

8.E-07

700.01200.01700.02200.02700.0

0.8

0.6

0.4

0.2

0.02700 2200 1700 1200 7003000

wavenumber (cm-1)

Pene

trat

ing

dept

h (µ

m)

0.E+00

1.E-07

2.E-07

3.E-07

4.E-07

5.E-07

6.E-07

7.E-07

8.E-07

700.01200.01700.02200.02700.00.E+00

1.E-07

2.E-07

3.E-07

4.E-07

5.E-07

6.E-07

7.E-07

8.E-07

700.01200.01700.02200.02700.0

0.8

0.6

0.4

0.2

0.0

0.8

0.6

0.4

0.2

0.02700 2200 1700 1200 7003000 2700 2200 1700 1200 7003000

wavenumber (cm-1)

Pene

trat

ing

dept

h (µ

m)

19

energy from the x-ray so that it is emitted with the kinetic energy. The relation of the energies can be expressed: hν = Ek + Eb, (2.11) where hν is the energy of the x-ray, Ek is the kinetic energy of the emitted electron and Eb is the binding energy of the emitted electron. Fig.2.14 shows the schematic illustration of the principle of XPS. The Eb can be dededuced, by measuring Ek, because the value of hν is constant. Each element has peculiar Eb, so that the information what atom is caused can be known after core electron binding energy is analyzed [2.6]. In fig. 2.15, the photoelectron is emitted from the sample if the energy of incident photon is high enough. It is affected by the applied voltage, and the orbit of that is curved. A detector sensor measures the binding energy [2.7].The relative number of each electron is determined by the incident energy.

Fig. 2.14 The schematic illustration of the principle of XPS.

Energy(eV)

X-ray

Kinetic energy

Binding energy

Vacuum energy

20

Fig. 2.15 Schematic illustration of XPS. X-ray beam strikes the sample, and photoelectron is emitted, and detector sensor measures the binding energy.

2.3 Conclusion

In this chapter, we explained the experimental procedure, and the principle of

measurement (Conductance method, FTIR, XPS). The sample was produced at this

laboratory.

References [2.1] T. Ohmi: “Advanced electronics I-15 Ultraclean ULSI gizyutu”, pp.157-158,

baifukan (1995). [2.2] T. Watanabe: “Denshisen jochaku・teikou kanetu jochaku sochi”, http://www.msl.titech.ac.jp/~hosono/facilities/EBeamEvaporator.html [2.3] Dieter K. Schroder: “Semiconductor Material and Device Characterization 3rd

Edition”, pp.347-350, Wiley Interscience, New York (2006). [2.4] Nicollian & Brews: “MOS Physics and Technology”, Wiley Interscience,

United States of America, p.200 (2003).

sample

X ｒａｙｂｅａｍ

photoelectron

detector sensor

slit θ

21

[2.5] Y. Furukawa, M.Takayanagi and K.Hasegawa : “Sekigai・Raman bunnkouhou”,

The Spectroscopical Society of Japan, pp.1-2,pp. 49-52 (2009).

[2.6] W. R. Runyan: “Semiconductor Measurements and Instrumentation”,

McGRAW-HILL KOGAKUSHA, LTD (1975).

[2.7] K. Ushida , J.Kawai et.al : “ Xsen・Housyakou no bunnkou” , The

Spectroscopical Society of Japan, pp.69-74 (2009).

22

Chapter 3. Electrical characteristics of La-silicate gate dielectrics 3.1 Dependence of interface state density on annealing time

As written in chapter1.3, the measured conductance curve shows only a single

broad peak in the case of SiO2 dielectrics. On the other hand, in the case of La2O3

gate oxide, the curve shows two distinct peak; one at the low frequency region and

the other one at the high frequency region. The first peak in the low frequency region

suggests the presence of slow traps with a longer trap capture and emission time

constants [3.1]. We call the trap which relates to low frequency region “slow trap”in

this paper. The second peak in the high frequency region indicates the presence of

fast traps with a shorter trap capture and emittion time constants.

23

Fig. 3.1 Conductance spectrum of a TiN / W / La2O3 /n-Si MOS capacitor

annealed at 500 oC for 2 s and 30 min.

Fig. 3.1 shows Gp/ω versus angular frequency for 2 s or 30 min annealing. In this

figure, two distinct peaks are observed at the low frequency and high frequency

regions.

The conductance spectra in the high frequency region can follow a normal

distribution. Therefore, the peaks in the high frequency region are given by Eq. (2.5),

(2.6). They result from interface traps.

On the other hand, the peaks in the low frequency region can follow a single

energy level. Thus, the conductance spectrum of slow trap Gp,slow/ω can be expressed

by Eq (2.2), where τit and Dit are replaced with slow trap time constant τslow and slow

trap state density Dslow ,respectively.

We can see the peaks of curves in low frequency region shifts the left hand as

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Gp/ω

(F/c

m2 )

0.0

0.5

1.0

2.0

2.5

(×10-6)3.0

102 103 104 105 106 107

ω (rad/s)

1.5

measurement Interface trap with normal distribution modelSlow trap with single energy model

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Gp/ω

(F/c

m2 )

0.0

0.5

1.0

2.0

2.5

(×10-6)3.0

102 103 104 105 106 107

ω (rad/s)

1.5

measurement Interface trap with normal distribution modelSlow trap with single energy model

2 s

30 min

24

annealing time is longer. Also, the longer annealing time becomes, the smaller local

maximum becomes.

Fig. 3.2 Energy distribution of the trap time constants τslow of TiN / W / La2O3 /n-Si

MOS capacitor annealed at 500 oC for 2 s and 30 min within the bandgap of Si. .

Fig. 3.2 shows the trap capture and emission time constant versus energy level.

Midgap in silicon band gap means E-Ei = 0. The time constant of sample annealed

for 30 min is longer than that of sample annealed for 2 s. When the time constant is

long, electrons can travel far. Thus, electrons are captured at far trap from the

conduction band.

1.00E-04

1.00E-03

1.00E-02

1.00E-01

-0.1 0 0.1 0.2 0.3 0.4 0.5 0.6

Cap

ture

and

em

mis

ion

time

cons

tant

of D

slow

(s)

E-Ei(eV)

10-3

10-4

10-2

0 0.2 0.3 0.4 0.5 0.6－0.1

10-1

0.1

2 s

30 min

25

Fig. 3.3 Schematic illustration of La-siliacte layer increases with increase in

annealing time or annealing temperature

Let us suppose that the origin of low trap can be located at the interface of La2O3

and La-silicate layer. In fig. 3.3, La-silicate layer grows as annealing time is longer.

From this figure, we can explain the reason why the time constants of slow traps

become longer with increase in annealing time. On the other hand, we can conclude

that the fast traps peaking at a high frequency region can be assigned as the Dit

located at the interface between La-silicate and Si substrate.

La2O3

Si-substrate

La-Silicate

WTiN(a) 2 s (b) 30 min

Si-substrate

WTiN

26

Fig. 3.4 Energy distribution of the D slow and Dit within the bandgap of Si for

TiN/W/La2O3/n-Si MOS capacitor annealed at 500 oC for 2 s .

Fig. 3.4 shows the Dslow and Dit of TiN/La2O3/n-Si capacitors annealed at 500oC for 2

s versus energy distribution. In fig.3.4 we can see that the increasing trend of Dit

distribution toward conductance band within the bandgap of Si-substrate.

We suggest that slow trap is located at the interface of La2O3 and La-silicate layer.

The result that the amount of Dslow is constant regardless of change in surface

potential means the slow traps should be distributed at a far distance from

Si-substrate. It is indicated that the amount of slow traps is almost same the digit

unlike the interface trap because it is not affected by surface potential. On the other

hand, interface traps are reduced with change of surface potential.

1.E+10

1.E+11

1.E+12

1.E+13

1.E+14

0 0.1 0.2 0.3 0.4

1014

0 0.1 0.2 0.3 0.4

Dsl

owD

it(e

V-1cm

-2) 1013

1012

1011

1010

E-Ei(eV)

Dslow

Dit

@500oC,2 s

1.E+10

1.E+11

1.E+12

1.E+13

1.E+14

0 0.1 0.2 0.3 0.4

1.E+10

1.E+11

1.E+12

1.E+13

1.E+14

0 0.1 0.2 0.3 0.4

1014

0 0.1 0.2 0.3 0.4

Dsl

owD

it(e

V-1cm

-2) 1013

1012

1011

1010

E-Ei(eV)

Dslow

Dit

@500oC,2 s

27

3.2 Dependence of interface state density on annealing temperature

0.0E+00

5.0E-07

1.0E-06

1.5E-06

2.0E-06

2.5E-06

3.0E-06

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Gp/ω

(F/c

m2 )

0.0

0.5

1.0

2.0

2.5

(×10-6)3.0

ω (rad/s)

1.5

10 103 104 105 106 107102

400℃

500℃

600℃

measurement

Interface trap with

normal distributionSlow trap with

single energy

Vg =Vfb annealed for 2 s

Fig. 3.5 Conductance spectrum of a TiN/W/La2O3/n-Si MOS capacitors annealed at

400, 500 and 600 oC for 2 s.

Fig. 3.5 shows Equivalent parallel conductance over angular freaquency (Gp/ω).

Annealing time is 2 s, and temperature is 400, 500, and 600oC. Peaks of curves in

low frequency region shift the left hand as annealing temperature increases. In this

figure, we see that as the curve of higher annealing temperature becomes the smaller

local maximum. This means the trap decreases when the annealing temperature is

getting to be higher.

28

Fig. 3.6 Slow trap capture and emission time constants versus energy distribution.

Trap time is longer as annealing temperature is increasing.

Fig 3.6 shows the slow trap capture and emission time constant versus energy level.

We see that time constant of slow trap is longer as the temperature becomes higher.

This means that slow trap should be located at a distance from surface of Si substrate

with increase in annealing temperature.

La2O3 reacts with Si substrate, and La-Silicate is formed by interfacial reaction. The

thickness of the La-silicate layer depends on the annealing temperature and time.

Thickness of the interfacial La-Silicate layer grows thicker with increase in annealing

temperature. The longer time constants result from growing of La-silicate layer. Thus,

we suggest that the origin of slow trap can be located at the interface of La2O3 and

La-silicate layer.

Cap

ture

and

Em

mis

ion

Tim

e C

onst

ant (

s)

E-Ei (eV)

(×10-3)

0

0.001

0.002

0.003

0 0 0 0 0 0 0 00.0 0.1 0.2 0.3

1.0

2.0

3.0C

aptu

re a

nd E

mm

isio

n

Tim

e C

onst

ant (

s)

E-Ei (eV)

(×10-3)

0

0.001

0.002

0.003

0 0 0 0 0 0 0 0

0

0.001

0.002

0.003

0 0 0 0 0 0 0 00.0 0.1 0.2 0.3

1.0

2.0

3.0

600oC

500oC

400oCCap

ture

and

emis

sion

tim

e co

nsta

nts

of D

slow

(mse

c)C

aptu

re a

nd E

mm

isio

n

Tim

e C

onst

ant (

s)

E-Ei (eV)

(×10-3)

0

0.001

0.002

0.003

0 0 0 0 0 0 0 00.0 0.1 0.2 0.3

1.0

2.0

3.0C

aptu

re a

nd E

mm

isio

n

Tim

e C

onst

ant (

s)

E-Ei (eV)

(×10-3)

0

0.001

0.002

0.003

0 0 0 0 0 0 0 0

0

0.001

0.002

0.003

0 0 0 0 0 0 0 00.0 0.1 0.2 0.3

1.0

2.0

3.0

600oC

500oC

400oCCap

ture

and

emis

sion

tim

e co

nsta

nts

of D

slow

(mse

c)

29

Fig. 3.7 The dependence of Dslow on energy for a TiN / W / La2O3 /n-Si

MOS capacitor annealed for 2 s at 400, 500, and 600 oC.

Fig. 3.7 shows Dslow of each annealing temperature. In this figure, we see that the

density of slow trap decreases as the annealing temperature increases within the

extent of energy we measured. We would like to note that annealing temperature is

higher and the slow trap decreases. A detailed analysis is necessary for future works.

0.0E+00

1.0E+13

2.0E+13

3.0E+13

4.0E+13

0 0.1 0.2 0.3 0.4

Dot

(eV-1

cm-2

)

E-Ei(eV)

0.0 0.1 0.2 0.3 0.4

(×1013)

0.0

2.0

1.0

3.0

4.0

600oC

500oC

400oCD

slow

(eV-

1 cm

-2)

30

Ec

Ev

Eｆ

La-SilicateLa2O3Metal Si-substrate

Fast-state DitOxide trap

Slow state Dslow

Thickness increase with increase

in annealing temperature

Fig. 3.8 Band diagram of La2O3 /La-silicate/n-Si capacitors. The

La-silicate layer is increasing .

In fig. 3.8, band diagram of La2O3/La-silicate/n-Si capacitors is shown. The

La-silicate thickness is given by

)exp(0 kTE

Ct asilicate −= (3.2)

where C0 is concentration of radical oxide atoms at the interface of La2O3/La-silicate,

and Ea is an activation energy, and k and T are the Boltzmann’s constant and absolute

temperature [3.1]. Thus, the thickness of the silicate layer is increasing with

annealing temperature.

We can conclude that slow traps are located at the interface between La-silicate

31

and La2O3. It is indicated that the dielectric layer without interface between

La-silicate and La2O3 is ideal for decreasing Dslow. Thus , the layer which does not

exist the interface between La2O3 and La-silicate is desirable. To produce ideal layer,

the whole of the layer should be composed of La-silicate.

Then, we need to consider decrease of interface trap. Fig. 3.9 shows capacitance

versus gate voltage characteristics of W(8 nm)/La2O3(4 nm)/n-Si. The hump is

observed at inversion and depletion region. It has a relation to interface trap. A higher

annealing temperature can prevent the hump from causing frequency dispersion.

-0.5 0 0.5

1 MHz100 kHz10 kHzIdeal

2.5

2.0

1.5

1.0

0.5

0-1.0

700oC

Gate voltage [V]

Cap

acita

nce

[µF/

cm2 ]

-0.5 0 0.5


2.5

2.0

1.5

1.0

0.5

0-1.0

700oC1 MHz100 kHz10 kHzIdeal

2.5

2.0

1.5

1.0

0.5

0-1.0

700oC

Gate voltage [V]

Cap

acita

nce

[µF/

cm2 ]

0.5


2.0

1.5

1.0

0.5

0-1.0 -0.5 0

800oC2.5

Gate voltage [V]0.5


2.0

1.5

1.0

0.5

0-1.0 -0.5 0

800oC2.5


2.0

1.5

1.0

0.5

0-1.0 -0.5 0

800oC2.5

Gate voltage [V]


0.5

2.5

2.0

1.5

1.0

0.5

0-1.0 -0.5 0


0.5

2.5

2.0

1.5

1.0

0.5

0-1.0 -0.5 0

900oC

Gate voltage [V]

Cap

acita

nce

[µF/

cm2 ]

-0.5 0 0.5


2.5

2.0

1.5

1.0

0.5

0-1.0

700oC

Gate voltage [V]

Cap

acita

nce

[µF/

cm2 ]

-0.5 0 0.5


2.5

2.0

1.5

1.0

0.5

0-1.0


2.5

2.0

1.5

1.0

0.5

0-1.0

700oC

Gate voltage [V]

Cap

acita

nce

[µF/

cm2 ]

0.5


2.0

1.5

1.0

0.5

0-1.0 -0.5 0

800oC2.5

Gate voltage [V]0.5


2.0

1.5

1.0

0.5

0-1.0 -0.5 0

800oC2.5


2.0

1.5

1.0

0.5

0-1.0 -0.5 0

800oC2.5

Gate voltage [V]


0.5

2.5

2.0

1.5

1.0

0.5

0-1.0 -0.5 0


0.5

2.5

2.0

1.5

1.0

0.5

0-1.0 -0.5 0

900oC

Gate voltage [V]

Cap

acita

nce

[µF/

cm2 ]

(a) (b)

(c)

32

Fig.3.9 C-V characteristics of W/La2O3/n-Si (a) annealed at 700oC, (b)800oC,

(c)900oC. Frequency dispersion is preventerd.

Fig. 3.10 Dit versus annealing temperature of W(8 nm)/La2O3(4 nm)/n-Si.

Fig 3.10 shows the interface state density versus annealing temperature measured

by W(8 nm)/La2O3(4 nm)/n-Si structure. Dit decreases with higher annealing

temperature. I would like to note that Dit decreases greatly when annealing

temperature is over 700 oC. The decrease in Dit with annealing temperature over 700

oC can result from the reaction at interface of La-silicate and n-Si substrate. It can be

considered that relaxation of strain between La-silicate and Si-substrate occurs, and

interface state density decreases. This will be discussed in detail in next chapter.

3.3 Conclusion

In this chapter, conductance spectrum of La-silicate are examined by conductance

600As-depo 800400 1000 Annealing temperature(oC)

Dit

(cm

-2/e

V)

1014

1013

1012

1011

200 600As-depo 800400 1000 Annealing temperature(oC)

Dit

(cm

-2/e

V)

1014

1013

1012

1011

200

33

method. In consequence, the peaks of Gp/ω peak in low frequency region can arise

from slow trap located at interface between La2O3 and La-silicate, because the peak

is related to increase in La-silicate thickness. Moreover, a high temperature annealing

can lead to decrease in interface state density.

References [3.1] M. Mamatrishat, et al.: “ Oxide and interface trap densities estimation in ultrathin W/La2O3/Si MOS capacitors” Microelectronics Reliability (2012).

34

Chapter 4. Characterization of La-silicate gate dielectrics by FTIR and XPS

4.1 FTIR spectrum of La-silicate gate dielectrics

Fig. 4.1 shows the schematic illustration of the depth of evanescent wave from the

surface in this study. The depth is measured over about 510 nm at 1000cm-1, thus the

absorbance of La2O3 and La-silicate layer can be observed.

Si-substrate

La2O3

Ge

La-silicate

Infraredrays

5 nm

Fig. 4.1 Schematic illustration of the depth of evanescent wave from the surface in

this study sample.

The spectral result at 700-1400cm-1 of Ge (10 nm)/La2O3(5 nm)/n-Si samples

annealed at 800 oC , 500 oC and as-deposit are shown in fig. 4.2. The spectrum were

taken at room temperature in the 700 – 1400 cm-1 under a dry nitrogen ambient at a 8

cm-1 resolution.

35

Note that in fig 4.2, there are three features at 1250 cm-1, 1050 cm-1 and 900cm-1

observed. First dominant feature at 1250 cm-1 is the longitudinal optical (LO) mode

arising from asymmetric Si-O-Si stretching motions of the constituent SiO4

tetrahedra [4.1,4.2]. LO mode has information involved in strain at the surface of

Si-substrate. Second absorbance arising from La-silicate layer can be observed

around 1050-1100 cm-1. Third spectral feature at 900cm-1 is indicated Ge-O

stretching mode [4.3]. It is reported that the absorbance arising from La-O bonds

appears around 450-540 cm-1[4.4], but we cannot observe La-O bonds within the

range of wavenumbers measured in this study. Table1 shows the wavenumbers of

each bonds vibration.

Wavenumber(cm-1)

0

0.5

1

1.5

2

2.5

3

3.5

4

70080090010001100120013001400

As-depo

800oC

500oC

0

0.5

1

1.5

2

2.5

3

3.5

4

70080090010001100120013001400

As-depo

800oC

500oC

14001300120011001000 900 70080014001300120011001000 900 700800900 700800

Abso

rban

ce

Wavenumber(cm-1)

0

0.5

1

1.5

2

2.5

3

3.5

4

70080090010001100120013001400

As-depo

800oC

500oC

0

0.5

1

1.5

2

2.5

3

3.5

4

70080090010001100120013001400

As-depo

800oC

500oC

14001300120011001000 900 70080014001300120011001000 900 700800900 700800

Abso

rban

ce

Si-O-SiLO phonon La-Silicate

Ge-O

Fig. 4.2 The spectrum results of Ge(10 nm)/ La2O3(5 nm)/n-Si substrate

annealed at 800oC, 500oC and as-deposit .

36

Table. 4.1 FTIR bands and there assigned in the case of the

Ge/La2O3/La-silicate/Si.

Wavenumber(cm-1) Vibration mode

450-540 La2O3 phonon[4.4]

892 Asymmetric stretching mode of Ge-O-Ge bonds

from GeO4 units [4.3]

1050-1100 La-Silicate networks

1252 Si-O-Si bonds arising from LO mode [4.1,4.2]

Fig.4.3 Absorbance spectra of Ge/La2O3/La-silicate/n-Si annealed at various

temperature ranging from 300 to 800 oC.

Fig. 4.3 shows the absorbance spectra of Ge (10 nm )/La2O3(5 nm) annealed at

various temperature ranging from 300 to 800 oC. We use the spectral subtraction

technique. The absorbance of each temperature deducts the absorbance of the

90010001100120013001400 900100011001200130014001400 1300 1200 1100 1000 9001400 1300 1200 1100 1000 900

Abs

orba

nce

(a.u

.)

300oC

800oC

Wavenumber

37

as-deposit. It is observed that the red-shift of peak wavenumber of Si-O-Si bonds of

LO mode. It is observed the shift to left hand of Si-O-Si bond peak from 1182 to

1250 cm-1 and the sharper shape as shown in fig. 4.4.

Fig.4.4 The differential spectrum shift of Ge/La2O3/La-Silicate/n-Si annealed at

200-800oC

70080090010001100120013001400

Abs

orba

nce

Wavenumber(cm-1)1400130012001100100014001300120011001000 900 800 700900 800 700

Si-O-SILO-phonon

Si-O-SILO-phonon La-silicate

200oC

800oC

300oC

450oC

400oC

500oC

550oC

600oC

650oC

700oC

750oC

La-silicate

38

The peak wavenumber of LO mode of unmixed SiO2 layer appears at 1252 cm-1.

Thus, the vibration of the Si-O-Si bond angle must be stable when FTIR spectra at

1252 cm-1 is observed.

The crystal structure of SiO2 and La-silicate is amorphous. In the case of SiO2 layer,

it is reported that the decrease in Si-O-Si bonds of LO mode wavenumber could be

explained in terms of the existence of a compressively–strained SiO2 network near

the interface [4.5]. When SiO2 layer has been compressively strained near the

interface, the blue shift is observed.

There are two reasons why the red-shift occurs. The red shift of Si-O-Si bonds can

result from getting to be relaxed layer or from increasing the thickness of the

La-silicate layer.

Before annealing, in the case of La-silicate, the layer is compressed. The strain is

located near the interface between La-silicate and Si. As annealing temperature is

higher, the favorite bonding state inside the La-silicate layer can be formed. We

conclude the decrease in wavenumber of the Si-O-Si bonds of LO mode could be

interpreted in the terms of existence of a compressively strained La-silicate layer. It

is suggested that the strain-relaxed La-silicate layer can be obtained by high

temperature annealing. However, another reason is considered.

A possible reason for the characteristic and distinct red-shift for Si-O-Si bonds is

increase in thickness. In the case of SiO2, there are reports that the red-shift of

Si-O-Si bonds of LO mode can occur when the thickness is increasing,[4.6,4.7].

39

Fig. 4.5 Si-O-Si bond LO peak wavenumber versus annealing temperature property.

Red-shift of LO wavenumber is observed.

Fig.4.5 shows the LO peak wavenumber versus annealing temperature. We can see

that the wavenumber of LO phonon is increasing as annealing temperature is

increasing. The result of the red-shift of Si-O-Si bond peak from 1182 to 1250 cm-1

means that film uniformity or the increase in thickness of a silicate.

It is said that La-silicate layer becomes inhomogeneous film when it is annealed

under 700oC, but the La-silicate layer can become good uniform film by thermal

treatment over 700oC. The change of wavenumber between 200oC and 800oC can be

interpreted in terms of the viscous relaxation. Annealing temperature above 700 oC

can result in viscous relaxation of La-silicate layer.

1170

1180

1190

1200

1210

1220

1230

1240

1250

1260

200 300 400 500 600 700 800 900200 300 400 500 600 700 800 900Annealing temperature(oC)

Wav

e nu

mbe

r(c

m-1

)1260

1170

125012401230

12201210

120011901180

Si-O-Si bonds of SiO2 LO phononwavenumber

1170

1180

1190

1200

1210

1220

1230

1240

1250

1260

200 300 400 500 600 700 800 900

1170

1180

1190

1200

1210

1220

1230

1240

1250

1260

200 300 400 500 600 700 800 900200 300 400 500 600 700 800 900Annealing temperature(oC)

Wav

e nu

mbe

r(c

m-1

)1260

1170

125012401230

12201210

120011901180

1260

1170

125012401230

12201210

120011901180

Si-O-Si bonds of SiO2 LO phononwavenumber [4.1,4.2]

40

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

70080090010001100120013001400

2 s

12s

22s

32s

362s

422s

30min

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

70080090010001100120013001400

@800oC

2 s12s22s32 s

362 s

422 s

30 minA

bsor

banc

e

Wave number(cm-1)1400 1300 1200 1100 1000 900 800 700

Si-O-Si LOphonon

Fig. 4.6 FTIR spectrum of Ge/La2O3/La-silicate Si annealed at 800oC for 2 - 422 s.

Fig. 4.6 shows the FT-IR spectrum of Ge/La2O3/La-silicate/n-Si annealed at 800oC

for 2 - 422 s. These spectrum are normalized by the peak at the 900 cm-1, which

means Ge-O bonds. The sign of Si-O-Si LO phonon is observed even when

annealing time is 2 s. Then, absorbance is increasing with annealing time. However,

the peak stays at 1250 cm-1 even if annealing time is longer. In other words, the wave

number of the peak position of Si-O-Si bonds of LO mode remains at 1250 cm-1,

whereas the absorbance intensity is increased by prolonging the annealing time.

When annealing temperature is constant at 800oC, and annealing time changes, the

peak shift does not occur in spite of increasing thickness. It is certain that red-shift is

occurred not by increase in thickness silicate layer, by strain-relaxed layer with the

Si-O-Si bonds. The result mean high temperature annealing over 700 oC makes the

Si-O-Si bonds relax.

[4.1,4.2]

41

(a) (b)

Fig. 4.7 Schematic illustration of the crystal structure of (a) Silica glass (b)

La-silicate model [4.9].

Fig. 4.7 (a) and (b) show the schematic illustration of structure of Silicate glass and La-silicate, respectively. [4.9] The structure of the silica glass is amorphous. It is suggested that the random arrangement of tetrahedra is formed by the vibration of the Si-O-Si bond angle. This angle can change from 120 to 180o with a mean value of 144o. For the ideal wavenumber of FTIR of Si-O-Si bonds of silica glass is indicated that 1250 cm-1. According to a central model, the red-shift of 30 cm-1 corresponds to a reduction of the Si-O-Si average bond angle by 7.7o or the Si-Si second neighbor distance by 2.4% at interface[4.8]. We would suggest that La atom plays the role of “network modifier”. It disrupts the

continuity of the glass structure by breaking bonds with the formation of non-bridging oxygens. Non-bridging oxygens join together, and La atoms break the bonds one after another. This process cycle happens many times as temperature is increasing, and the Si-O-Si angle reaches the ideal angle of SiO2, which is energetically stable. It is interpreted that the structure of La-silicate before annealing is

complessively-stressed. The vibration angle is affected by the strain, and the peak wavenumber of the Si-O-Si bonds are lower than 1250 cm-1. Then, when sample is annealed La atoms break the Si-O-Si bonds, and then recombine the Si-O-Si bonds. Si-O-Si bond angle becomes energetically stable gradually with increase in annealing temperature. The strain-relaxed structure can be obtained as annealing temperature is over 700oC, as shown in Fig.4.5.

O2-

Si4+

La atomLa atom

O2-

Si4+

42

4.2 XPS spectrum of La-silicate gate dielectrics

0

0 .2

0 .4

0 .6

0 .8

1

1 .2

18341836183818401842184418461848

Wave number(cm-1)

800oC

600oC500oC

18341836183818401848 1846 1844 1842

Inte

nsity

(a.u

)hν= 7940 eV , Si 1s, TOA = 80o

Ge (10 nm)/La2O3 (5 nm)/n-Si.Si 1s

Fig.4.8 XPS spectra of Si 1s of Ge/La2O3/n-Si annealed at 800, 600, and 500 oC.

X-ray photoelectron Si 1s spectrum of the samples with post metallization

annealing at 500, 600 and 800oC for 30 min measured at photoelectron take-off angle

0

0 .05

0 .1

0 .15

0 .2

0 .25

18391841184318451847

Binding energy(eV)

800oC600oC

500oCInte

nsity

(a.u

) Si-rich La-rich

18391840184118421847 1846 1845 1844 18430

0 .05

0 .1

0 .15

0 .2

0 .25

18391841184318451847

Binding energy(eV)

800oC600oC

500oCInte

nsity

(a.u

) Si-rich La-rich

18391840184118421847 1846 1845 1844 1843 18391840184118421847 1846 1845 1844 1843

43

at 80 degrees. Here, Si 1s spectral intensities arising from Si-substrate are adjusted to

be equal to each other in order to compare the changes in annealing temperature.

When there is a La-rich silicate, a peak is observed around 1842 eV. In addition, a

peak around 1844 eV indicates the presence of Si-rich silicate phase [4.10]. In fig.

4.8, La-silicate layer is increased with increase in annealing temperature. Compared

with the spectra of 500 and 600 oC, it is indicated that Si-rich component with PMA

at 800 oC has much more La-rich component. It is suggested that Si-rich silicate layer

is formed at interface of Si and La-silicate when annealing temperature is higher. We

can obtain favorite interface by forming Si-rich silicate at the surface of Si-substrate.

The XPS data supports the result that high temperature annealing leads to decrease in

Dit.

4.3 Conclusion

In this chapter, in order to examine the change of network structure of La-silicate,

the bonds of LO phonon of Si-O-Si is investigated by FTIR. High temperature

annealing leads the relaxed strain network of La-silicate.

The XPS data shows that La-silicate layer was growing as annealing temperature is

increasing. Strain relaxation can occur with growing of La-silicate layer.

References

[4.1] Z. Cui, et al.: “Characterization of ultrathin silicon oxide films with

mirror-enhanced polarized reflectance Fourier transform infrared spectroscopy”,

Journal of Applied Phisics, Vol.89, No. 9, 1 May 2001.

[4.2] I.P. Lisovskiia, et al.: ”IR spectroscopic investigation of SiO2 film structure”,

44

Thin Solid Films, Vol 213, Issue 2, pp. 164–169 (1992).

[4.3] N. Terakado, et al: “The structure and optical properties of GeO2–GeS2 glasses”,

Journal of Non-Crystalline Solids, 354, 1992–1999 (1997).

[4.4] M. Nieminen, et al.: “Formation and stability of lanthanum oxide thin flms deposited from beta-diketonate precursor”, Applied Surface Science 174 155 (2001).

[4.5] S. Miyazaki, et al: “Structure and electronic state of ultrathin SiO2 thermally

grown on Si(100) and Si(111) surfaces”, Applied Surface Science 113/114 585–589

(1997).

[4.6] K. T. Queeney, et al: “Infrared spectroscopic analysis of the of the Si/SiO2

interface structure of thermally oxidized silicon”, Journal of Applied Phisics,Vol.87,

No.3, February (2000).

[4.7] V. P. Tolstoy, et al.: “HANDBOOK OF INFRARED SPECTROSCOPY OF

ULTRATHIN FILMS”, Wiley- Interscience, pp.429.

[4.8] F. L. Galeener Phys. Rev. B 197 4292 (1979).

[4.9] M. A.Lamkin,et al: ”Oxygen Mobility in Silicon Dioxide and Silicate Glasses :

a Review”, journal of the European Ceramic Society 10, 347-350 (1992).

[4.10] H.Nohira. et al:”Effect of Deposition Temperature on Chemical Structure of

Lanthanum Oxide/Si Interface Structure”, ECS Transactions, 3(2) 171 (2006).

Chapter 5. Conclusion In this study, interface and slow traps are examined by conductance method. In

45

consequence, the peaks of Gp/ω peak in low frequency region can arise from slow

trap located at interface between La2O3 and La-silicate, in chapter 3.

In order to observe the change of network structure of La-silicate gate dielectrics,

the bonds of LO phonon of SiO2 is investigated by FTIR-ATR and XPS. It is

confirmed that strain inside La-silicate layer can be relaxed by high temperature

annealing over 700 oC, in chapter 4. The improvement of electrical characteristics by

high temperature annealing can be explained from the point of strain relaxed

La-silicate layer.

Acknowledgments

First of all, I would like to express my gratitude to my supervisor Prof. Hiroshi

46

Iwai and Prof. Kuniyuki Kakushima for their continuous encouragement and advices

for my study. They also gave me many chances to attend conferences. The

experiences are precious for my present and future life.

I deeply thank to Prof. Takeo Hattori, Prof. Kenji Natori, Prof. Nobuyuki Sugii,

Prof. Akira Nishiyama, Prof. Yoshinori Kataoka, Prof. Kazuo Tsutsui, Associate Prof.

Parhat Ahmet, and for useful advice and great help whenever I met difficult problem.

I also thank research colleagues of Iwai Lab. for their friendship, active many

discussions and many of encouraging words.

I would like to appreciate the support of secretaries, Ms. Nishizawa and Ms.

Matsumoto.

I also express the appreciation to Mr. Mamat, for giving me much advise.

I would like to thank Mr. Daisuke who is reliable man and tough man for his

passion.

Finally, I would like to thank my parents Katsunori and Hisako and my sister

Yurika for their endless support and encouragement.

Takuya Seki February, 2012

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