EFFECTS OF PROCESS VARIATION ON THE PERFORMANCE...

EFFECTS OF PROCESS VARIATION ON THE PERFORMANCE PARAMETER OF

VLSI INTERCONNECTS

THESIS

Submitted for the degree of

DOCTOR OF PHILOSOPHY

IN ELECTRONICS AND COMMUNICATION ENGINEERING

By

AIR COMMODORE (Retd) K. G. VERMA

Under the supervision of

Dr. B. K. KAUSHIK

and

Prof. RAGHUVIR SINGH

SCHOOL OF ELECTRONICS AND COMMUNICATION ENGINEERING

SHOBHIT UNIVERSITY, MEERUT-250110

2011

EFFECTS OF PROCESS VARIATION ON THE PERFORMANCE

PARAMETER OF VLSI INTERCONNECTS

A THESIS

Submitted in fulfillment of the

Requirements for the award of the degree

of

DOCTOR OF PHILOSOPHY

in

ELECTRONICS AND COMMUNICATION ENGINEERING

By

AIR COMMODORE (Retd) K.G. VERMA

SCHOOL OF ELECTRONICS AND COMMUNICATION ENGINEERING SHOBHIT UNIVERSITY, MEERUT-250110

2011

Dedicated

To

“My Little Angel”

AISHANYA

For lighting up my whole world by just her mere existence.

i

CANDIDATE’S DECLARATION

I, hereby, declare that the work presented in the thesis entitled “EFFECTS

OF PROCESS VARIATION ON THE PERFORMANCE

PARAMETER OF VLSI INTERCONNECTS” in fulfillment of the

requirements for the award of Degree of Doctor of Philosophy, submitted in

the School of Electronics and Communication Engineering at Shobhit

University, Meerut is an authentic record of my own research work

under the supervision of Dr. B. K. Kaushik and Prof. Raghuvir Singh.

I also declare that the work embodied in the present thesis:

i. is my original work and has not been copied from any

Journal/thesis/book, and

ii. has not been submitted by me for any other Degree.

(Air Commodore (Retd.) K.G. Verma)

Shobhit University, Meerut

ii

CERTIFICATE OF THE SUPERVISOR(S)

This is to certify that the thesis entitled “Effects of Process Variation on

the Performance Parameter of VLSI Interconnects” is a record of

bonafide research carried out by Air Commodore (Retd) K. G. Verma,

under our guidance and supervision and that no part of this thesis has been

submitted for any other degree or diploma. Air Commodore (Retd) K.G.

Verma has worked under our supervision for a minimum period of 24

months from the date of his Ph.D. registration.

It is further certified that Air Commodore (Retd) K.G. Verma has

worked with us for the required period in the School of Electronics &

Communication Engineering at Shobhit University, Meerut.

The assistance and help received during the course of work have been

duly acknowledged.

Prof. Raghuvir Singh Dr. B. K. Kaushik

(Internal Supervisor) (External Supervisor)

Shobhit University G.B. Pant Engg. College, Pauri Garhwal

Meerut (UP) (Now at Indian Inst. of Tech.- Roorkee)

Shobhit University, Meerut

iii

ABSTRACT

The feature size of integrated circuits has been aggressively reduced in the

pursuit of improved speed, power, silicon area and cost characteristics.

Semiconductor technologies with feature sizes of several tens of nanometers are

currently in development. Aggressive scaling of semiconductor process technology

over the last several decades has resulted in creation of many new electronics

products and information appliances. The trend is expected to continue for the coming

years and create countless opportunities and challenges. Recent developments in

semiconductor industry show a rapid increase in chip frequency and design

complexity. Introduction of newer technologies is now moving towards a two year

cycle as compared to traditional three year cycle. Though technology scaling helps in

addressing design complexity and performance trends, it opens up a whole new

spectrum of design validation challenges.

Technology scaling allows packing billions of transistors within a chip. On the

other hand, it is not easy to fabricate very small transistor with analogous

characteristics, which leads to variations. It is now well known that transistor level

random local variations are growing rapidly in each fabrication technology

generation. Therefore, it is necessary to quantify variation in silicon.

The performance of VLSI/ULSI chip is becoming less predictable as device

dimensions shrink below the sub-100-nm scale. The reduced predictability can be

attributed to poor control of the physical features of devices and interconnects during

the manufacturing process. Variations in these quantities result in variations in the

electrical behavior of circuits. These variations have interdie and intradie components,

as well as layout pattern dependencies. The device material variations in geometry

(tox, Leff , W), and variations in doping levels and profiles have a direct impact on the

behavior of a MOSFET. Variations in the linewidth affect the resistance and the

interlayer capacitance. Variations in the interwire spacing may cause a significant

iv

degradation in the signal integrity. Layout pattern dependent variations within the

interlayer oxide and the chip multiprocessing process also have a significant impact

on the interconnect parasitics. The dissimilar sources of variations in the IC

fabrication process lead to both random and systematic effects on circuit performance.

All of these make it increasingly difficult to accurately predict the performance of a

circuit at the design stage, which ultimately translates to a parametric yield loss. The

recent trends in VLSI chip exhibit significant variations within a chip and between

chips, due to the high complexity of design and the presence of large number of

correlated parameters.

Process variations are not completely random. It can be divided into

deterministic part and non-deterministic part. Random variations are intrinsic

fluctuations in process parameters such as dopant fluctuations from wafer to wafer, lot

to lot. On the other hand, systematic variations depend on the layout pattern and are

therefore predictable for the systematic part, the variations need to be experimentally

modeled and calibrated, in order to either compensate hiring the design phase or

captured in the analysis phase. These effects, which include optical proximity

correction (OPC), residual error and chemical mechanical planarization (CMP)

dishing, have a substantial but deterministic impact on the critical dimension (CD) of

a transistor gate or the width and thickness of an interconnect wire. By accounting for

systematic part of process variation in timing analysis, uncertainty can be reduced,

thereby achieving closer bound for circuit performance. With the shrinking feature

size in VLSI technology, the impact of process variation is increasingly felt. Since the

width, thickness and spacing of interconnects are each scaled by 1/α (scaling factor),

cross-section areas must scale by 1/α2. The length of short distance interconnections is

scaled by 1/α, so that resistance is increased by α. With decreasing device dimensions,

increase in the levels of integration is observed and consequently there is increase in

the die size. This lengthens the interconnections from one side of the chip to the other

end and, therefore, both resistance and capacitance of interconnects are increased,

producing much larger time constants. Thus, the effects of increased propagation

delays, signal decay, and clock skew will reduce the maximum achievable operating

frequency, even though the smaller transistors produce gates with less delay.

v

As technology scaling trend continues, interconnect parasitic play dominant

role in determining chip performance and functionality. RLC delays become

significant portion of chip delay and noise/crosstalk caused due to parasitic coupling

poses threat to circuit functionality. The intense drive for signal integrity has been at

the forefront of rapid and new development in CAD algorithms. With increasing

demands for high signal speeds coupled with decreasing feature sizes, interconnect

effects such as signal delay, distortion and crosstalk become the dominant factors

limiting overall performance of high-speed systems. If not considered during the

design stage, interconnect effects can cause failed designs. Since extra iterations in the

design cycle are costly, accurate prediction of these effects is a necessity in high-

speed designs.

This thesis undertakes the evaluation of propagation delay deviations for

Driver-Interconnect-Load (DIL) system due to variations in oxide thickness; threshold

voltage; driver width and interconnect resistive and capacitive parasitic. The impact of

process induced variations on propagation delay of the circuit is discussed for three

different technologies i.e 130nm, 70nm and 45nm using Monte Carlo simulations.

The comparison between three technologies shows that as device size shrinks, the

process variation becomes dominant and subsequently gives rise in delays. The

simulation also reveals that process variation has large effect on the driver delay due

to variation in threshold voltage, oxide thickness and width of the gate. But there is a

little variation in delay due to interconnect resistance although large delay variation

can be observed due to interconnect capacitance variations.

vi

ACKNOWLEDGEMENTS

The largest journey starts but with one step, the huge trees sprout up from one small

seed, the deep rivers have their origin in just one little drop, the great treatises open up

with one small word & all the works of research are initiated with a single idea or a

deep thought. I also embarked on my little journey in the academic field with a

thoughtful suggestion from someone who has been well wisher throughout my life. I

know at my age neither it was easy nor that simple to take up this challenge but I

wanted to prove myself not to the world but to myself that I could still do some

meaningful work before I hang-up my shoes. But I know I couldn’t accomplish this

alone, I needed the guidance & support from my seniors in this field.

It has never been in the finesse of things that a small part of any thesis should

serve as a prologue to express the debt of gratitude and thankfulness to the mighty

minds that were the main inspiration and forces in carrying out and completing this

academic work.

At the very outset, I fail to find, adequate words to express my endeavoring

sincere thanks & profound gratitude to my chief guide & supervisor Prof. Raghuvir

Singh, an Academic Advisor in Shobhit University, Meerut with extra-ordinary skills

& academic depth who has devoted his life in enlightening the minds of so many &

above all a humanist in understanding the agony of the students. I will always

remember him as a “Param Guru”.

A deep appreciation from the core of my heart is expressed for my external

supervisor Dr. B. K. Kaushik, Assistant Professor, IIT, Roorkee, who in-spite of his

hectic schedule always had time to clear the doubts and intricacies of the subject. I am

thankful for his sharp & concrete suggestions, intellectual support, personal interest &

vii

constant encouragement throughout the period of research study that enabled me to

carry out this research work. I will always remember him as an amicable teacher.

I have no words to thank Prof. R. P. Agarwal, Pro-Vice Chancellor, Shobhit

University, Ex. Prof. & Dean (Academics) at IIT, Roorkee, Ex Vice Chancellor of B.

U., Jhansi, Ex. Vice Chancellor, Dr. H. S. Gour University, Sagar, for his feedback in

improving the quality of my work & for his able guidance toward my work. My

experience with him has made me understand what exactly a pupil can learn from a

passionate teacher. He is a person of unstinting generosity, gifted with a rare

combination of engineering knowledge.

I am at a loss to find words to thank Prof. Sankar Sarkar, Director, School of

Electronics & Communication Engg., Ex. Prof. IIT, Roorkee & Ex. Dean of faculty of

Engineering, Modi Institute of Technology & Science, for his added responsibility

and impressing upon me the virtues of minute details during the entire journey. I am

extremely grateful to him for his unwavering support.

I cannot close this chapter without acknowledging the constant support &

selfless of my wife ‘Ritu’ who takes so much pride in my pursuance of excellence

and exploring the new horizons in my field.

In the end I have to thank Almighty, who is always there to hold my hand &

show the right path whenever I waver. He is the eternal guide for me always in my

life.

Date: (Air Commodore (Retd.) K. G. Verma)

Place: Meerut

viii

CONTENTS Page No.

DECLARATION i

CERTIFICATE ii

ABSTRACT iii

ACKNOWLEDGEMENTS vi

CONTENTS viii

LIST OF FIGURES xii

LIST OF TABLES xv

LIST OF SYMBOLS xvii

LIST OF ABBREVIATIONS xix

Chapter 1 INTRODUCTION AND STATEMENT OF THE PROBLEM

1.1 INTRODUCTION 1

1.2 STATEMENT OF PROBLEM 5

1.3 ORGANIZATION OF THESIS 7

Chapter 2 PROCESS VARIATION AND INTERCONNECTS - A REVIEW

2.1 INTRODUCTION 9

2.2 CLASSIFICATION OF VARIATIONS 12

2.3 RANDOM PROCESS VARIATIONS SOURCES 15

2.3.1 Device Geometry Variations 18

2.3.2 Device Material Parameter Variations 19

2.3.3 Device Electrical Parameter Variations 20

2.4 INTERCONNECTS 21

2.4.1 Modeling Interconnect as RC & RLC Circuits 25

2.4.2 Lumped and Distributed Models 27

2.4.3 Cross-talk Noise 32

ix

2.4.4 Interconnect Objectives 36

2.5 PROCESS VARIATIONS IN TERCONNECTS 38

2.5.1 Size Effects and Temperature Independence 40

2.5.2 Process Variations in Interconnects 40

2.5.3 Sources of Interconnect Process Variations 43

2.5.3.1 Photolithography 44

2.5.3.2 Metallization 47

2.5.3.3 Rapid Thermal Process 48

2.5.3.4 Chemical Mechanical Polishing 49

2.6 INTERCONNCT CHARACTERIZATION 51

2.6.1 On Chip Interconnect Variations 52

2.6.2 Delays due to Interconnect Variations 56

2.6.3 Parametric Delay Evaluation under Process Variation 58

2.7 INTERCONNECT ANALYSIS 60

Chapter 3 EFFECT OF PROCESS BASED OXIDE THICKNESS

VARIATION ON THE DELAY OF DIL SYSTEM USING

MONTE CARLO ANALYSIS

3.1 INTRODUCTION 62

3.2 PROCESS VARIATION ANALYSIS 70

3.3 EFFECT OF OXIDE THICKNESS VARIATION ON DELAY OF

DRIVER-INTERCONNECT-LOAD SYSTEM 71

3.4 CONCLUSION 83

Chapter 4 ANALYSIS OF PROPAGATION DELAY DEVIATION UNDER

PROCESS INDUCED THRESHOLD VOLTAGE VARIATION

4.1 INTRODUCTION 84

4.2 MONTE CARLO ANALYSIS 92

x

4.3 EFFECT OF THRESHOLD VOLTAGE VARIATION ON DELAY

OF DRIVER-INTERCONNECT-LOAD SYSTEM 94

4.4 CONCLUSION 103

Chapter 5 MONTE CARLO ANALYSIS OF PROPAGATION DELAY DUE

TO PROCESS INDUCED DRIVER WIDTH VARIATIONS

5.1 INTRODUCTION 104

5.2 DRIVER WIDTH DEPENDENCE IN DIFFERENT MODES

OF OPERATION 108

5.3 MONTE CARLO ANALYSIS 111

5.4 EFFECT OF DRIVER WIDTH VARIATION ON

DELAY OF DRIVER-INTERCONNECT-LOAD SYSTEM 112

5.5 CONCLUSION 121

Chapter 6 MONTE CARLO ANALYSIS OF PROPAGATION DELAY DUE

TO PROCESS INDUCED LINE PARASITIC VARIATIONS


6.2 ON CHIP INTERCONNECT VARIATIONS 125

6.3 INTERCONNECT MODELS 126

6.4 MONTE CARLO ANALYSIS OF DIL SYSTEM 132

6.5 RESULTS AND DISCUSSION 133

6.6 CONCLUSION 138

Chapter 7 CONCLUSIONS AND SUGGESTIONS FOR FUTURE WORK


7.2 SUMMARY OF IMPORTANT FINDINGS 141

7.2.1 Introduction to Problem 141

7.2.2 Process Variation and Interconnects 141

7.2.3 Effect of Process Based Oxide Thickness Variation 142

xi

7.2.4 Propagation Delay Analysis Under Threshold

Voltage Variation 142

7.2.5 Effect of Driver Width Variations on Propagation Delay 142

7.2.6 Analysis of Propagation Delay Due to

Line Parasitic Variation 143

7.3 MAIN CONTRIBUTIONS 143

7.4 SUGGESTIONS FOR FUTURE WORK 146

APPENDIX A 151

REFERENCES 152

LIST OF PUBLICATIONS 188

xii

LIST OF FIGURES

Figure No.

Title Page No.

Figure 2.1

Classification of various process variations

14

Figure 2.2

Placement of various interconnects (Local,

Intermediate and Global) in Microprocessor Unit

(MPU) and Application Specific Integrated

Circuit (ASIC)

24

Figure 2.3

Development of interconnect models (a) RC

model; (b) RLC model

30

Figure 2.4

Schematic of a typical interconnect structure

31

Figure 2.5

Orientation of the copper interconnect in oxide

41

Figure 2.6

Hierarchy of variation for interconnects

43

Figure 2.7

CMP induced OCV on interconnects

53

Figure 3.1

SPICE input and output voltage due to variation

in tox for 130 nm technology

72

Figure 3.2

Delay of driver and driver with interconnect due

to variation of tox_n

74

Figure 3.3

Percentage change in delay of driver and

interconnect line with the variation in oxide

thickness

74

xiii

Figure 3.4

SPICE output and input voltage variation due to

change in tox for 70 nm technology

76

Figure 3.5

Variation in driver and line delay due to change

in oxide thickness

78

Figure 3.6

Percentage variation in Driver and line delay due

to percentage change in oxide thickness

78

Figure 3.7

SPICE Output and input voltage variation due to

change in tox for 45 nm technology

80

Figure 3.8

Variation in all Delay due to change in oxide

thickness of NMOS

82

Figure 3.9

Percentage Variation in Driver and line delay

due to percentage change in oxide thickness of

NMOS

82

Figure 4.1

Driver Interconnect Load (DIL) System

92

Figure 4.2

SPICE input and output waveform through DIL

for 130 nm technology Driver

95

Figure 4.3



97

Figure 4.4



100

xiv

Figure 4.5

Comparison of percentage change in delay due

to variations in threshold voltage for 130 nm, 70

nm and 45 nm technologies

102

Figure 5.1

Driver Interconnect Load (DIL) System 108

Figure 5.2



113

Figure 5.3



115

Figure 5.4



117

Figure 5.5

Comparison of percentage change in delay due

to variations in driver width for 130 nm, 70 nm

and 45 nm technologies

120

Figure 6.1

(a) Single lump of an RLC model; (b) N-

Segment RLC interconnect with G neglected.

131

Figure 6.2

Driver Interconnect Load (DIL) System

133

Figure 6.3

Plot showing percentage deviation in

propagation delay with respect to process

induced capacitance variation

136

Figure 6.4

Plot showing percentage deviation in

propagation delay with respect to process

induced resistance variation

138

xv

LIST OF TABLES

Table No. Title

Page No.

Table 2.1 Comparison of ITRS M1 Physical Line Dimension

Targets to Intel Data

38

Table 3.1 Variation in delay due to change in oxide thickness of

NMOS and PMOS for 130 nm fabrication process

technology

73



technology

77



technology

81

Table 4.1 Variation in delay due to change in threshold voltage of

NMOS & PMOS for 130 nm fabrication process

technology

96

Table 4.2

Table 4.3

Variation in delay due to change in threshold voltage of


technology

Variation in delay due to change in threshold voltage of


technology

98

101

xvi

Table 5.1 Variation in delay due to change in driver width of

NMOS & PMOS for 130nm fabrication process

technology

114



technology

116



technology

119

Table 6.1 Variation in propagation delay due to deviation in

capacitance for 130 nm, 70 nm and 45 nm fabrication

technology

135

Table 6.2 Variation in propagation delay due to deviation in

resistance for 130 nm, 70 nm and 45 nm fabrication

technology

137

Table 7.1 Maximum and Minimum variation of delays under

process variation in three technologies

145

xvii

LIST OF SYMBOLS Ion On Current

Ioff Off Current

1/α Scaling Factor

oxt Gate Oxide Thickness

tox_n NMOS Oxide Thickness

tox_p PMOS Oxide Thickness

Leff Effective Driver Channel Length

W MOSFET Channel Width

L MOSFET Channel Length

W/L MOSFET Aspect Ratio

VT or Vt Threshold Voltage of Transistor

Si Silicon

SiO2 Silicon-Dioxide

σ Sigma Variation

Cov Overlap Capacitance

Clat Lateral Capacitance

Cfr Fringe Capacitance

λCu Mean Free Path of Copper

totR Lumped line resistance

totC Lumped line capacitance

totL Lumped line inductance

cC Lumped coupling capacitance

M Lumped mutual inductance

r Distributed line resistance per unit length

c Distributed line capacitance per unit length

l Distributed line inductance per unit length

cc Distributed coupling capacitance per unit length

xviii

ℓ Interconnect length

ω0 Effective line-widths

Wi Width of Interconnect

T Metal Thickness

H Interlayer Dielectric Thickness

S Spacing between Interconnect Lines

TOV Zero bias threshold voltage

α Velocity saturation index

𝛾 Fabrication Process Parameter

𝑁𝐴 Doping Concentration of P-Type Substrate

𝐶𝑜𝑥 Gate oxide capacitance

𝛷𝑓 Fermi Potential

𝑉𝑆𝐵 Source Bulk Voltage

K Boltzmann Constant

T Room Temperature

𝑛𝑖 Intrinsic Carrier

𝑞 Electron Charge

𝜀𝑠 Permittivity of Silicon

tnV Threshold voltage (positive) of NMOS

tpV Threshold voltage (negative) of PMOS

nW NMOS Driver Width

pW PMOS Driver Width

g Transconductance

xix

LIST OF ABBREVIATIONS

OCV On-Chip Variation

CAD Computer Aided Design

EDA Electronic Design Automation

GSI Giga scale integration

ECP Electro Chemical Plating

CPU Central Processing Unit

ITRS International Technology Roadmap for Semiconductors

IC Integrated circuit

DSM Deep Sub-Micron

PVT Process, Voltage and Temperature

CMP Chemical Mechanical Planarization

NMOS n-MOSFET

PMOS p-MOSFET

RDF Random Dopant Fluctuation

LER Line Edge Roughness

OTV Oxide Thickness Variation

CD Critical Dimension

RSM Response Surface Method

DFM Design for Manufacturing

DFY Design for Yield

SSTA Statistical Static Timing Analysis

STA Static Timing Analysis

xx

PDF Probability Density Function

CDF Cumulative Distribution Function

MC Monte Carlo

RET Resolution Enhancement Technology

DIL Driver-Interconnect-Load

RLC Resistance-Inductance-Capacitance

RC Resistance-Capacitance

TEM Transverse Electromagnetic Mode

MPU Microprocessor Unit

FPGA Field Programmable Gate Arrays

CD Critical Dimension

D2D Die-to-Die

WID within-die

RTP Rapid Thermal Process

PVD Physical vapor deposition

ALD Atomic layer deposition

RTA Rapid thermal annealing

AFP Abrasive-free process

ITP Interconnect Technology Parameters

ILD Inter Level Dielectric

DIBL Drain Induced Barrier Lowering

RSM Response Surface Method

OPC Optical proximity correction

ULSI Ultra Large Scale Integration

xxi

VLSI Very Large Scale Integration

MOSFET Metal Oxide Semiconductor Field Effect Transistor

CMOS Complementary metal oxide semiconductor

SPICE Simulation Program with Integrated Circuits Emphasis

SRAM Static Random Access Memory

DRAM Dynamic Random Access Memory

ASIC Application Specific Integrated Circuit

PVT Process Voltage Temperature

CNTs Carbon Nano Tubes

WDM Windows Driver Model

1

Chapter 1

INTRODUCTION AND

STATEMENT OF THE PROBLEM

1.1 INTRODUCTION

MOS transistor based integrated circuits have completely transformed the world. As

per estimation there are more than 20 billion silicon semiconductor chips currently in

use with an additional 700,000 sold each day. The continually shrinking size of the

MOS transistors that result in faster, smaller, and cheaper systems have enabled

widespread use of chips. Among these semiconductor chips, majority of components

are high-performance general-purpose microprocessor. With the shrinking feature size

in VLSI technology, the impact of process variation is increasingly felt (Bowman,

2001). Process variation has become a major concern in the design of many

nanometer circuits, including interconnect pipelines.

The scaling down of device size in ICs i.e. scaling of integrated circuits has

resulted in more complex chips having millions of interconnections. Also with

increase in switching speed and mixing devices with different driving capability on

the same chip result in crosstalk effects. The prime objectives of technology scaling

2

are increase in packing density, decrease in the gate delay and decrease in power

dissipation (Weste and Eshraghian, 1992). Higher densities are only possible if the

interconnects are also scaled. In interconnect scaling; the width reduces with increase

in density. Reduced width means increased resistance and denser interconnect means

higher coupling capacitance (Shoji, 1996). With huge functionalities being integrated,

long interconnects have become a common feature. The increase in wire density and

high operational frequency of the circuit on-chip causes coupled noise or crosstalk

because of associated parasitic, which may lead to critical delays or logic

malfunctions and hence become an important parameter to test. The major difficulties

in performance improvement are an increased interconnects delays and an increased

cross coupling effect (Elgamel et al., 2003). Crosstalk effect induces pulse and delay.

The performance of a high-speed chip is highly dependent on the

interconnects, which connect different macro cells within a VLSI/ULSI chip.

Interconnects are metal or polysilicon structures used to connect different

cells/devices. The function of interconnects or wiring systems is to distribute clock

and other signals and to provide power/ground to and among the various

circuits/systems functions on the chip. The performance such as time delay and power

dissipation of a high-speed chip is highly dependent on the interconnects. To escape

prohibitively large delays, designers scale down global wire dimensions more slowly

than the transistor dimensions (El-Moursy and Friedman, 2003b; El-Moursy and

Friedman, 2004a; El-Moursy and Friedman, 2007). As technology advances,

interconnects have turned out to be more and more important than the transistor

resource, and it is essential to use global interconnects optimally (Poechmueller et al.,

3

1991). For high-density high-speed chips of submicron-geometry, it is mostly the

interconnection rather than the device performance that determines the chip

performance.

Process variations manifest themselves as the uncertainties of circuit

performance, such as delay, noise and power consumption. Environmental variations,

such as supply voltage and temperature variations, also impact circuit delay and noise.

The primary sources of manufacturing variation include deposition, Chemical

Mechanical Planarization (CMP), Etching, Resolution Enhancement Technology

(RET). Transistor performance depends heavily on gate dimension. A small gate

variation changes the channel length, creating a variation in Ion and Ioff. Dependence of

transistor current is increasingly non-linear to channel length. As a result the

variability in current Ion and Ioff has been increasing with process node size. A 10%

transistor gate variation can translate to as much as a variation of -15% to +25% in

gate delay. Interconnect parasitic are significant and complex components of circuit

performance, signal integrity and reliability in IC design. Copper resistivity rises

dramatically below 90nm due to increased electron scattering on grain boundaries.

Interconnect delay in deep sub-micron processes can often dominate total delay and

thus should be modeled as accurately as possible. To address the effect, great amount

of research has been done recently, such as the clock skew analysis under process

variation, statistical performance analysis, worst case performance analysis,

parametric yield estimation, impact analysis on micro architecture and delay fault test

under process variation. Since the width, thickness and spacing of interconnects are

each scaled by 1/α (scaling factor), cross-section areas must scale by 1/ α2. Thus, for

4

short distance interconnections the conductor length is also scaled by 1/α, so that

resistance is increased by α. With decreasing device dimensions, the industry is also

seeing further increases in the levels of integration and consequent increases in die

size. This lengthens the interconnections from one side of the chip to the other end

and, therefore, both resistance and capacitance of interconnects are increased,

producing much larger time constants. Thus the effects of increased propagation

delays, signal decay, and clock skew will decrease maximum achievable operating

frequency, even though the smaller transistors produce gates with less delay. One

solution to this problem has been to make use of multilayer interconnections with

thicker, wider conductors and thicker separating layers. Other method is to use

cascaded drivers and repeaters to reduce the effects of long interconnect. A further

option is to use optical interconnection (Agarwal, 2002) techniques where a very high

level of interconnection is required for speed circuits.

The propagation delay induced by word lines, bit lines, clock lines, and bus

lines in memory or logic VLSI will remain the key concerns while designing the

interconnects. The performance of VLSI/ULSI chip is becoming less predictable as

device dimensions shrink below the sub-100-nm scale (Boning and Nassif, 2000). The

reduced predictability is due to poor control of the physical features of devices and

interconnects during the manufacturing process. Variations in these quantities result

in variations in the electrical behavior of circuits. These variations have interdie and

intradie components, as well as layout pattern dependencies. The device material

variations in geometry (tox, Leff, W), and variations in doping levels and profiles have a

direct impact on the behavior of a MOSFET. Variations in the linewidth affect the

5

resistance and the interlayer capacitance. Variations in the interwire spacing may

cause a significant degradation in the signal integrity. Layout pattern dependent

variations within the interlayer oxide and the chip multiprocessing process also have a

significant impact on the interconnect parasitic. The dissimilar sources of variations in

the IC fabrication process lead to both random and systematic effects on circuit

performance. All of these make it increasingly difficult to accurately predict the

performance of a circuit at the design stage, which ultimately translates to a

parametric yield loss. The recent trends in VLSI chip exhibit significant variations

within a chip and between chips, due to the high complexity of design and the

presence of large number of correlated parameters. Therefore, it is necessary to

evaluate and understand the effect of process variations on the interconnects

performance parameters.

1.2 STATEMENT OF THE PROBLEM

A detailed literature review in the area of process variations in interconnects

leads to the conclusion that in current scenario, it is essential to take a fresh look at

propagation delay deviations in inductive long interconnects through an improved

approach. This work addresses the requirement through adequate in-depth analysis

and supporting computer simulations. Based on the approach taken for the purpose

the problem dealt with can be stated as follows:

6

• Introduction of a composite representation for CMOS-driven interconnects.

The model combines Driver-distributed RLC interconnect-Load system for

evaluating the effect of process variations on overall propagation delay.

• Delay deviation at the far ends of a CMOS driven interconnects due to

process based oxide thickness variation in Driver-Interconnects-Load (DIL)

System Using Monte Carlo Analysis.

• Analysis of the effects of threshold voltage variation on propagation delay in

DIL system for three fabrication technologies.

• Comprehensive analysis of the effect of channel width variation on the

propagation delay through driver-interconnect-load (DIL) system. The

impact of process induced driver width variations on propagation delay of

the circuit is discussed for three different technologies i.e 130nm, 70nm and

45nm.

• Evaluations of the effect of interconnect resistive and capacitive parasitic

variation on propagation delay for different fabrication technologies.

7

1.3 ORGANIZATION OF THE THESIS

The main aim of the present work is to analyze the effect of process variation

on propagation delay in interconnect pipelines. The contributions and important

developments are presented in this thesis in the following sequence:

• The present chapter 1 introduces the subject of the thesis topic. The

objectives of the problem are identified.

• Chapter 2 reviews the past research works carried out on process variation

and interconnects in terms of propagation delay. Various aspects of CMOS

driver, interconnects and process variation have been discussed. The role of

interconnect parasitic on performance is examined. The effect of process

variation on delay and power dissipation is also discussed.

• Chapter 3 presents an analysis of propagation delay deviation at the far ends

of a CMOS driven interconnects due to process based oxide thickness

variation in Driver-Interconect-Load (DIL) System Using Monte Carlo

Analysis.

• Chapter 4 presents the study of the analysis of the effects of threshold

voltage variation on propagation delay in DIL system for three fabrication

technologies. This study is demonstrated using SPICE simulation.

8

• Chapter 5 presents a complete analysis of the effect of channel width

variation on the propagation delay through driver-interconnect-load (DIL)

system. The consequence of process induced driver width variations on

propagation delay of the circuit is discussed for three different technologies

i.e 130nm, 70nm and 45nm.

• Chapter 6 presents the effect of interconnect resistive and capacitive

parasitic variation on propagation delay for different fabrication

technologies. The interconnect parasitic variation is due to changes in the

width of interconnect.

• Finally, Chapter 7 summarizes the work and draws conclusions on the basis

of the results presented in the preceding chapters. Some suggestions for

future works are also provided in this chapter.

9

Chapter 2

PROCESS VARIATION AND INTERCONNECTS –

A REVIEW

2.1 INTRODUCTION

Deep Sub-micron (DSM) technology allows packing billions of MOSFETs within a

single chip. However, it is becoming increasingly hard to fabricate extremely small

transistors with same characteristics. As the feature size continues to decrease in

advanced DSM nodes, the capability to forecast various characteristics of manufactured

transistor is worsening. This is because of the increased complexity of the semiconductor

manufacturing process and the atomic scale control required for fabricating transistors.

Although, process variability used to be a major concern for analog designers, but, now it

is also a foremost design issue (Borkar et al., 2003; Srivastava et al., 2005; Su et al.,

2003) for a digital designers too and therefore its prediction is among highest priority.

10

With complementary metal-oxide semiconductor (CMOS) integrated circuits

shrinking to the nanometer scale, the impact of process variation on integrated circuit

design and manufacture has become critical. Process variations with a random nature will

directly result in changes in the physical structure of integrated circuits, thereby affecting

their performance. Relevant research has become a hot spot of integrated circuit design

and verification.

As critical dimensions of integrated circuits get smaller, the impact of process

variation on the performance of VLSI systems must be considered (ITRS) (Dai and Ji,

2001; Xiong et al., 2005; Nassif, 1998a; Nassif, 1998b; Nassif, 2000a; Nassif, 2001a;

Nassif, 2001b; Sauter et al., 1999; Sauter et al., 2000a; Sauter et al., 2000b; Teene, 2005;

Zarkesh et al., 1999; Zanella et al., 2000; Sharifzadeh et al., 1989). In particular, the

electrical performance of an integrated circuit is primarily affected by environmental and

physical factors (Nassif, 2000b). Environmental factors that occur during chip operation

include power supply variations and temperature changes across the chip. Physical

factors affected during fabrication include, but are not limited to, interconnect line-width

(Steinhogl et al., 2004; Jiang et al., 2001; Kitada et al., 2007), metallic grain size

(Schindler et al., 2003a; Schindler et al., 2003b; Kitada et al., 2007; Sun et al., 2008),

and transistor channel length (Bowman, 2001; Neiroukh and Song, 2005; Friedberg et al.,

2005a; Friedberg et al., 2005b; Okada et al., 2003; Azuma et al., 1998). While much

effort has been made on optimizing design and manufacturing at the global level for

interconnects (Luman and Davis, 2004; Zarkesh and Meindl, 1999; Zarkesh et al., 2003a;

11

Zarkesh et al., 2003b; Kapur et al., 2002; Anderson et al., 2001; Anderson et al., 2002;

Warnock et al., 2002; Wisniewski et al., 2003a; Wisniewski et al., 2003b; Pan et al.,

1999; Chern et al., 1992; Lopez, 2009), noticeable performance degradation is occurring

especially as local interconnect line-width dimensions approach the mean free path of

copper (λCu=40 nm) (ITRS) (Steinhogl et al., 2002). Overall, these factors can have a

great impact on the behavior exhibited by the circuit (Nassif, 2001a; Lopez, 2009).

In nano-scale integrated circuits, interconnect delay has become one of the key

parameters in high-performance chip design. In order to accurately estimate the

interconnect delay; many researchers have proposed a variety of methodology. However,

with the rapid development of semiconductor technology, process variations will give

rise to great effects on the interconnect delay which cannot be ignored (Manney et al.,

1992). Many approximations may contain errors as a result of not considering process

variations. Therefore, we should consider process variation issues in delay estimations to

make them applicable to today's nano-scale integrated circuit design.

The semiconductor industry has been fueled by enhancements in integrated circuit

(IC) density and performance, resulting in information revolution for over four decades

and is expected to continue in future. The periodic improvement in density (as per

Moore’s Law) and performance has, been mainly achieved through aggressive device

scaling and/or increase in chip size. As far as MOS transistor scaling is concerned, device

12

performance improves as gate length, gate dielectric thickness, and junction depth are

scaled. In sharp contrast, scaled chip wiring (interconnect) suffers from increased

resistance due to decrease in conductor cross-sectional area and may also suffer from

increased capacitance if metal height is not reduced with conductor spacing. As operating

frequencies continue to spiral upward, parasitic inductive effects must also be considered

(Mezhiba and Friedman, 2002; Mezhiba and Friedman, 2004). Thus, interconnect

parasitic play an increasing role in overall chip performance as feature size scales.

This chapter reviews and discusses key issues related to process variations in

general, interconnects and their importance and latter effect of process variations in

interconnects are dealt.

2.2 CLASSIFICATION OF VARIATIONS

Generally, variability can be mainly categorized to Process and Environmental

variations. Under, process variation category, the main sources of random process

variation are random dopant fluctuation (RDF), line edge roughness (LER) and oxide

thickness variation (OTV). This leads to variation in threshold voltage and subsequently

in drive current. Hence, the performance parameters like delay and power will deviate

from their desired nominal values (Zhou and Khouas, 2005). On the other hand,

environmental variations include supply and temperature variations. The source of supply

13

variation is IR drop in the power grid. Supply variations are further aggravated by

inductive effects in power rails. The variation in switching activity leads to temperature

hot spots inside the chip.

Based on the ease of predictability, process variations can be further classified to

systematic and non-systematic. The behavior of systematic variation is primarily because

of physical parameter variations such as variations due to optical proximity, CMP and

metal fill etc. These variations are well-understood and documented and can be predicted

apriori, by analyzing the layout of the design. These variations can be modeled before

manufacturing by exhaustive analysis of the designed layout.

Non-systematic process variations have uncertain or random behavior. These

variations arise from the processes that are orthogonal to design implementation (Das,

2009). The statistical characteristics of these process parameters are known during the

design time and are modeled using random variables. The examples of non-systematic

variations are due to RDF, LER and OTV.

Depending on the spatial scales of the variation, the non-systematic variation has

two categories of (i) Die-to-Die or Inter-die or Global Variation and (ii) Within-Die or

Intra-die or Local Variation. Die-to-die (or inter-die or global) variations affect all

transistors within a die in the same way and have identical effect. For example, gate

14

length variation of all the devices on the same chip being larger or smaller than the

nominal value. The die-to-die variations result in shift in the process from lot-to-lot,

wafer to wafer, reticle to reticle on each gate in the chip. On the other hand, within-die

(or intra-die or local) variations affect each device within the same die differently. For

example, some devices on a die have smaller gate length whereas other devices on the

same die have a larger gate length.

Figure 2.1 Classification of various process variations

Variations/Deviations

Process Related Environmental Related

Systematic Non-Systematic Voltage Temperature

Die-to-die Within-die

Spatially Correlated Random

15

The within-die variations can be further classified as spatially correlated and

random variations. Spatially Correlated Variations are the kind of within-die variations

which exhibit similar characteristic for devices in small neighborhood in the die than

those placed far apart. However, random or independent variations are kind of within-die

variations which are statistically independent from other device variations. As an

illustration, RDF and LER are two major random variations. With the continuous process

scaling, the contributions of random component of variation is increasing.

2.3 RANDOM PROCESS VARIATIONS SOURCES

Process variations affect device geometry, which in turn deviates the performance

parameters of the design. This section discusses primary causes of the variability i.e

Random Dopant Fluctuations (RDF), Line Edge Roughness (LER), Oxide Thickness

Variation (OTV) and Mobility Fluctuation.

In DSM and nanometer regime, the number of dopants in the depletion region of a

transistor is rapidly diminishing and is therefore even countable. Due to discreteness of

dopant atoms, there is a statistical randomness in the number of dopants. The fluctuation

of the number of dopant atoms leads to variation of observed threshold voltage Vt for the

16

transistor. It is observed that the variation of threshold voltage follows a Gaussian

distribution and its standard deviation is inversely proportional to the square root of

active device area. Hence, increasing the size of the transistor helps in reducing the

variations but is not considered as a viable solution. RDF is regarded as the major source

of device variations in current nanometer technology node.

Line edge roughness is the local variation of the edge of the polysilicon gate along

its width. In technology nodes below 50nm, LER is quite noticeable making gate length

variation further more difficult (Croon at el., 2002). The causes of the increased LER

include the incoming photon count variation during exposure and the contrast of aerial

image, as well as the absorption rate, chemical reactivity, and the molecular composition

of resist (Ercken at el., 2004). In advanced technology nodes below 32nm, LER is

expected to become a significant source of variation due to its direct impact on the

standard deviation of threshold voltage.

Conventionally, silicon dioxide films are fabricated in thermal oxidation with

extremely tightly controlled process. However, in DSM technology node, the thickness of

oxide layer is countable number of atomic-level roughness of the oxide-silicon interface

layer (Asenov at el., 2002). The Si-SiO2 interface has the standard deviation of the order

of 2̊ A (Goodnick at el., 1985). The thickness of oxide film of 10˚A corresponds to

approximately five atomic layers of SiO2, while the thickness variation is 1-2 atomic

17

layers. Hence, the control of interface layer and oxide layer is becoming increasingly

difficult. This leads to increasing variation in device parameters like mobility and

threshold voltage. It significantly affects the gate tunneling current. Gate tunneling

current shows extreme sensitivity to oxide thickness. For a device with tox = 15̊ A, and

σtox = 1.8˚A, the current can be 5X larger than at the nominal conditions (Cassan at el.,

2000). The sources of mobility fluctuations are variation of the effective fields, fixed

oxide charges, doping, inversion layer, and the surface charge roughness. This leads to

variation of transistor’s drive current.

The growing number and complexity of variability mechanisms increase the

importance of methods for on-chip measurement. Both systematic and random process

variations need to be measured and categorized through silicon measurements.

Variability characterization requires collection of a very large amount of data which

demands for test structures that are inexpensive in terms of area and test time.

The emerging techniques of Design for Manufacturability (DFM) and statistical

design depend on the magnitude of process variations and the specific type of variation

(Agarwal et al., 2006b). However, innovations are required to handle random intra-die

variability in analog and large digital designs. The inter-die and spatially correlated intra-

die variations can be handled to a large extent using traditional techniques. As per the

ITRS (2006) projections, the threshold voltage variation will roughly double in 32nm

18

technology node compared to 65nm technology node. The delay variation at 65nm

technology node is 45% whereas it will be 57% in the 32nm technology node (Das, 2009).

It is important to quantify the magnitude of random variability. Incorporation of random

local process parameters in delay modeling is very important for accurate timing analysis.

In low power design, circuits are operated at different supply voltages (Liu and Svensson,

1993; Maheshwari and Burleson, 2004). Hence, supply voltage needs to be included in

the delay model. The switching activity inside the chip creates temperature islands. Thus,

temperature variation needs to be considered in the delay model. Ultimately, there is a

requirement for Process, Voltage and Temperature (PVT) aware delay model for accurate

timing prediction in digital circuit design.

As the technology reaches deep submicron or nanometer regime, the errors due

process variations becomes prominent. Some of the specific process variations typically

of concern for devices in integrated circuit design are hereby enumerated.

2.3.1 Device Geometry Variations

The first set of process variations of concern relate to the physical geometric structure of

MOSFET and other devices (resistors, capacitors) in the circuit. These typically include:

Film Thickness Variations: The gate oxide thickness is a critical but usually relatively

well controlled parameter. Variation tends to occur primarily from one wafer to another

with good across wafer and across die control. Other intermediate process thickness

19

variations (e.g., poly or spacer thickness) can impact channel length, but are rarely

directly modeled (Boning et al., 2000).

Lateral Dimension Variations: Lateral dimensions (length, width) typically arise due to

photolithography proximity effects (a systematic pattern dependency), mask, lens, or

photo system deviations (a repeated die dependent variation, though not directly a

function of the layout density or other layout parameters); or plasma etch dependencies

(which can have both wafer scale etch rate dependencies, as well as layout density, aspect

ratio, or other dependencies). MOSFETS are well known to be particularly sensitive to

effective channel length (and thus to poly gate length and spacer width), as well as gate

oxide thickness and to some degree the channel width. Of these, channel length variation

often is singled out for particular attention. This is due to the fact that such variations

have direct impact on device output current characteristics (Yu et al., 1996).

2.3.2 Device Material Parameter Variations

The device material variations are also prominent sources of variations. The variations

can be accounted for doping, deposition and anneal variations.

Doping Variations: Deviations arising due to dose, energy, angle, or other ion implant

dependencies can affect junction depth and doping profiles (and thus may also impact

effective channel length), as well as affect other electrical parameters such as threshold

voltage. Variations in thermal anneal and gate doping can also change the degree of gate

depletion in an active device, and cause variation in the effective gate oxide thickness.

20

Depending on the gate technology used, these deviations can lead to some loss in the

matching of NMOS versus PMOS devices even in the case where within wafer and

within die variation is very small.

Deposition and Annealing: Additional material parameter deviations are observed in

silicide formation, and in the grain structure of poly or metal lines. These variations may

depend on the deposition and anneal processes. These material parameter deviations can

contribute to appreciable contact and line resistance variation.

2.3.3 Device Electrical Parameter Variations

In many cases, the underlying geometry distribution is not characterized, but instead the

key electrical parameters are directly extracted and modeled for device electrical

parameter variations.

Vt variation: A key concern is threshold voltage (Vt) variation. Threshold voltage of a

MOSFET varies due to

(1) Changes in oxide thickness

(2) Substrate, polysilicon and implant impurity level

(3) Surface charge.

Process variation may increase or decrease the aspect ratio (W/L).Variation in W and L is

caused by lithographic process. These variation are not correlated because W is

21

determined in the field oxide step while L is defined in the polysilicon and source/drain

diffusion steps. While many elements of Vt may be due to oxide thickness or other

geometric deviations, additional sources of variation are often encountered. In particular,

mobile charge in the gate oxide can introduce a bias dependent variation; this is

sometimes approximated as being about 10% of the Vt of the smallest device in a given

technology. Another source of Vt variation that is just beginning to become important in

static random access memory (SRAM) (Izumikawa and Yamashina, 1996; König and

Glesner, 1994) and other circuits related to random dopant fluctuations. In particular, as

scaling of MOS devices continues into the deep submicron regime, concern has been

raised about the random placement and concentration fluctuations due to discrete location

of dopant atoms in the channel and source/drain regions.

Leakage Currents: Sub threshold leakage currents may vary substantially, and can be

affected by shallow trench isolation structure and stress (Boning. and Nassif, 2000).

2.4 INTERCONNECTS

The function of interconnects or wiring systems is to distribute clock and other

signals and to provide power/ground to and among the various circuits/systems functions

on the chip (Cong, 1999; Pandey et al., 2005). The performance, say time delay (Ismail et

al., 2000a; Wyatt, 1985) and power dissipation (Ismail et al., 1999a) of a high-speed chip

is highly dependent on interconnects, which connect different macro cells within a VLSI

22

chip (Ismail et al., 2002). To escape large delays, designers scale down global wire

dimensions more sluggishly as compared to the transistor dimensions (Sai-Halasz 1995;

Sylvester and Wu 2001). As technology advances, interconnects have turned out to be

more and more important than the transistor resource, and it is essential to use global

interconnects optimally. For high-density high-speed submicron-geometry chips, it is

mostly the interconnection rather than the device performance that determines the chip

performance.

Distribution of the clock and signal functions is accomplished on three types of

wiring (local, intermediate, and global) as shown in Figure 2.2. Interconnect, which

depends on its length, can be classified as local, semi-global and global (Rabaey 1996).

Local wiring, consisting of very thin lines, connects gates and transistors within an

execution unit or a functional block (such as embedded logic, cache memory, or address

adder) on the chip. Local wires usually span a few gates and occupy first and sometimes

second metal layers in a multi-level system. The length of a local interconnect wire

approximately scales with scaling of technology, as the increased packing density of the

devices make it possible to similarly reduce the wire lengths. Intermediate wiring

provides clock and signal distribution within a functional block with typical lengths up to

3–4 mm. Intermediate wires are wider and taller than local wires to provide lower

resistance signal/clock paths. Global wiring provides clock and signal distribution

between the functional blocks (El-Moursy and Friedman, 2004c; El-Moursy and

Friedman, 2005b; Huang et al., 2003; Ismail et al., 2001; Kurd et al., 2001; Lu et al.,

23

2001; Mekie et al., 2004; Mekie et al., 2006; Tam et al., 2000; Wann et al., 1983; Wood

et al., 2001; Yamaguchi et al., 2001) , and it delivers power/ground to all functions on a

chip (Benini et al., 1999). Global wires, which occupy the top one or two layers, are

longer than 4mm and can be as long as half of the chip perimeter (Pullela et al., 1993).

The length of global interconnect wires grow proportionally to the die size. The

length of semi-global interconnect behaves intermediately. The global interconnects are

much wider than local and semi-global interconnects. Thus resistance of global

interconnects is small and therefore their behavior resembles that of lossless transmission

lines.

At lower frequencies, interconnects cause no difficulty for signal propagation.

However, at higher frequencies, they cause severe signal degradation such as signal

delay, crosstalk, ringing, reflections and distortions which must be addressed by VLSI

designers (Mishra et al., 2010; Moll et al., 1998). It has been predicted since long times

that interconnect wiring delays rather than transistor logic delays would be the major

contributors to the overall global path delays for ICs fabricated by the deep submicron

CMOS processes (Bakoglu, 1990; Bakoglu, 1985). The increasing dominance of

interconnect coupled with the aggressive scaling in operating frequencies to increase chip

performance has fundamentally changed the nature of IC design. The impact of

interconnect, therefore, needs to be considered during all stages of design and at all levels

of design hierarchy. Even during process development, interconnect performance is an

important consideration in the design of the on-chip metal system.

24

Figure 2.2 Placement of various interconnects (Local, Intermediate and Global) in

Microprocessor Unit (MPU) and Application Specific Integrated Circuit (ASIC).

Source: ITRS.

25

With the upgrade of technology from micron to nanometer regime, technological,

device and interconnect challenges are closely examined by different researchers (Hiraki

et al., 1995). Propagation delay, crosstalk and power dissipation in global interconnects

have become a core research problem (Naeemi et al., 2003; Naeemi et al., 2004).

Therefore, a lot of work is being carried out to address these problems (Yamauchi and

Matsuzawa, 1996). Various models have been suggested in literature to analyze

interconnects (Ymeri et al., 2002; Zaage and Groteluschen, 1993; Zheng et al., 2000;

Zhou et al., 1994).

2.4.1 Modeling Interconnect as RC & RLC Circuits

During, early phase of VLSI design, the gate parasitic impedances had been much

larger than interconnect parasitic impedances, since size of gate (width and length) were

quite large. For example, 5µm was a typical minimum feature size in 1980. Therefore,

interconnect parasitic impedances were modeled as short circuit. With the conventional

technology that used a feature size of 1μm or above, interconnects resistance was

negligible as compared to the driver’s resistance. Thus, interconnect and loading gates

were modeled as a lumped loading capacitance. The interconnect delay was determined

by the driver resistance times the total loading capacitance (Mead and Rem, 1979; Mead

and Rem, 1982; Mohsen and Mead, 1979; Wong et al., 2000). However, with the scaling

of technology and increased chip sizes (submicron VLSI technology), the cross-sectional

area of interconnects had been scaled down while their lengths increased. Therefore, the

26

interconnect resistance was comparable to the driver resistance and the interconnect

capacitances became comparable to the gate parasitic capacitances, which forced the

designers to model interconnects as RC line (Penfield and Rubinstein, 1981). With the

introduction of RC models interconnection delay (Chatzigeorgiou et al., 2001), power

consumption and repeater insertions (Alpert, 1997; Alpert et al., 1998; Alpert et al.,

1999; Adler et al., 1998; Banerjee and Mehrotra, 2001a; Rubinstein et al., 1983) became

important in realizing high performance VLSI’s (Kaushik, 2007f). Almost every aspect

of the design and analysis was affected by new interconnect model (Jin et al., 2001;

Meindl et al., 2001; Yacoub et al., 1988).

With ever-growing length of interconnects and clock frequency on a chip, the

effects of interconnects cannot be restricted to RC models. The importance of on-chip

inductance is continuously increasing with faster on-chip rise times, wider wires, and the

introduction of new materials for low resistance interconnects (Deutsch et al., 1997;

Banerjee and Mehrotra, 2001b; Banerjee and Mehrotra, 2002; El-Moursy and Friedman,

2003a; El-Moursy and Friedman, 2004b; Ismail et al., 1999b; Ismail et al., 2000b). The

usage of higher operating frequencies increases the value of |jωL|, which plays a role in

interconnect delay calculation and its design construction (Havemann and Hutchby,

2001; Kamon et al., 1994).

27

Wide wires are frequently encountered in clock distribution networks, power and

ground lines, and other global interconnects such as data bus and control lines in upper

metal layers (Nekili and Savaria, 1993). These wires are low resistive lines that can

exhibit significant inductive effects (El-Moursy and Friedman, 2005a; Eo et al., 2002a;

Eo et al., 2002b; Kopcsay et al., 2002; Krauter et al., 1995; Krauter et al., 1998). Due to

presence of these inductive effects, the new generation VLSI designers have been forced

to model interconnects as RLC lines (Agarwal et al., 2004; Cao et al., 2000; Cases and

Quinn, 1980; Coulibaly and Kadim, 2004; Kahng and Muddu, 1997)

2.4.2 Lumped and Distributed Models

Depending on the operating frequency, signal rise times, and nature of its

structure, the analytical models can be broadly categorized as lumped and distributed. At

lower frequencies, interconnect can be modeled as lumped RC or RLC circuits

(Odabasioglu et al., 1997; Odabasioglu et al., 1998). RC circuit responses are monotonic

in nature which fails to account for ringing in signal waveforms (Qian et al., 1994;

Ousterhout, 1984). In order to account for ringing in signal waveforms, RLC circuit

models are required (Achar and Nakhla, 2001).

At high signal-speeds, electrical length of interconnects becomes a significant

fraction of the operating wavelength, giving rise to signal distortion that do not exist at

lower frequencies. The conventional lumped impedance interconnect models are

28

inadequate in such a situation as they do not adequately exhibit the distortions. The

transmission line models based on quasi-transverse electromagnetic mode (TEM)

assumptions yield better results. The TEM approximation represents the ideal case, where

both electric (E) and magnetic (H) fields are perpendicular to the direction of propagation

and it is valid under the condition that the line cross section is much smaller than the

wavelength. However, the in-homogeneities in practical wiring configurations give rise to

E or H fields in the direction of propagation. If the line cross section or the extent of these

non-uniformities are a small fraction of the wavelength in the frequency range of interest,

the solution of Maxwell’s equations are given by the so-called quasi-TEM modes and are

characterized by distributed resistance, inductance, capacitance and conductance per unit

length parameters (Paul, 1994). In realistic situations, due to complex interconnect

geometries and varying cross-sectional areas, interconnects may need to be modeled as

non-uniform lines. In this case, the per unit length impedance parameters are functions of

the distance, along the length of transmission line (Boulejfen et al., 2000; Griffith and

Nakhla, 1990; Manney et al., 1992; Palusinski and Lee 1989).

In deep submicron technology, lumped models are no longer capable of satisfying

the accuracy requirements and cannot exactly locate the coupling elements in the

equivalent circuit of the coupled line. It is well accepted that simulations of a distributed

RC model of interconnect matches more accurately the actual behavior in comparison to

lumped RC model (Gupta et al., 1997; Rabaey, 1996). In similar fashion, a distributed

RLC model outperforms the lumped RLC model in terms of modeling accurately the

29

behavior of a line. A distributed RLC model of interconnect, known as the transmission

line model, becomes the most accurate approximation of the actual behavior (Rabaey,

1996). The transmission line analogy for interconnect considers the signal propagation to

be a wave propagation over the interconnect medium. This is in contrast to the distributed

RC model, where the signal diffuses from source to the destination governed by the

diffusion equation. In the wave mode, a signal propagates by alternatively transferring

energy from the electric to magnetic fields, or equivalently from capacitive to the

inductive nodes. Interconnect models must incorporate distributed self and mutual

inductance (Priore, 1993) to accurately estimate interconnect time delay, power

dissipation, crosstalk and other parameters of significance (He et al., 1999; He et al.,

2000).

The evolution of various models with time is shown in Figure 2.3. It is assumed

that leakage conductance ‘g’ equals 0, which is true for most insulating materials such as

SiO2, sapphire etc. Dealing with inductance requires efficient extraction methods

(Kaushik et al., 2007d; Kaushik et al., 2007e; Kaushik et al., 2008; Kaushik et al., 2009;

Rosa, 1908; Ruehli, 1972).

Presence of inductance also increases the processing time of the computer-aided

design tools. Usually the interconnect circuits extracted from layouts contain a large

number of nodes that make the simulation highly CPU intensive. Distributed coupled

30

RLC models become necessary even for the early design stages, and is suggested in many

papers (Branin Jr, 1967; Cullum et al., 2000; Djordjevic et al., 1987; Dounavis et al.,

1999; Dounavis et al., 2000; Dounavis et al., 2003; Sim et al., 2003). The distributed π,

3π, and 4π models are used for representing distributed RLC interconnect.

(a)

(b)

Figure 2.3 Development of interconnect models (a) RC model; (b) RLC model.

z

rΔz rΔz rΔz

cΔz cΔz cΔz

ℓ lΔz lΔz lΔz

Rtot = rℓ, Ltot=lℓ and Ctot=cℓ

cΔz cΔz cΔz

rΔz rΔz

rΔz ℓ

z

Rtot = rℓ and Ctot=cℓ

31

Cfr1

Cfr2

Cov2

Cfr3

Cov

Cfr5

Clat

Cfr4

Figure 2.4 shows a typical interconnect geometry in a custom design layout (Liu et

al., 2000). Interconnects on adjacent layers are orthogonal to each other, which is a

special case of the general configuration. The top interconnect has larger width and

smaller length compared to lower interconnects. The capacitance at any metal line or

node consists of the following three components:

1) Overlap capacitance Cov due to the overlap between two interconnects in different

metal layers;

2) Lateral capacitance Clat between two intra-layers interconnects;

3) Fringe capacitance Cfr between two interconnects in different metal layers; this fringe

capacitance is between the sidewall of one interconnect and the top (or bottom) of

another interconnects in a different layer (Pucknell. and Eshraghian 1988).

Figure 2.4 Schematic of a typical interconnect structure.

32

2.4.3 Cross-talk Noise

The recent trend in the VLSI industry toward miniature designs, low power consumption

(Khellah and Elmasry, 1999; Nakagome et al., 1993), and increased integration of analog

circuits (Kumar et al., 2005) with digital blocks (Kleveland et al., 2002) has made the

signal integrity analysis a challenging task. The quest for high-speed applications has

highlighted the previously negligible effects of interconnects, such as ringing, signal

delay, distortion, reflections, and crosstalk (Hao and Lei, 2005; Massoud et al., 1998).

Crosstalk refers to the interaction between signals that are propagating on various

lines in the system (Chaudhary et al., 1993; Coulibaly and Kadim, 2005). Crosstalk is

mainly due to the dense wiring required by compact and high-performance systems

(Sinha et al., 2002). High-density and closely laid interconnects result in electromagnetic

coupling between signal lines (Shin et al., 2004). The active signal energy is coupled to

the quiet line through both mutual capacitance and inductances, resulting in noise

voltage–currents (Venkatesan et al.,2003a; Venkatesan et al.,2003b) . This may lead to

inadvertent switching and system malfunctioning. Crosstalk is a major constraint while

routing in high-speed designs. By its very nature, crosstalk analysis involves systems of

two or more conductors. It can affect timing, causing a delay failure, it can increase the

power consumption due to glitches, and it can cause functional failure because of the

signal deviation (Rossello and Segura, 2004; Rossello and Segura, 2006). Interconnect

cross capacitance noise refers to the charge injected in quiet nets, victims, by switching

on neighboring nets, aggressors, through the capacitance between them (cross

capacitance). This is perceived to be one of the significant sources of noise in current

33

technologies. Cross capacitance can also affect delay and slew depending on whether the

aggressor signals are switching in the same or in the opposite direction to the victim net.

Traditionally, coupling capacitance (cross capacitance) and recently mutual

inductance parasitic are held responsible for crosstalk noise. When signal switching

causes transient current to flow through the loop formed by the signal wire and current

return path, a changing magnetic field is created and the mutual inductance noise occurs

(Davis and Meindl, 2000a; Davis and Meindl, 2000b; Lin and Kuh, 1990). A voltage on a

quiet line that is in or near this loop is induced. For several signals in a bus switching

simultaneously, these noise sources can be cumulative. Cross capacitance is a short range

phenomenon; however, mutual inductance can be a long-range phenomenon, which is

worse in the presence of wide busses. This noise is very significant in current

technologies due to faster switching speeds and wider, synchronous bus structures. The

analysis of inductive effects is quite complex and highly dependent on layout.

Analytical expressions are preferred for analyzing interconnects noise, as

simulation is always expensive and ineffective to use with designs containing millions of

transistors and wires. However, analytical expressions are not sufficiently accurate and

do not consider all interconnect and driver parameters. Different design stages have

different requirements for the accuracy of modeling interconnects crosstalk noise effects.

Many studies have been conducted to model metal lines and crosstalk effects. For the

34

purpose of the timing verification, ideal ground-based RC or RLC-distributed-circuit

models for interconnect lines have been widely used (Kahng and Muddu, 1996; Sakurai,

1993; Chen et al., 2005; Cheng et al., 1999). The conventional ideal RC or RLC

transmission line model of interconnects (Kuznetsov and Schutt-Aine, 1996), without

considering the detailed physical phenomena, are not accurate enough to verify the

timing of high performance VLSI circuits (Jin et al., 2000). Most research efforts have

been focused on developing formulas for the peak noise pulse amplitude. The pulse width

of the crosstalk noise and the peak noise occurring time, which are of similar importance

for circuit performance as the peak amplitude, should also be considered. Since digital

gates are inherently low-pass filters, they can filter out noise pulses with high amplitude

provided that the noise pulse width is sufficiently narrow.

Most of the noise models and avoidance techniques consider only capacitive

coupling (Cong and Leung, 1993; Cong et al., 1993; Cong et al., 1995; Cong and He,

1995; Cong et al., 1996; Cong et al., 1997a; Cong et al., 1997b; Sakurai, 1993; Shepard.

and Narayanan 1996; Sylvester and Shepard 2001; Vittal and Marek-Sadowska, 1997;

Vittal et al., 1999). Compact expressions for worst-case time delay and crosstalk of

coupled; distributed resistance capacitance RC lines are rigorously derived by Sakurai

(1993). However, at current operating frequencies inductive crosstalk effects can be

substantial and therefore they should be included for complete coupling noise analysis

(Murugan et al., 2004a; Murugan et al., 2004b; Murgan et al., 2005a; Murgan et al.,

2005b).

35

Crosstalk noise is the main source of noise in static CMOS designs (Nagaraj et

al., 2001; Narasimha et al., 2006; Ertugrul 2006; Tang and Friedman, 1999). The

crosstalk noise increases the signal settling time. Among several factors that affect the

crosstalk noise, key factors include aggressor/victim drive strengths, parasitic RLC of the

interconnect network, aggressor signal switching times, transistor device models and

victim receiver noise margins. Unless crosstalk noise occurs on asynchronous signals

such as reset clear signals or on clock signals, crosstalk noise has to be strong enough to

propagate through logic before it could be detected. The glitch in the victim net from

aggressor net causes the victim net to take longer time to settle to its final value. In static

combinational logic, crosstalk increases the delay across a net; in dynamic logic crosstalk

can cause the state of a node to flip, causing a permanent error. The crosstalk-induced

delay is in fact the crosstalk-induced glitch plus the original response of the affected

victim line. In simple terms the amplitude of the noise induced in a victim line scales

with Cc/Ctot. Crosstalk noise verification can be classified into four major steps (Nagaraj

et al., 2001) i.e Coupled Network Extraction; Victim Aggressor Selection; Cluster

Network Generation; Crosstalk Noise Computation.

Modeling static noise has been a rigorously studied topic and various static-noise

models have been proposed time to time that exhibit a high degree of accuracy (Sakurai,

1993; Vittal et al., 1999; Devgan, 1997; Acar et al.¸ 1999; Ding et al., 2003; Chen and

Marek, 2002; Yin and He, 2001). However, accurate estimation of crosstalk-induced

36

delay remains a challenging task. Typically, dynamic delay is modeled by replacing the

coupling capacitance between two wires by an equivalent ground capacitance based on

the Miller effect. A few other approaches model dynamic delay by the superposition of a

static-noise waveform on the nominal switching waveform of the isolated victim (Sato et

al., 2003; Bhardwaj et al., 2002). These superposition-based approaches require accurate

modeling of static noise and nominal victim waveforms. These waveforms must then be

properly aligned to obtain worst case delay change.

Crosstalk reduction is one of the primary research areas these days. Several methods

such as repeater insertion (Lillis et al., 1996), shield line insertion between two adjacent

wires (Lepak et al., 2001), optimal spacing between signal lines (Tseng et al., 1998) and

lastly the most superior bus encoding method (Lampropoulos et al., 2004; Stan and

Burleson, 1995) are being employed for crosstalk reduction.

2.4.4 Interconnect Objectives

The International Technology Roadmap for Semiconductors (ITRS) enumerates the list

of targets that are organized and assembled as a mutual effort by members within

semiconductor industry, academicians, researchers, consumers etc. Target implies a

simple aim for an objective, whereas, projection implies the ability to predict a particular

goal or value. Basically, the ITRS is a wish list for the semiconductor industry with

evolving targets. In particular, there are copper interconnect targets made for high

performance microprocessors (MPUs) (Dobberpuhl, et al., 1992), Field Programmable

37

Gate Arrays (FPGAs) (Pereira et al., 2005) and Application Specific Integrated Circuits

(ASICs) on which currently the research is targeted. Technology nodes or generations are

given in terms of their year or critical dimension (CD). The year indicates the time at

which the CD will be used for mass production. The CD is defined as width of the first

metal layer (M1). To clarify, a wire-pitch is the lateral spacing given for the width of the

wire and the spacing needed between itself and its neighboring wire on one side. A wire-

pitch may also be referred to as the center-to-center spacing between adjacent wires. The

physical dimensions (width and height) of the interconnect would scale by a factor of 0.7.

In other words, every successive technology generation is 70% the physical size of the

previous generation. While the targets are not tough and rapid numbers, the goal is to

guide industry as it scales well into the 11nm node by the year 2022. In Table 2.1, seven

technology nodes are presented comparing M1 (Metal level 1) physical line dimensions

noted in the ITRS and compared to data published by Intel (Yang et al., 1998; Tyagi et

al., 2000; Jan et al., 2003; Bai et al., 2005; Mistry et al., 2007; Brain et al., 2009; Lopez,

2009). Since 22nm is still to be achieved/commercialized by Intel, the projected

dimensions have been formed for comparison using 32nm data and the scaling factor of

0.7. Noticeably, the roadmap projections are much more aggressive. In fact, since 2007

the cross-sectional area of the M1 Intel interconnects are more than twice than ITRS

projections.

A simple explanation of this discrepancy between the ITRS and industry is the

loose definition of a technology node. According to (Havemann, R.H. and Hutchby, J.A.,

2001), the technology node once was a measure of the printed gate length of the

38

transistor. Today, to be at any given technology node is to meet a set of criteria described

by the ITRS for the transistor (i.e., transistor drive current, transistor leakage current and

power envelope), circuits, memories, semiconductor materials, interconnects etc.

Table 2.1 Comparison of ITRS M1 Physical Line Dimension Targets to Intel Data

Technology Node Width [nm] Height [nm] Cross-section Area

Ratio: Intel/ ITRS Year 1/2 Pitch [nm] ITRS Intel ITRS Intel

1999 180 230 253 322 480 1.6

2001 130 150 175 240 280 1.4

2004 90 107 107 182 150 0.8

2007 65 68 106 116 170 2.3

2010 45 45 80 81 144 3.2

2013 32 32 56 61 95 2.7

2016 22 22 39* 44 67* 2.7*

*Intel projection using a scaling factor of 0.7 and 32nm dimensions.

2.5 PROCESS VARIATIONS IN INTERCONNECTS

The task of scaling critical dimensions requires a parallel effort to control and/or

tolerate process variations because they can significantly impact the overall chip

performance, power, yield and cost (ITRS). Of primary interest is the process of

39

increasing wire delay by scaling Cu interconnect (Steinhogl et al., 2004; Schindler et al.,

2003a; Schindler et al., 2004; Steinhogl et al., 2005; Kitada et al., 2007; Sun et al., 2008;

Steinhogl et al., 2002; Lopez, 2009; Plombon et al., 2006; Chen et al., 2006;

Steinlesberger et al., 2004; Alers et al., 2006; Marom and Eizenberg, 2006; Shimada et

al., 2006; Besling et al., 2004; Li et al., 2004; Engelhardt et al., 2004; Guillaumond et al.,

2003; Lakshminarayanan et al., 2003; Sarvari and Meindl, 2003; Traving et al., 2003;

Schindler et al., 2003a; Schindler et al., 2003b; Steinhogl et al., 2005; Steinlesberger et

al., 2002a; Steinlesberger et al., 2002b; Boning, 2003; Mehrotra and Boning, 2001;

Barnat and Lu, 2001; Chen and Gardner, 1998). As technology continues to scale well

into the sub-100 nm regime, size effects play a significant role in interconnect

performance ( Huang and Chen, 2004; Steinhogl et al., 2004; Schindler et al., 2003;

Schindler et al., 2004; Lopez et al., 2007; Lopez, 2009; Steinhoegl et al., 2005; Kitada et

al., 2007; Sun et al., 2008; Steinhogl et al., 2002; Plombon et al., 2006; Chen et al.,

2006; Steinlesberger et al., 2004; Alers et al., 2006; Shimada et al., 2006; Besling et al.,

2004; Engelhardt et al., 2004; Guillaumond et al., 2003; Lakshminarayanan et al., 2003;

Sarvari and Meindl, 2003; Traving et al., 2003; Schindler et al., 2003a; Schindler et al.,

2003b; Steinhogl et al., 2005; Boning, 2003; Mehrotra and Boning, 2001; Barnat and Lu,

2001; Chen and Gardner, 1998; Levenson, 1989). Noticeable performance degradation

occurs especially as the line-width dimensions approach the mean free path of copper

(λCu =40 nm). Moreover, variations in the line-width and line-height become increasingly

difficult to control.

40

2.5.1 Size Effects and Temperature Independence

It is well known that significant performance degradation occurs especially as the

interconnect width dimensions approach the mean free path of copper (λCu=40 nm). The

root cause of the degradation is size effects. A size effect can be defined as a physical

barrier that exists regardless of external environmental factors such as temperature. As

interconnect continues to scale well below the λCu, interaction of the electron with the

sidewalls and grain boundaries of interconnect becomes more prominent. Although the

overall effective resistivity can be lowered by decreasing the temperature of a wire, size

effects still increase the effective resistivity as the dimensions of the wire come close to

λCu. While the chip cooling is advantageous to mitigate effective resistivity with size

effects, but ironically the cooling techniques are still limited to air cooling to reduce cost.

2.5.2 Process Variations in Interconnects

In physical terms interconnects are layers of patterned metal on or within dielectric that is

usually an oxide as seen in Figure 2.5 (Lopez, 2009). Temperature, lateral dimensions

and vertical dimension impact the electrical property of a metal line. Lateral dimensions

signify the x- and y-component of dimension of a wire (Figure 2.5), which can be length

or width depending on one's orientation. Vertical dimension refers directly to the

thickness or height of interconnect as seen in Figure 2.5 along the z-axis.

41

Figure 2.5 Orientation of the copper interconnect in oxide.

At the electrical level, grain boundary structures and interconnect sidewalls that serve as

copper diffusion barriers varies from one process to another (Steinhogl et al., 2004;

Steinhoegl et al., 2005; Kitada et al., 2007; Chen et al., 2006; Shimada et al., 2006;

Besling et al., 2004; Guillaumond et al., 2003; Lopez, 2009). Since the metallic grain

sizes and interconnect sidewalls are physically constrained by the dimensions of

interconnect (Schindler et al., 2003; Schindler et al., 2004), electrical variability crops up

from physical variability seen along the dimensions of the metallic wire.

Parametric variation describes the effects of fabrication variation (Duvall 2000)

and is categorized into two groups: die-to-die (D2D) and within-die (WID) (Figure 2.6).

Parametric variation depicts the physical variations resulting from various fabrication

X

Z

Y

42

processes. Parametric variations directly impacts the electrical performance of the

interconnect. D2D variations arising from lot-to-lot, wafer-to-wafer and some from

within-wafer variations (Bowman et al., 2002) come from process fluctuations in

temperature (Nassif, 2001), chemical mechanical polishing (CMP) (Boning, 2003) and

wafer placement. Bowman et al., (2002) observed that within-wafer variations contribute

to both D2D and WID fluctuations. For example, resist thickness across a wafer is

random from wafer to wafer, but is deterministic within a wafer. As a result, thickness

variation is deterministic across the wafer; however, when comparing resist thickness of a

die from the center of the wafer to a die from the edge of the same wafer, resist thickness

differs. Looking WID, resist thickness varies from one edge of the chip to the other, but

varies little in thickness when examining a local area within the die (Lopez, 2009).

There are two kinds of WID variation: systematic (WID-S) and random (WID-R).

Smooth variations are referred to as systematic WID variations. As an example, stepper

lens aberrations in lithography create a smooth nonlinear pattern variation in printed line-

widths across the die (Yu et al., 1996), while the imperfections in the mechanics of the

steppers create deviations in the pattern from die to die. Random variations, like doping

atom placement in a device channel (Narasimhulu et al., 2003), are referred to as random

WID variations. Some WID variations can have both a systematic and random

component. Duvall (2000) showed that process conditions can vary randomly from die to

die, but varies deterministically within-die.

43

Figure 2.6 Hierarchy of variation for interconnects

2.5.3 Sources of Interconnect Process Variations

The sources of electrical variability within a design are of primary concern to a

semiconductor company when fabricating high performance VLSI chips. Ultimately,

these sources of variation affect the overall yield and cost of an integrated circuit. The

main steps in chip fabrication that contributes to variability are photolithography,

metallization, rapid thermal process (RTP) and chemical mechanical polishing (CMP).

These are all steps are followed in a copper damascene process (Campbell 2001). For

example, creating damascene copper interconnects begins with photolithography. Once a

pattern is transferred to the resist, the resist is used as a mask so that trenches can be

etched into the oxide layer below. The resist is then cleared, and metallization is

Electrical Variations

Physical Variations

Die-to-Die Within Die

Systematic Random

44

performed by depositing a thin barrier layer of TaN prior to the Cu deposition. To

encourage reflow and grain enlargement, the wafer undergoes RTP. Finally, CMP

polishes away the overburden, completing the damascene process.

2.5.3.1 Photolithography

Photolithography (or "optical lithography") is a process used in microfabrication to

selectively remove parts of a thin film or the bulk of a substrate. It uses light to transfer a

geometric pattern from a photo mask to a light-sensitive chemical "photoresist", or

simply "resist," on the substrate. A series of chemical treatments then either engraves the

exposure pattern into, or enables deposition of a new material in the desired pattern upon,

the material underneath the photo resist. In complex integrated circuits, for example a

modern CMOS wafer will go through the photolithographic cycle up to 50 times.

Photolithography shares some fundamental principles with photography in that

the pattern in the etching resist is created by exposing it to light, either directly (without

using a mask) or with a projected image using an optical mask. This procedure is

comparable to a high precision version of the method used to make printed circuit boards.

Subsequent stages in the process have more in common with etching than with

lithographic printing. It is used because it can create extremely small patterns (down to a

few tens of nanometers in size), it affords exact control over the shape and size of the

objects it creates, and because it can create patterns over an entire surface cost-

effectively. Its main disadvantages are that it requires a flat substrate to start with, it is not

45

very effective at creating shapes that are not flat, and it can require extremely clean

operating conditions.

Historically, photolithography has used UV light from gas-discharge lamps using

mercury, sometimes in combination with noble gases such as xenon. These lamps

produce light across a broad spectrum with several strong peaks in the ultraviolet range.

This spectrum is filtered to select a single spectral line. From the early 1960’s through the

mid-1980’s, Hg lamps had been used in lithography for their spectral lines at 436 nm ("g-

line"), 405 nm ("h-line") and 365 nm ("i-line"). However, with the semiconductor

industry’s need for both higher resolution (to produce denser and faster chips) and higher

throughput (for lower costs), the lamp-based lithography tools were no longer able to

meet the industry’s requirements.

Interconnects are simply patterned metal within a dielectric. The pattern is

generated using photolithography. Since 2008, M1 and intermediate wiring levels (i.e.,

long local wires) share the same line-widths, aspect ratios, and barrier/cladding

thicknesses (ITRS). This implies that the variability seen at M1 will also be seen at

intermediate wiring levels. To clarify this point, interconnect critical dimension (CD)

variation (M1 to intermediate level line-widths) is affected by photolithography. Stepper

lens lithography contributes to both D2D and WID variations. Particularly, optical

proximity correction has been used in industry to compensate for optical diffraction and

distortion of wire features on-chip (Kahng and Pati, 1999). Consequently, stepper lens

46

aberrations create a systematic nonlinear pattern variation in printed line-widths across

the die, while the imperfections in the mechanics of the steppers create deviations in the

pattern from die-to-die (Duvall 2000, Lopez, 2009).

Effective line-widths (ω0) are projected to exhibit a ±3σω010% total CD variation

for M1 to intermediate metal levels for all generations (ITRS), where CD is the ITRS

Microprocessor Unit (MPU) half-pitch. Aside from ω0 variation, at the physical level,

fabricated interconnect lines are not perfectly straight with clean line-edges. The

roughness seen along the length of wire or line-edge roughness (LER) results in the

degradation of performance of interconnects. In recent past, Steinhogl et al., (2004) and

Leunissen et al., (2006) observed the impact of LER on effective resistivity (ρeff). They

noted that wires with ω0=40 nm can have LER variations as great as 15 nm, resulting in

widths from 25 nm to 55 nm along the length of a wire. Improving the photolithography

technology from i-line to deep UV showed a reduction in LER, where an effective line-

width of 60nm with an LER of 6nm is illustrated (Tokei et al., 2009).

Steinhogl et al. (2004) showed that LER contributes greatly to wire resistivity

especially if the width variation is equal or greater than 50% of the line-width.

Furthermore, it was determined that LER may no longer be neglected for line-widths

below 50nm with LER amplitude exceeding 15nm. The amount of LER depends on the

photolithographic and resist technology used (Steinhogl et al., 2004; Leunissen et al.,

47

2005). Thus, LER is understood to be an inherent and fixed-constant by-product that is

superimposed on the metal line-width, which makes it width independent.

2.5.3.2 Metallization

Metallization is shaped with processing challenges. The most common form of Cu

metallization (Hara et al., 2004; Kapur et al., 2001) is electrochemical plating (ECP).

Other forms include filament evaporation, e-beam evaporation and sputter deposition. To

prevent Cu diffusion into the surrounding oxide, a TiN, TaN, and/or Ta barrier layer is

applied prior to ECP. Because the barrier layer is electrically conductive, Acar et al.

(1999) considered an effective resistivity for Cu interconnects. Later Traving et al. (2003)

explained how the Ta crystal orientation impacts the effective resistivity. Through careful

processing, the resistivity of the barrier layer can be reduced, improving electrical

conduction. Van et al., (2007) fabricated and electrically tested 20nm damascene Cu

lines. This work compares the challenges of barrier layer application via physical vapor

deposition (PVD) and atomic layer deposition (ALD). Process challenges included partial

filling and pinching. Van et al., (2007) also attributed variability in electrical

measurement to a large variation in grain structure. While much work has been done in

barrier deposition, others are trying to increase grain size. Alers et al. (2006), used a

novel plating chemistry to enlarge grain size to minimize the impact of grain boundary

scattering. Sun et al. (2008), using physical metrology indicated that grain growth is

strongly influenced by the barrier layer. In summary, metallization presents a variety of

processing challenges. Without careful processing, variations in barrier layer deposition

48

and grain structure can have a profound impact on the effective resistivity of the copper

interconnect.

2.5.3.3 Rapid Thermal Process

A widely used type of annealing is called rapid thermal process (RTP). Annealing was

originally used to repair the damaged silicon lattice caused by ion implantation by

heating the wafer between 800oC and 1000oC (Jaeger 2002). Today, RTP describes a

family of single-wafer hot processes that have been developed to minimize the thermal

budget of a process by reducing the time at temperature in addition to, or instead of,

reducing the temperature (Campbell 2001). RTP provides good uniformity and

reproducibility. As a result, RTP impacts wafer-to- wafer variation; however, heating and

cooling the wafer uniformly to prevent warping, maintaining a uniform temperature

during the process and measuring the wafer temperature are challenges still faced by

process engineers (Campbell 2001). RTP is attractive for producing larger metallic grains

in copper interconnects to reduce resistivity (Jiang et al., 2001a; Jiang et al., 2001b;

Steinlesberger et al., 2003). This process is also referred to as rapid thermal annealing

(RTA). However, as interconnects are fabricated with line-widths near the mean free path

of an electron in Cu, the line-width imposes a limit on the effectiveness of RTP on grain

size growth (Jiang et al., 2001; Steinlesberger et al., 2003; Steinlesberger et al., 2002;

Hara et al., 2004). Due to physical limitations, variation in grain structure can be

expected. In short, the lateral wire dimensions at the nanometer regime play an important

role in affecting the effective resistivity of interconnect.

49

2.5.3.4 Chemical Mechanical Polishing

Chemical mechanical polishing (CMP) is a unit process that contributes to height

variation for on-chip interconnects. Extensive work has been done on CMP (Boning

2003), which is a known contributor to resistive variability (Park et al., 1999). Several

studies show that the removal rate is higher at the wafer edges than at the center and that

over-polishing is needed for complete copper removal (Fayolle and Romagna 1997).

Consequently, because copper metal is relatively softer than silicon oxide, metal dishing

can occur. Metal dishing is defined as the recessed height of a copper line compared to

the neighboring oxide (Park et al., 1999). Wider global wires typically experience more

dishing than narrower local wires. This phenomenon is also exacerbated by the pattern

density that also contributes to oxide erosion (Park et al., 1999; Fayolle and Romagna

1997; Shih et al., 2001). Oxide erosion is known as the difference between the original

oxide height and the post-polish oxide height (Park et al., 1999). It also has been shown

that over design can occur if pattern density is not considered in an ASIC design flow

(Zarkesh et al., 2003).

Lakshminarayanan et al. (2003) showed the effects of the underlying metal layers

on the resistance of a wire created from a Damascene copper CMP process. Their

research shows how a wire over an area with no underlying metal can have a higher

resistance consequence of the upper metal layer conforming to that of its underlying

50

layer. In short, wire resistance turns out to be a function of the underlying density,

exhibiting a near linear dependence of the Metal 2 layer on the Metal 1 layer

(Lakshminarayanan et al., 2003). Considering a long wire across a chip, the underlying

layer will induce a variation in resistance in addition to any dishing or erosion that may

occur. Consequently, the underlying metal layers exhibiting dishing and erosion further

contribute to height variability (Lakshminarayanan et al., 2003).

Another generally overlooked component of CMP is the thermal contribution to

the removal rate of copper and slurry chemistry. Sorooshian et al. ( 2004) reported that

increasing the polishing temperature increases the removal rate of copper, exacerbating

dishing and erosion. It has been demonstrated that the impact of pad temperature can be

quantified into a single defined value in terms of activation energy (Sorooshian et al.,

2004). If the thermal gradient across a wafer is not kept uniform, removal rates during

CMP could be considerably different across the wafer than when pattern density alone is

considered.

To overcome the effects of CMP, early steps were taken by examining different

pattern densities (Park et al., 1999; Fayolle and Romagna 1997; Shih et al., 2001),

optimizing the CMP process by reducing the chemical effect (Romagna and Fayolle

1997) and creating a completely abrasive-free process (AFP) (Kondo et al., 2000;

Yamaguchi et al., 2000). However, because of the underlying metal layers, extending

51

metal layout rules for improved manufacturability and placing the responsibility of

dishing and erosion on the designer rather than on the process engineer have been

proposed (Lakshminarayanan et al., 2003). In addition, careful attention should be paid to

the thermal contributions of pad temperature (Sorooshian et al., 2004).

Acar at al. (1999), observed that dishing is expected to change no more than 10%

of the nominal conductor height h0. Yamaguchi et al. (2009), showed that both dry-

etching of the low-k layer and CMP intensify LER and wedges. In modeling the electrical

performance of a copper interconnect with process variations from an optimized CMP

process, pattern density, the effects of underlying metal density, and the resulting

physical dimensions effects on resistivity must be considered.

2.6 INTERCONNECT CHARACTERIZATION

Due to the process variation, interconnect technology parameters (ITP) are varying

substantially. For simplicity, the researchers consider variations in metal width (Wi),

metal thickness (T), and interlayer dielectric (ILD) thickness (H). The typical distribution

of interconnect technology parameters can be observed for permittivity, inter level

dielectric thickness, metal height and metal width (Boning and Nassif 2000). The

variation is especially large in the ILD (Inter Level Dielectric) thickness and metal line

width. Their variations have a definite impact to the total line capacitance and interline

52

coupling capacitance and result in variation of the signal delay and crosstalk noise. The

effect of the process variation should be modeled, because its impact on the signal delay

and crosstalk is substantial. The conventional skew corner worst-case modeling is too

conservative (Edahiro, 1993; Boning and Nassif 2000).

2.6.1 On Chip Interconnect variations

The source for on chip variations (OCV) is related to variation in interconnects height

and width, resulting in variation in both resistance and capacitance. Since the delays

attributed to interconnect are becoming more dominant as geometries shrink, particular

attention should be paid to accurate modeling of interconnect variations. In advanced

interconnect processes, which could involve use of multiple dielectrics, use of different

metallization on different layers could result in significant variations. Depending on

material properties of low-k dielectrics, “dishing” could be observed on metal lines

spaced wide apart (Figure 2.7) (Verma et al., 2010a; Verma et al., 2010b; Verma et al.,

2010c). Erosion is the other mechanism and is a function of line space and density. Two

additional sources of variation are the Chemical Mechanical Planarization (CMP) process

and proximity effects in the photolithography and etch processes. Variation in the CMP

process results from the difference of hardness of the interconnect material and that of the

dielectric. Ideally the CMP process will remove the unwanted Copper, leaving only lines

and via. The photolithography and etch proximity effects are shown in micro loading

effects as the etch process step tends to over-etch isolated lines.

53

Figure 2.7 CMP induced OCV on interconnects

Diffraction effects and local scattering in photolithography may tend to over expose

densely spaced lines and under expose isolated lines. Tiling and metal slotting have been

added as design rule requirements to mitigate these effects by minimizing the density

gradient. Different tiling algorithms will give varying results, but the smaller the density

gradient, the smaller the variations that will be seen on the die (Jarrar and Taylor 2006).

Process variations impact signal-integrity issues such as crosstalk noise, coupling

induced delay, electro migration, IR drop, etc. When process variations impact these

parameters significantly, manufactured products may experience unexpected reliability

failures. Therefore, it is extremely important to include variability during reliability

analysis and optimization—this will minimize yield loss due to reliability failures caused

by process variation and ensure a robust design across the entire process spread.

54

The impact of interconnect variations on signal-integrity issues, such as crosstalk

noise and coupling-induced-delay degradation (i.e., dynamic delay) is one of actively

researched area. Accurate statistical modeling of interconnect coupling requires accurate

nominal models for crosstalk noise and coupling-induced-delay change caused by the

simultaneous switching of aggressor and victim wires.

Static noise is defined as the noise pulse induced on a quiet victim net due to the

switching of neighboring aggressors (Nakhla et al., 2004; Nakhla et al., 2006). Agarwal

et al. (2006a) discussed the impact of process variation on static crosstalk noise in

coupled RC interconnects. Static noise can result in functional failures due to false

switching of the victim line. For the first order, the magnitude of static noise is directly

proportional to the ratio of coupling capacitance to total ground capacitance. This causes

the noise magnitude to be very sensitive to variations in metal width and inter-wire

spacing, and small variations in these dimensions can result in large fluctuations in the

noise peak (Kaushik et al., 2006; Kaushik et al., 2007a; Kaushik et al., 2007b). To prove

this fact, consider a simple coupled RC-interconnect test case. The width (Wi), thickness

(T), spacing (S), and ILD layer thickness (H) for the interconnect lines are randomly

chosen to be 0.4, 0.75, 0.45, and 0.3μm, respectively. Moreover, the variation in W, T,

and H are assumed to be 25%, 21%, and 17% of the nominal values, respectively (W and

S to be perfectly inversely correlated) (Agarwal et al., 2006b). The spread of noise

waveforms can be obtained using SPICE (Nagel et al., 1975) Monte Carlo simulations.

Using simulations it is shown that for this test case, the noise peak varies from

55

approximately 160 to 235 mV, thereby implying that variation in noise due to process

variation can be significant and should be modeled accurately. The noise-peak

distribution is Gaussian and the mean and variance of this distribution is obtained using

the Monte Carlo results. The impact of noise on functional failures is typically

characterized by noise-immunity curves.

Dynamic delay is defined as the signal delay on the victim line when both the

aggressor and the victim switch simultaneously. It is well known that an adjacent

switching aggressor can either slow down or speed up a victim depending on its

switching polarity with respect to the victim. The victim becomes slower in the case of

out-of-phase switching and faster due to in-phase switching. The delay push-out during

out-of-phase switching is a major concern due to the possibility of setup-time failures,

and hence, must be accounted for in order to ensure correct operation of the circuit. The

dynamic-delay modeling with and without process variations can ascertain the effect of

process variations.

Crosstalk noise is relatively less Gaussian than crosstalk delay. The propagated noise

is even less Gaussian. This can be attributed to non-linear nature of the transfer functions

of the CMOS gates.

56

2.6.2 Delays due to Interconnect Variation

Interconnects have turned out to be most crucial factor of signal delays,

especially, in deep and very deep submicron designs. Timing margin have become so

small as frequencies increase that even Pico-second variations can no longer be ignored,

in particular for high speed clock design. Global interconnect delay increases as

technology scales down. To mitigate the global interconnect delay problem metal wires

have been scaled in a selective fashion. Optimal buffer insertion methods, which reduce

delay from quadratic to linear, become difficult as the number of buffers increase at a fast

rate (Dhar and Franklin, 1991; Ginneken, 1990; Maheshwari and Visweswaran, 2000;

Nekili and Savaria, 1992). The proliferation of buffers also leads to increased power in

designs. Alternatives to buffer insertion have been proposed, some of which include static

source-follower driver (Acar et al., 2001), differential current sensing, and multilevel

signaling. In multilevel signaling approach matching and proper sizing of the driver and

receiver transistors is done and it is thus prone to process variations, resulting in doubled

bandwidth and delay comparable to buffer insertion.

Simply scaling down the supply voltage, undesirable characteristics of scaled

CMOS, such as Drain Induced Barrier Lowering (DIBL), quantum mechanical gate

tunneling, and punch through can also be alleviated (Chandra et al., 2002; Chandrakasan

et al., 2001). In the sub-threshold region, the MOS gate capacitance is significantly less

than that in the super-threshold region due to the channel depletion capacitance that

57

appears in series with the oxide capacitance (Kil et al., 2006). Unlike MOS gate

capacitance, the wire capacitance value is independent of the supply voltage. As a result,

the CV/I delay of wires increase more steeply than that of logic gates in sub-threshold

circuits, exacerbating the global interconnect delay problem. Several testing

methodologies have been suggested by researchers for interconnect centric VLSI chip

such as FPGAs, Memories, MPUs etc (Renovell et al., 1997; Renovell et al., 1998;

Renovell et al., 1999; Renovell et al., 2002)

To first order, delay through interconnect can be expressed as the RC product of

its resistance and capacitance. With any change in the physical dimensions of the wire, its

resistance and capacitance also change, causing interconnect delay to fluctuate. In order

to model the impact of variability on wire delay, one needs to capture the effect of

geometric variations on the electrical parameters. The change in electrical parameters due

to variations in geometric dimensions can be captured by the simple linear

approximation.

The thickness of metal lines can vary at the bottom due to etch effects. The

Chemical Mechanical Polishing (CMP) effect influences the thickness variation from the

top of the metal, varying the inter-wire resistance and capacitance. Though the

distribution of resistance is fairly Gaussian, the tail of the distribution can be attributed to

non-linear increase in resistance due to electron scattering effects. Surface and grain

58

boundary scattering of electrons increases the resistance for narrow width wires. As

technology continues to scale, the tail would become more prominent due to increased

electron scattering effect. The delay distribution using Monte Carlo simulations shows

that, even with large variations in geometric dimensions, the delay distribution remains

Gaussian.

Characterizing and managing process variations of interconnect geometry is

becoming critical for 0.13 micron and below. Delay analysis can no longer ignore process

variations for 0.13 micron and below technologies. Individual parameter sensitivity

analysis show that the delays are most influenced by the interconnect resistance and

capacitance (Lu et al., 2004).

2.6.3 Parametric Delay Evaluation under Process Variation

In order to address the effect of process variation, the various methods are:

• clock skew analysis under process variation ,

• statistical performance analysis,

• worst case performance analysis parametric yield estimation,

• impact analysis on micro architecture

• Delay fault test under process variation.

59

In all the above research, one important task is to compute variation in path delay

under process variation, either as functions of process variables or as random variables of

certain distribution. However, the conventional methods to compute path delay are either

slow or inaccurate. The response surface method (RSM) performs multiple simulations to

obtain high accuracy; the RSM method must perform multiple parasitic extractions under

different process conditions (Brawhear et al., 1994; Acar et al.¸ 2001; Gattiker et al.,

2001; Fabbro et al., 1995). Since there are a large number of metal layers in the modern

technology, there are many interconnect process variables. For example, for a k-layer

technology, there are 3k process variables, corresponding to the metal width, metal

thickness and inter-layer dialectic thickness of each layer. Thus the traditional RSM

becomes prohibitive for large circuits. Another method PARADE (Lu et al., 2004) for

fast Parametric Delay Evaluation using analytical formulae and pre-characterized lookup

tables is used to estimate for the interconnect delays. In this method variation in path

delays is evaluated efficiently, based on the lumped C delay model and based on the

effective capacitance delay model respectively. No multiple parasitic extractions and

multiple delay evaluations are needed (Lu et al., 2004). The efficiency of this method

makes it possible to comprehensively analyze circuit performance on all interconnect and

device process variables for large circuits. Compared to the traditional RSM, the delay

error is within 7% using analytical methods, and is within 1% using the table lookup

method in PARADE (Lu et al., 2004). Thus PARADE method avoids multiple parasitic

extractions and multiple delay evaluations as did in the traditional RSM, and results in

60

significant speedup. Since this method is based on effective capacitance delay model it

achieves higher accuracy (Lu et al., 2004).

2.7 Interconnect Analysis

By accounting for systematic part of process variation in timing analysis,

uncertainty in interconnects analysis can be reduced, thereby achieving closer bound for

circuit performance. One way of random analysis is to use OPERA technique that models

the stochastic response in an infinite dimensional Hilbert space in terms of orthogonal

polynomials expansions (Vrudhula et al., 2006. It is the prototype software that has the

capability to carry out a SPICE Monte Carlo analysis. Using such a polynomial

representation, there is no need to repeatedly generate samples of the random parameters,

and solve the system as required in Monte Carlo approach. Typically, interconnect

technology parameters are fixed by parasitic extractors (Sim et al., 2002; Sinha et al.,

1999) and a single fixed value is used for the inter-layer dielectric or metal thickness of

each layer. Another approach to account for process variation is depicted below

For random part, it is assumed that the change in the delay of each cell on a path

due to process variation can be described as a linear function of the variation, an

assumption valid as long as the variation are small. Making this assumption allows one to

61

sum the cell delays to calculate the probability distribution function of the path delay in a

straightforward way. First the delay sensitivities to cell physical parameters and

interconnect RC networks are calculated. Then it is integrated with RC sensitivities to

process parameters, to get the corresponding delay sensitivities to those process

parameters. Given distributions of these parameters, the delay distribution is obtained

(Dai and Ji, 2001a; Dai and Ji, 2001b).

62

Chapter 3

EFFECT OF PROCESS BASED OXIDE THICKNESS

VARIATION ON THE DELAY OF DIL SYSTEM USING

MONTE CARLO ANALYSIS

3.1 INTRODUCTION

The gate oxide, which serves as insulator between the gate and channel, should

be made as thin as possible to increase the channel conductivity and performance

when the transistor is ON and to reduce subthreshold leakage when the transistor is

OFF. However, with current gate oxides with a thickness of around 1.2 nm (which in

silicon is ~5 atoms thick) the quantum mechanical phenomenon of electron tunneling

occurs between the gate and channel, leading to increased power consumption.

Insulators that have a larger dielectric constant than silicon dioxide (referred to as

high-k dielectrics), such as group IVb metal silicates e.g. hafnium and zirconium

silicates and oxides are being used to reduce the gate leakage from the 45 nanometer

technology node onwards. Increasing the dielectric constant of the gate dielectric

allows a thicker layer while maintaining a high capacitance (capacitance is

proportional to dielectric constant and inversely proportional to dielectric thickness).

All else equal, a higher dielectric thickness reduces the quantum tunneling current

63

through the dielectric between the gate and the channel. On the other hand, the barrier

height of the new gate insulator is an important consideration; the difference in

conduction band energy between the semiconductor and the dielectric (and the

corresponding difference in valence band energy) also affects leakage current level.

For the traditional gate oxide, silicon dioxide, the former barrier is approximately 8

eV. For many alternative dielectrics the value is significantly lower, tending to

increase the tunneling current, somewhat negating the advantage of higher dielectric

constant. With extremely thin gate oxide thickness, the effect of process variation is

creeping in the overall performance of the MOSFET.

Recently, process variation has become a major concern in the design of

nanometer circuits, including interconnect pipelines, especially when semiconductor

fabrication technology is in submicron region. Process variation results in

uncertainties of circuit performances such as delay, noise and power consumption.

This chapter analyzes the effect of oxide thickness variation due to process variation

on the delay of Driver-Interconnect-Load (DIL) system in VLSI Interconnects. The

impact of this process variation on circuit delay is discussed for three different

fabrication technologies i.e. 130 nm, 70 nm and 45 nm. The results of three

technologies when compared shows that as device size shrinks the process variation

emerges as a dominant factor and subsequently increases the uncertainty of the

delays. The analysis reveals that process variation has significant effect on the driver

delay due to variation in oxide thickness of the gate.

The feature size of integrated circuits has been aggressively reduced in the

64

pursuit of improved speed, power, silicon area and cost characteristics (Rabaey, 1996;

Kang and Leblebici, 2003). Semiconductor technologies with feature sizes of several

tens of nanometers are currently in development. As per ITRS, the future nanometer

scale circuits will contain more than a billion transistors and operate at clock speeds

well over 10 GHz. Distributing robust and reliable power and ground lines; clock;

data and address; and other control signals through interconnects in such a high-

speed, high-complexity environment, is a challenging task (Cheng et al., 1999;

Kowalczyk et al., 2001; Sai-Halasz, 1995; Sylvester and Wu, 2001; Bakoglu, 1990)

as every system implemented either through ASIC design or on FPGA are prone to

the effects of the parasitic components of interconnect impedance.

The function of interconnects or wiring systems is to distribute clock and other

signals and to provide power/ground to and among the various circuits/systems

functions on the chip (Sai-Halasz, 1995; Sylvester and Wu, 2001). Interconnects

connect different macro cells within a VLSI chip. To escape prohibitively large

delays, designers scale down global wire dimensions more sluggishly than the

transistor dimensions. As technology advances, interconnects have turned out to be

more and more important than the transistor resource, and it is essential to use global

interconnects optimally. For high-density high-speed submicron-geometry chips, it is

mostly the interconnection rather than the device performance that determines the

chip performance.

Distribution of the clock and signal functions is accomplished on three types

of wiring such as local, intermediate, and global. Depending on the length of

65

Interconnect, they can be classified as local, semi-global and global (Rabaey, 1996).

Local wiring connects gates and transistors within an execution unit or a functional

block, on the chip. Local wires usually span a few gates and occupy first and

sometimes second metal layers in a multi-level system. The length of local

interconnect wire roughly scales with scaling of technology, as the increased packing

density of the devices make it possible to similarly reduce the wire lengths.

Intermediate wiring provides clock and signal distribution within a functional block

with typical lengths up to 3–4 mm. Intermediate wires are wider and taller than a local

wires to provide lower resistance signal/clock paths. Global wiring provides clock and

signal distribution between the functional blocks, and it delivers power/ground to all

functions on a chip. Global wires, which occupy the top one or two layers, are longer

than 4 mm and can be as long as half of the chip perimeter. The length of global

interconnect wires grow proportionally to the die size. The length of semi-global

interconnect behaves intermediately. The global interconnects are much wider than

local and semi-global interconnects. Thus resistance of global interconnects is small

and therefore their behavior resembles that of lossless transmission lines.

A high-performance chip is heavily dependent on the interconnects,

connecting different macro cells within a VLSI/ULSI chip (Bernstein and Rohrer,

1999; Gasteier, et al., 1998; Deutsch, et al., 1997; Eo and Eisenstadt, 1993; Jarvis,

1963). With increase in length of interconnects and clock frequency on a chip, the

effects of interconnects cannot be predicted accurately if restricted to RC models

(Davis and Meindl, 2000; Kaushik and Sarkar, 2008). The parameters such as faster

on-chip rise times and wider wires, effects of on-chip inductance are continuously

66

increasing. The interconnect delay dominates gate delay in current deep sub

micrometer VLSI circuits (Sakurai, 1983; Sakurai, 1993). Such behavior is expected

to increase further when scaling in fabrication technology reaches in submicron

region.

Wide wires are frequently encountered in clock distribution networks, power

and ground lines, and other global interconnects such as data bus and control lines in

upper metal layers. These wires are low resistive lines that can exhibit significant

inductive effects. Due to presence of these inductive effects, the new generation VLSI

designers have been forced to model interconnects as distributed RLC transmission

lines, rather than simple RC–ones. Modeling interconnects as distributed RLC

transmission line, has posed many challenges in terms of accurately determining the

signal propagation delay; power dissipation through an interconnect; crosstalk

between co-planar interconnects and interconnects on different planes due to

capacitive and inductive coupling; and optimal repeater insertion (Bakoglu and

Meindl, 1985; Adler and Friedman, 1998; Alpert et al., 1997).

On-chip global interconnects is among the top challenges in CMOS

technology scaling due to rapidly increasing operating frequencies and growing chip

size. The clock signal has already been brought into the multi-gigahertz range where

inductance and other transmission line effects of on-chip long lines become important.

For higher operating frequencies, dispersion and skin effects are among the new

concerns. The use of reverse scaling methodology will decrease the line resistance,

but the line inductance effects will become more prominent. With global clock

67

network, which was already power hungry, there is likely that more power is

consumed and hence become even more difficult to design. Particularly, the delay

induced by word lines, bit lines, clock lines, and bus lines in memory or logic VLSI

will remain the key concerns while designing the interconnects.

To avoid prohibitively large latencies, designers scale down global wire

dimensions more slowly than the transistors dimensions and this causes a rapid

growth in gap between transistors and interconnects densities on a chip. Thereby, as

technology advances to Giga-Scale Integration (GSI), global interconnect resource

becomes more and more valuable and it is essential to use global interconnects

optimally.

The reduced predictability, as device dimensions shrink below the sub-100-nm

scale, effects performance of VLSI/ULSI chip. This is due to poor control of the

physical features of devices and interconnects during the manufacturing process.

Variations in these quantities result in variations in the electrical behavior of circuits.

These variations have interdie and intradie components, as well as layout pattern

dependencies. The device material variations in geometry (tox, Leff, W), and variations

in doping levels and profiles have a direct impact on the behavior of a MOSFET.

Variations in the line width affect the resistance and the interlayer capacitance.

Variations in the inter-wire spacing may cause a significant degradation in the signal

integrity. Layout pattern dependent variations within the interlayer oxide and the chip

multiprocessing process also have a significant impact on interconnect parasitic. The

dissimilar sources of variations in the IC fabrication process lead to both random and

68

systematic effects on circuit performance. All the above mentioned facts make it

increasingly difficult to accurately predict the performance of a circuit at the design

stage, which ultimately translates to a parametric yield loss. The recent trends in VLSI

chip exhibit significant variations within a chip and between chips, due to the high

complexity of design and the presence of large number of correlated parameters.

Therefore, fast and efficient methods are required to compute an accurate statistical

description of the response.

Process variations are not completely random. It can be divided into

deterministic part and nondeterministic part. Random variations are intrinsic

fluctuations in process parameters such as dopant fluctuations from wafer to wafer,

lot-to-lot. On the other hand, systematic variations depend on the layout pattern and

are therefore predictable for the systematic part, the variations need to be

experimentally modeled and calibrated, in order to either compensate hiring the

design phase or captured in the analysis phase. These effects, which include optical

proximity correction (OPC), residual error and chemical mechanical planarization

(CMP) dishing (Orshansky et al., 2000), have a substantial but deterministic impact

on the critical dimension (CD) of a transistor gate or the width and thickness of an

interconnect wire. By accounting for systematic part of process variation in timing

analysis, uncertainty can be reduced, thereby achieving closer bound for circuit

performance. With the shrinking feature size in VLSI technology, the impact of

process variation is increasingly felt. To address the effect, great amount of research

has been done recently, such as the clock skew analysis under process variation (Liu

et al., 2000; Mehrotra et al., 2000; Malavasi et al., 2002), statistical performance

69

analysis (Brawhear et al.¸1994; Chang and Sapatnekar, 2003; Agarwal et al., 2003),

worst case performance analysis (Orshansky et al., 2000; Acar et al., 2001),

parametric yield estimation (Borkar et al., 2003), impact analysis on micro

architecture (Borkar et al., 2003) and delay fault (Gattiker et al., 2001) test under

process variation (Luong and Walker 1996; Liou et al., 2002; Krstic et al.¸ 2003; Lu

et al.¸ 2004). Since the width, thickness and spacing of interconnects are each scaled

by 1/α (scaling factor), cross-section areas must scale by 1/α2. The length of short

distance interconnections is scaled by 1/α, so that resistance is increased by α. With

decreasing device dimensions, we see increase in the levels of integration and

consequent increase in die size. This lengthens the interconnections from one side of

the chip to the other end and, therefore, both resistance and capacitance of

interconnects are increased, producing much larger time constants. Thus, the effects

of increased propagation delays, signal decay, and clock skew will reduce the

maximum achievable operating frequency, even though the smaller transistors

produce gates with less delay. One solution to this problem has been to make use of

multilayer interconnections with thicker, wider conductors and thicker separating

layers. Other method is to use cascaded drivers and repeaters to reduce the effects of

long interconnect. A further option is to use optical interconnection techniques where

a very high level of interconnection methodology is required. As the technology

reaches deep submicron or nanometer regime, the errors due to process variations

becomes prominent (Fabbro et al., 1995; Vrudhula et al., 2006).

This chapter analyzes the effect of oxide thickness variation due to process

variation on the delay of Driver-Interconnect-Load (DIL) system in VLSI

70

interconnects. The propagation delay variations through DIL system are observed due

to process variations in driver individually for different technologies.

3.2 PROCESS VARIATION ANALYSIS

The investigation carried out in this work takes into account a Driver-

Interconnect-Load (DIL) system. The driver is an inverter gate driving interconnects.

The driver is subjected to process variations in reference to oxide thickness for three

different technologies of 130 nm, 70 nm and 45 nm. To obtain statistical information

on how much the characteristics of a circuit can be expected to scatter over the

process, Monte Carlo analysis is applied. Monte Carlo analysis performs numerous

simulations with different boundary conditions. It chooses randomly different process

parameters within the worst case deviations from the nominal conditions for each run

and allows statistical interpretation of the results. In addition to the process parameter

variations, mismatch can be taken into account as well, providing a more

sophisticated estimation of the overall stability of the performance with respect to

variations in the processing steps. In most cases the parameters on which the

assumptions for the mismatch base upon, are worst case parameters. A proper layout

and choice of devices can significantly improve scatter due to mismatch. In order to

obtain reasonable statistical results, a large number of simulations are needed, leading

to quite long simulation times.

71

3.3 EFFECT OF OXIDE THICKNESS VARIATION ON DELAY OF DRIVER-INTERCONNECT-LOAD SYSTEM

Monte Carlo simulations are run for oxide thickness variations in 130 nm, 70

nm and 45 nm fabrication technology. Figure 3.1 shows the SPICE input and output

voltage variations for a nominal variation of 30% in oxide thickness in NMOS and

PMOS transistors in 130 nm technology. It is observed that the output varies

significantly due to the process variation parameter. Table-3.1 accounts for NMOS

oxide thickness (tox_n ), PMOS oxide thickness (tox_p), the delay due to driver

(Delay driver), the delay due to driver and interconnect line (Delay driver line), the

delay of interconnect line, the percentage variation in NMOS and PMOS oxide

thickness and percentage variation in delay of driver and line. It is observed that the

variation in delay ranges from 4.60% to -2.39% for 130 nm technology. Figure 3.2

shows the delay of driver and driver with interconnect due to variation of tox_n

whereas Figure 3.3 shows the percentage change in delay of driver and interconnect

line with the variation in oxide thickness.

72

Figure 3.1 SPICE input and output voltage due to variation in tox for 130 nm

technology

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Time (ns)

0.0

0.5

1.0

1.5

Volta

ge (V

)

v(vin,gnd)v(out1,gnd)v(out2,gnd)

Tox-130nm

73

Table 3.1: Variation in delay due to change in oxide thickness of NMOS and PMOS

for 130 nm fabrication process technology

tox_n

(nm)

tox_p

(nm)

Driver

Delay

(ps)

Driver

and Line

Delay

(ps)

Line

Delay

(ps)

Variation

in tox_n

(%)

Variation

in tox_p

(%)

Variation

in Delay of

Driver and

line

(%)

2.544 3.246 60.187 60.343 0.15641 -20.49 1.44 -2.39%

2.6988 3.091 60.298 60.444 0.14577 -15.66 -3.41 -2.23%

3.122 3.125 61.517 61.529 0.012313 -2.44 -2.33 -0.47%

3.1908 3.997 61.411 61.439 0.027984 -0.29 24.92 -0.62%

3.2 3.2 61.819 61.822 0.0026039 0.00 0.00 0.00%

3.2832 3.238 62.173 62.199 0.02.6221 2.60 1.19 0.61%

3.3192 2.835 62.579 62.626 0.04.7229 3.72 -11.40 1.30%

3.3692 3.005 62.719 62.777 0.05.8432 5.29 -6.09 1.54%

3.4023 2.588 63.174 63.253 0.07.9522 6.32 -19.10 2.31%

3.4443 3.377 62.906 62.981 0.07.4579 7.63 5.53 1.87%

3.7124 3.353 64.429 64.663 0.23408 16.01 4.78 4.60%

74

Figure 3.2: Delay of driver and driver with interconnect due to variation of tox_n

Figure 3.3: Percentage change in delay of driver and interconnect line with the

variation in oxide thickness

59.5

60

60.5

61

61.5

62

62.5

63

63.5

64

64.5

65

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9

Del

ay (p

s)

tox_n (nm)

Delay Under Process Variation

Delaydriver (ps)

Delaydriverline (ps)

-3%

-2%

-1%

0%

1%

2%

3%

4%

5%

-25 -20 -15 -10 -5 0 5 10 15 20

% C

hang

e in

Del

ay

% Change in tox_n

% Variation in Delay of Driver and Line

% Change in Delaydriverline

75

Correspondingly, MC simulations are run for oxide thickness variations in 70 nm

fabrication technology also. Figure 3.4 shows the SPICE input and output voltage

variations for variation in oxide thickness for NMOS and PMOS transistors of the

driver in 70 nm technology. It is observed that the output varies appreciably higher

than the results observed for 130 nm technology due to the process variation

parameter. Table-3.2 accounts for NMOS oxide thickness (tox_n ), PMOS oxide

thickness (tox_p), the delay due to driver (Delay driver), the delay due to driver and

interconnect line (Delay driver line), the delay of interconnect line, the percentage

variation in NMOS and PMOS oxide thickness and percentage variation in delay of

driver and line. Figure 3.4 shows the delay of driver and driver with interconnect due

to variation of tox_n whereas Figure 3.5 shows the percentage change in delay of

driver and interconnect line with the variation in oxide thickness.

76

Figure 3.4: SPICE output and input voltage variation due to change in tox for 70 nm

technology

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Time (ns)

0.0

0.5

1.0

1.5

Volta

ge (V

)


Tox-70nm

77

Table 3.2 Variation in delay due to change in oxide thickness of NMOS and PMOS

for 70 nm fabrication process technology.

tox_n

(nm)

tox_p

(nm)

Driver

Delay

(ps)

Driver

and Line

Delay (ps)

Line

Delay

(ps)

Variation

in tox_n

(%)

Variation

in tox_p

(%)

Variation in

Delay of

Driver and

line

(%)

1.2722 1.7244 49.28 49.514 0.236 -20.49 1.44 0.19

1.3494 1.6421 49.08 49.305 0.223 -15.66 -3.41 -0.24

1.561 1.6603 49.12 49.342 0.227 -2.44 -2.34 -0.16

1.5954 2.1236 49.19 49.429 0.2396 -0.29 24.92 0.02

1.6 1.7 49.19 49.421 0.234 0.00 0.00 0.00

1.6416 1.7203 49.28 49.524 0.2424 2.60 1.19 0.21

1.6596 1.5061 49.32 49.566 0.2421 3.72 -11.41 0.29

1.6846 1.5965 49.39 49.643 0.2495 5.29 -6.09 0.45

1.7011 1.3753 49.44 49.688 0.2483 6.32 -19.10 0.54

1.7221 1.794 49.51 49.769 0.2586 7.63 5.53 0.70

1.8562 1.7814 50.01 50.264 0.2544 16.01 4.79 1.71

78

Figure 3.5: Variation in driver and line delay due to change in oxide thickness

Figure 3.6: Percentage variation in Driver and line delay due to percentage change in

oxide thickness.

49

49.2

49.4

49.6

49.8

50

50.2

50.4

1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9

Del

ay (p

s)

tox_n (nm)

Delays Under Process Variation

Delaydriver (ps)


-0.5

0

0.5

1

1.5

2

-22 -17 -12 -7 -2 3 8 13 18

% C

hang

e in

Del

ay

% Change in tox_n

% Variation in Delay Under Process Variation

Variation in Delaydriverline (%)

79

Figure 3.7 demonstrates the Monte Carlo SPICE simulation input and output voltage

variations due to variation in oxide thickness in NMOS and PMOS transistors of the

driver in 45 nm technology. It is observed that the output varies drastically due to the

process variation parameter in 45 nm technology compared to 130 nm and 70 nm

technologies. Table-3.3 accounts for NMOS oxide thickness (tox_n ), PMOS oxide

thickness (tox_p), the delay due to driver (Delay driver), the delay due to driver and

interconnect line (Delay driver line), the delay of interconnect line, the percentage

variation in NMOS and PMOS oxide thickness and percentage variation in delay of

driver and line. It is observed that the variation in delay ranges from -14.1% to

10.81% for 45 nm technology. Figure 3.8 shows the delay of driver and driver with

interconnect due to variation of tox_n whereas Figure 3.9 shows the percentage

change in delay of driver and interconnect line with the variation in oxide thickness.

80

Figure 3.7 SPICE Output and input voltage variation due to change in tox for 45 nm

technology

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Time (ns)

0.0

0.5

1.0

1.5

Volta

ge (V

)


Tox-45nm

81

Table 3.3 Variation in delay due to change in oxide thickness of NMOS and PMOS

for 45 nm fabrication process technology.

tox_n

(nm)

tox_p

(nm)

Driver

Delay

(ps)

Driver and

Line Delay

(ps)

Line

Delay

(ps)

Variatio

n in

tox_n

(%)

Variatio

n in

tox_p

(%)

Variation in

Delay of

Driver and

line

(%)

0.5565 0.71 62.89 62.896 0.1000 -20.49 1.44 -14.10

0.5903 0.6761 65.34 65.463 0.1219 -15.66 -3.41 -10.59

0.6829 0.6836 71.93 72.031 0.09364 -2.44 -2.33 -1.62

0.6979 0.8744 72.75 72.846 0.08919 -0.29 24.92 -0.51

0.7 0.7 73.13 73.22 0.08780 0.00 0.00 0.00

0.7182 0.7083 74.40 74.542 0.1406 2.60 1.19 1.81

0.726 0.6201 75.09 75.278 0.1844 3.72 -11.40 2.81

0.737 0.657 75.78 75.992 0.2027 5.29 -6.09 3.79

0.7442 0.5663 76.47 76.677 0.2009 6.32 -19.10 4.72

0.7534 0.7387 76.82 77.021 0.2005 7.63 5.53 5.19

0.812 0.733 81.01 81.138 0.1262 16.01 4.79 10.81

82

Figure 3.8 Variation in all Delay due to change in oxide thickness of NMOS

Figure 3.9 Percentage Variation in Driver and line delay due to percentage change in

oxide thickness of NMOS

60

65

70

75

80

85

0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85

Del

ay (p

s)

tox_n (nm)

Variation in Delay Under Process Variation

Delaydriver (ps)


-15

-10

-5

0

5

10

15

-25 -20 -15 -10 -5 0 5 10 15 20

Varia

tion

in D

elay

(%)

Variation in tox_n (%)

Variation in Delay (%)

Variation in Delaydriverline (%)

83


process variation becomes dominant and subsequently gives rise in variation of

delays. The simulation also reveals that process variation has large effect on the driver

delay due to variation in oxide thickness. But there is a little variation in delay due to

interconnect.

3.4 CONCLUSION

Process variation represents a major challenge to design system-on-chip using

nanometer technologies. In this chapter, we have evaluated process variation effects

on Driver-interconnect-load system due to process based oxide thickness. The

performance of DIL interconnects is effected with variations in the driver and

interconnect geometry of nanoscale chips. The resulting diminished accuracy in the

estimates of performance at the design stage can lead to a significant reduction in the

parametric yield. Hence, an accurate statistical description of the DIL response is

critical for designers. While deciding deviation in electrical parameter, the random or

systematic part of process variations plays an important role. The significant

variations of device model parameters severely affect the variations in performance

parameter such as delay. The comparison between three technologies showed the

process variation becomes a dominant factor as the device size shrinks which

subsequently raises the variation in delays.

84

Chapter 4

ANALYSIS OF PROPAGATION DELAY DEVIATION

UNDER PROCESS INDUCED THRESHOLD VOLTAGE

VARIATION

4.1 INTRODUCTION

The threshold voltage of a MOSFET is usually defined as the gate voltage where

an inversion layer forms at the interface between the insulating layer (oxide) and the

substrate (body) of the transistor. The purpose of the inversion layer's forming is to allow

the flow of electrons through the gate-source junction.

In an n-MOSFET the substrate of the transistor is composed of p-type silicon,

which has positively charged mobile holes as carriers. When a positive voltage is applied

on the gate, an electric field causes the holes to be repelled from the interface, creating a

depletion region containing immobile negatively charged acceptor ions. A further

increase in the gate voltage eventually causes electrons to appear at the interface, which

is called an inversion layer, or channel. Historically the gate voltage at which the electron

85

density at the interface is the same as the hole density in the neutral bulk material is

called the threshold voltage. Practically, threshold voltage is the voltage at which there

are sufficient electrons in the inversion layer to make a low resistance conducting path

between the MOSFET source and drain. If the gate voltage is below the threshold

voltage, the transistor is turned off and ideally there is no current from the drain to the

source of the transistor. In fact, there is a current even for gate biases below threshold

(subthreshold leakage) current, although it is small and varies exponentially with gate

bias.

In modern devices the threshold voltage is a much less clear-cut parameter subject

to variation with the biases applied to the device. With MOSFETS becoming smaller, the

number of atoms in the silicon that produce many of the transistor's properties is

becoming fewer, with the result that control of dopant numbers and placement is more

erratic. During chip manufacturing, random process variations affect all transistor

dimensions: length, width, junction depths, oxide thickness etc., and become a greater

percentage of overall transistor size as the transistor shrinks. The transistor characteristics

become less certain, more statistical. The random nature of manufacture means we do not

know which particular example MOSFETs actually will end up in a particular instance of

the circuit. This uncertainty forces a less optimal design because the design must work for

a great variety of possible component MOSFETs.

Process variation in deep submicron region has emerged as a foremost

86

apprehension for design of circuits including interconnects such as uncertainties of circuit

performances of VLSI/ULSI chip below the sub-100-nm scale. The uncertainty such as

reduced predictability can be attributed to poor control of the physical features of devices

and interconnects during the manufacturing process. The above deviations results in

variations of electrical behavior of circuits. Threshold voltage of a MOSFET varies due

to changes in oxide thickness; substrate, polysilicon and implant impurity level; and

surface charge. This chapter analyzes the effect of threshold voltage variation on the

propagation delay through driver-interconnect-load (DIL) system. The impact of process

induced threshold variations on circuit delay is discussed for three different technologies

i.e 130 nm, 70 nm and 45 nm. The comparison of results between these three

technologies shows that the process variation issue becomes dominant during design

cycle, especially when it increases the uncertainty of the delays significantly.

The variation in modern nanometer circuits has not scaled down in proportion to

the scaling down of their feature sizes. The uncertainties in performance is contributed by

manufacturing process variations (e.g. threshold voltage, effective channel length),

environmental variations (e.g., supply voltage, temperature), and device fatigue

phenomenon. Parametric variations uncertainty deeply impacts the timing characteristics

of a circuit and makes timing verification extremely difficult. Hence there is need to

consider the parametric variations in timing analysis for accurate timing estimation.

The thrust of reducing the feature size of integrated circuits is to improve speed,

87

power, silicon area and cost realization (Sai-Halasz, 1995). The latest development in

semiconductor technologies with feature sizes of several tens of nanometers is currently

in progress. International Technology Roadmap for Semiconductors (ITRS) predicts that

future VLSI circuits will contain more than a billion transistors with an operating

frequency of 10GHz. Development of high-speed and high-complexity VLSI circuits is

the most challenging task in the era of nanotechnology because it is difficult to design

distributing robust, reliable power and ground lines, clock, data, address and other control

signal lines (Sylvester and Wu, 2001; Kaushik and Sarkar, 2008).

Proper distribution of clock and other signals to the power/ ground and among the

various circuits/ systems functions on the chip are the main function of interconnects or

wiring systems (Sylvester and Wu, 2001). The performance such as time delay and power

dissipation of a high-speed chip is highly dependent on interconnects, which connect

different macro cells within a VLSI chip. Designers scale down dimensions of global

wires more slothfully than the transistor dimensions to escape prohibitively large delays.

With advancement of technology, interconnects become more and more important than

the transistor resource, and it is then essential to use global interconnects optimally. For

high-speed submicron-geometry chips, the chip performance is mostly determined by

interconnection.

The sharing and circulation of clock and other signal functions is accomplished on

three types of wiring (local, intermediate, and global). Local wiring, consisting of very

88

thin lines, connects gates and transistors within an execution unit or a functional block

(such as embedded logic, cache memory, or address adder) on the chip (Sai-Halasz,

1995). Local wires which usually span a few gates, occupy mostly first and sometimes

second metal layers in a multi-level system. The length of a local interconnect wire

approximately scales with scaling of technology because of the increased packing density

of the devices which reduce the wire lengths. Intermediate wires are wider and taller than

local wires and provides clock and signal distribution within a functional block with

typical lengths up to 3–4 mm. Global wiring provides clock and signal distribution

between the functional blocks, and it delivers power/ground to all functions on a chip.

Global wires are longer than 4mm and mostly occupy the top one or two layers. The

lengths of global wires are as long as half of the chip perimeter. The intermediate length

is provided by semi-global interconnect. The global interconnects are much wider than

local and semi-global interconnects. Therefore, smaller resistance and lossless

transmission line behavior are provided by global interconnects.

The performance of a high-speed chip is highly dependent on interconnects,

which connect different macro cells within a VLSI/ULSI chip. Interconnect effects

cannot be restricted to RC models with ever-growing length of interconnects and clock

frequency on a chip (Sylvester and Wu, 2001; Kaushik and Sarkar, 2008). The

importance of on-chip inductance is continuously increasing with faster on-chip rise

times, wider wires, and the introduction of new materials for low resistance

interconnects. It has become well accepted that interconnect delay dominates gate delay

89

in current deep sub micrometer VLSI circuits (Sai-Halasz 1995; Sylvester and Wu 2001;

Kaushik and Sarkar 2008). With the continuous scaling of technology and increased die

area, this behavior is expected to continue.

Wide wires are suitable for their applications in interconnects as they encounters

clock distribution networks, power and ground lines, and other global interconnects such

as data bus and control lines in upper metal layers. These low resistive wires can exhibit

significant inductive effects. These inductive effects leads the new generation VLSI

designers to model distributed RLC transmission lines interconnects which is more

simple than RC–ones. Distributed RLC transmission line interconnects has been faced

many challenges in terms of accurately determining the signal propagation delay, power

dissipation, crosstalk between co-planar interconnects and interconnects on different

planes due to capacitive and inductive coupling, and optimal repeater insertion (Sai-

Halasz 1995; Sylvester and Wu 2001; Kaushik and Sarkar 2008).


dimensions shrink below the sub-100-nm scale (Orshansky et al., 2000; Liu et al.¸ 2000;

Mehrotra et al., 2000). The reduced predictability can be attributed to poor control of the

physical features of devices and interconnects during the manufacturing process.

Electrical behaviors of circuits are affected by variation of some specified quantities such

as physical features and manufacturing process of the devices. These variations have

interdie and intradie components, as well as layout pattern dependencies. The behavior of

90

a MOSFET is duly affected by device material variations in geometry (tox, Leff

, W), and

variations in doping levels and profiles. The line width variation affects the resistance and

interlayer capacitance whereas inter-wire spacing variations may cause a significant

degradation in the signal integrity. Interconnect parasitic, such as resistance, inductance

and capacitance are dependent on the layout pattern variations within the interlayer oxide

and the chip multiprocessing process. The dissimilar sources of variations in the IC

fabrication process lead to both random and systematic effects on circuit performance. It

becomes increasingly difficult to accurately predict the performance of a circuit at the

design stage due to all of these variations in the IC. In recent trends of VLSI, high

complexity of design and large number of correlated parameters exhibit significant

variations within a chip and between chips. Therefore, fast and efficient methods are

required to compute an accurate statistical description of the response.

Process variations can be divided into deterministic part and nondeterministic part

(Mehrotra et al., 2000; Malavasi et al., 2002). Random variations are defined as the

intrinsic fluctuations in process parameters such as dopant fluctuations from wafer to

wafer, lot- to- lot. On the other hand, systematic variations depend on the layout pattern

and these types of variations need to be experimentally modeled and calibrated. The

critical dimension (CD) of a transistor gate or the width and thickness of an interconnect

wire is affected by optical proximity correction (OPC), residual error and chemical

mechanical planarization (CMP) dishing (Brawhear et al., 1994; Chang and Sapatnekar

2003). Uncertainty can be reduced by accounting for systematic part of process variation

91

in timing analysis, by which closer bound for circuit performance can be achieved. The

impact of process variation is increasingly felt with scaling of feature sizes in deep

submicron technology. Recently, great amount of research such as clock skew analysis

under process variation (Orshansky et al., 2000; Liu et al.¸ 2000; Mehrotra et al., 2000;

Malavasi et al., 2002; Brawhear et al., 1994; Chang and Sapatnekar 2003; Agarwal et al.,

2003), statistical performance analysis (Chang and Sapatnekar 2003; Agarwal et al.,

2003), worst case performance analysis (Acar et al., 2001; Borkar et al., 2003),

parametric yield estimation (Borkar et al., 2003; Gattiker et al., 2001), impact analysis on

micro architecture (Borkar et al., 2003; Gattiker et al., 2001) and delay fault (Luong and

Walker 1996; Liou et al., 2002) test under process variation (Luong and Walker 1996;

Liou et al., 2002; Krstic et al., 2003; Lu et al., 2004) has been done to address this

effects. As the technology reaches deep submicron or nanometer regime, the errors due to

process variations becomes prominent (Lu et al., 2004; Fabbro et al., 1995; Vrudhula et

al., 2006). Threshold voltage of a MOSFET varies due to (1) Changes in oxide thickness;

(2) Substrate, polysilicon and implant impurity level; (3) Surface charge.

This chapter analyzes the effect of threshold voltage variation due to process

variation on the propagation delay of Driver-Interconnect-Load (DIL) system as shown in

Figure 4.1. The propagation delay variations through DIL system are observed due to

process variations in driver individually for different technologies i.e 130nm, 70nm and

45nm.

92

Figure 4.1 Driver Interconnect Load (DIL) System

4.2 MONTE CARLO ANALYSIS

The analysis carried out in this work takes into account a Driver-Interconnect-Load

(DIL) system as shown in Figure 4.1. The driver is an inverter gate driving interconnects.

The threshold voltage of the transistor in the driver is described by the following equation

𝑉𝑇 = 𝑉𝑇𝑂 + 𝛾�2𝛷𝑓 + 𝑉𝑆𝐵 − �2𝛷𝑓 (4.1)

where, in equation (4.1)

𝑉𝑇𝑂= Threshold voltage for 𝑉𝑆𝐵 = R

𝛾 = Fabrication –process parameter and is given as

𝛾 =�2𝑞𝑁𝐴𝜀𝑠𝐶𝑜𝑥

0V

𝛷𝑓 = −𝑘𝑇𝑞𝑙𝑛𝑁𝐴𝑛𝑖

CL

z=ℓ LN RN RN-1 LN-1 L1 V1

C2 CN-1 CN C1

VN+1

IN+1

IN

V2 R1

τ

m2

m1

Vi

93

𝑁𝐴 =doping concentration of p-type substrate.

𝐶𝑜𝑥 = Gate oxide capacitance

The threshold voltage of a device is dependent on various physical parameters

which are prone to process variation. In this analysis, the driver is subjected to process

variations in reference to threshold voltage for three different technologies of 130 nm, 70

nm and 45 nm. To obtain statistical information on how much the characteristics of a

circuit can be expected to scatter over the process, Monte Carlo analysis is applied.

Monte Carlo analysis performs numerous simulations with different boundary conditions.

It chooses randomly different process parameters within the worst case deviations from

the nominal conditions for each run and allows statistical interpretation of the results. In

addition to the process parameter variations, mismatch can be taken into account as well,

providing a more sophisticated estimation of the overall stability of the performance with

respect to variations in the processing steps. In most cases the parameters on which the

assumptions for the mismatch are based are worst case parameters. A proper layout and

choice of devices can significantly improve scatter due to mismatch. Reasonable

statistical results can be obtained provided large numbers of simulations are performed,

though leading to quite long simulation times.

94

4.3 EFFECT OF THRESHOLD VOLTAGE VARIATION ON DELAY

OF DRIVER-INTERCONNECT-LOAD SYSTEM

Monte Carlo simulations are run for threshold voltage variations in 130 nm, 70

nm and 45 nm fabrication technology. Figure 4.2 shows the SPICE input and output

voltage for a variation of 30% in threshold voltage in NMOS and PMOS transistors in

130 nm technology. It is observed that the output varies significantly due to the process

variation parameter. Table-4.1 accounts for NMOS threshold voltage (Vtn); PMOS

threshold voltage (Vtp); the delay due to driver and interconnects line; the percentage

variation in NMOS and PMOS threshold voltage and percentage variation in delay of

driver and line. It is observed that the variation in delay ranges from -2.39% to 4.60% for

130 nm technology.

95

Figure 4.2 SPICE input and output waveform through DIL for 130 nm technology Driver

0 50 100 150 200 250 300 350 400

Time (ps)

0.0

0.5

1.0

1.5

Vol

tage

(V

)

v(out2,gnd)v(vin,gnd)

130nm

96

Table 4.1 Variation in delay due to change in threshold voltage of NMOS & PMOS for

130 nm fabrication process technology

Vtn

(V) Vtp (V)

Driver

and Line

Delay (ps)

Variation in

Vtn

(%)

Variation in

Vtp (%)

Variation in Delay

of Driver and line

(%)

0.044 -0.218 59.88 -34.15 2.39 -2.39

0.049 -0.201 60.36 -26.11 -5.68 -2.23

0.064 -0.205 61.60 -4.06 -3.89 -0.47

0.066 -0.302 61.64 -0.48 41.53 -0.62

0.067 -0.213 61.82 0.00 0.00 0.00

0.070 -0.217 62.08 4.33 1.99 0.61

0.071 -0.173 62.28 6.21 -19.00 1.30

0.073 -0.191 62.40 8.81 -10.14 1.54

0.074 -0.145 62.61 10.54 -31.83 2.31

0.075 -0.233 62.56 12.72 9.22 1.87

0.085 -0.230 63.43 26.69 7.98 4.60

97


0 50 100 150 200 250 300 350 400

Time (ps)

0.0

0.5

1.0

1.5

Vol

tage

(V

)


70nm

98



Vtn

(V) Vtp (V)

Driver and

Line Delay

(ps)

Variation

in Vtn

(%)

Variation in

Vtp (%)

Variation in

Delay of Driver

and line

(%)

0.132 -0.225 44.907 -34.15 2.39 -9.13

0.148 -0.208 45.974 -26.11 -5.68 -6.97

0.192 -0.211 48.879 -4.06 -3.89 -1.10

0.199 -0.311 49.051 -0.48 41.53 0.75

0.200 -0.220 49.421 0.00 0.00 0

0.209 -0.224 50.014 4.33 1.99 1.20

0.212 -0.178 50.456 6.21 -19.00 2.09

0.218 -0.198 50.738 8.81 -10.14 2.66

0.221 -0.150 51.186 10.54 -31.83 3.57

0.225 -0.240 51.137 12.72 9.22 3.47

0.253 -0.238 53.124 26.69 7.98 7.49

99

Similarly, Monte Carlo simulations are run for threshold voltage variations in 70

nm fabrication technology also. Figure 4.3 shows the SPICE input and output voltage

variations for variation in threshold voltage for NMOS and PMOS transistors of the

driver in 70 nm technology. It is observed that the output varies appreciably higher than

the results observed for 130 nm technology due to the process variation parameter.

Table-4.2 accounts for NMOS threshold voltage (Vtn); PMOS threshold voltage

(Vtp); the delay due to driver and interconnects line; the percentage variation in NMOS

and PMOS threshold voltage and percentage variation in delay of driver and line. It is

observed that the variation in delay ranges from -9.13% to 7.49% for 70nm technology.

Figure 4.4 demonstrates the Monte Carlo SPICE simulation input and output

voltage variations due to variation in threshold voltage of NMOS and PMOS transistors

of the driver in 45 nm technology. It is observed that the output varies drastically due to

the process variation parameter in 45nm technology compared to 130nm and 70nm

technologies.

Table 4.3 accounts for NMOS threshold voltage (Vtn); PMOS threshold voltage

(Vtp); the delay due to driver and interconnect line; the percentage variation in NMOS

and PMOS threshold voltage and percentage variation in delay of driver and line. It is

observed that the variation in delay ranges from -13.9% to 12.5% for 45 nm technology.

100


0 50 100 150 200 250 300 350 400

Time (ps)

0.0

0.5

1.0

1.5

Voltage (

V)


45nm

101



Vtn (V) Vtp (V)

Driver and

Line Delay

(ps)

Variation in

Vtn

(%)

Variation

in Vtp (%)

Variation in

Delay of Driver

and line

(%)

0.145 -0.225 63.055 -34.15 2.39 -13.90

0.163 -0.208 65.425 -26.11 -5.68 -10.60

0.211 -0.211 71.976 -4.06 -3.89 -1.70

0.219 -0.311 72.613 -0.48 41.53 -0.83

0.220 -0.220 73.22 0.00 0.00 0

0.230 -0.224 74.656 4.33 1.99 1.96

0.234 -0.178 75.603 6.21 -19.00 3.25

0.239 -0.198 76.337 8.81 -10.14 4.26

0.243 -0.150 77.263 10.54 -31.83 5.52

0.248 -0.240 77.414 12.72 9.22 5.73

0.279 -0.238 82.393 26.69 7.98 12.5

102

Figure 4.5 Comparison of percentage change in delay due to variations in threshold

voltage for 130 nm, 70 nm and 45 nm technologies

The comparison between three fabrication technologies indicates that as device

size shrinks, the process variation becomes dominant and subsequently gives rise in

variation of delays. Figure 4.5 demonstrates this claim by comparing the percentage

change in delay due to variations in threshold voltage for 130 nm, 70 nm and 45 nm

technologies. It is observed that as feature reduces the variation in delay performance

increases due to change in threshold voltage. Thus these simulation results reveals that

process variation has large effect on the driver delay due to variation in threshold voltage.

-20%

-15%

-10%

-5%

0%

5%

10%

15%

-40% -30% -20% -10% 0% 10% 20% 30%

130nm

70nm

45nm

% Threshold Voltage Variation

%C

hang

e in

Del

ay

103

4.4 CONCLUSION

Process variation represents a major challenge to design system-on-chip using nanometer

technologies. In this chapter, process variation effects on the delay of Driver-

interconnect-load systems due to threshold voltage variations are evaluated. The driver

and interconnect geometry variation at nanoscale results significant variations in their

performance. The resulting diminished accuracy in the estimation of performance at the

design stage can lead to a significant reduction in the parametric yield. Thus, it becomes

critical for designer to determine an accurate statistical description of the DIL response.

In deviating electrical parameter random or systematic part of variations plays an

important role. In the presence of significant variations of device model parameters the

variations in performance parameter such as delay is severely affected. It is quite obvious

from the comparative results obtained between three technologies that as device size

shrinks the process variation becomes a dominant factor resulting in rise in the variation

in delays.

104

Chapter 5

MONTE CARLO ANALYSIS OF PROPAGATION DELAY

DUE TO PROCESS INDUCED DRIVER WIDTH

VARIATIONS

5.1 INTRODUCTION


dimensions scales down below the sub-100-nm. The design of circuits including

interconnect pipelines in current deep submicron regime is greatly affected by process

variation which results in uncertainties of circuit performances such as propagation delay.

Modern VLSI technology suggests that the poor control of physical features of devices

and interconnects are being attributed during the manufacturing process. Variations in

these quantities maps to variations in the electrical behavior of circuits. The channel

width of MOSFET varies due to changes in drain/source thickness; substrate, polysilicon

and implant impurity level; and surface charge. This research chapter provides a

comprehensive analysis of the effect of channel width variation on the propagation delay

through driver-interconnect-load (DIL) system. The impact of process induced driver

105

width variations on propagation delay of the circuit is discussed for three different

technologies i.e 130 nm, 70 nm and 45 nm. The comparison of results between these

three technologies shows that with shrinking device sizes, process variation becomes

dominant during design cycle and subsequently increases the uncertainty of the delays.

The feature size of integrated circuits has been aggressively reduced in the pursuit

of improved speed, power, silicon area and cost characteristics (Sai-Halasz, 1995).

Presently feature sizes of several tens of nanometers are currently in development in

Semiconductor technologies. According to Moore’s law, the numbers of transistors are

getting doubled on a single chip within eighteen months which ultimately increases the

complexity and packing density of a VLSI chip.

Variability in modern nanometer sized circuits has not scaled down in proportion

to the scaling down of their feature sizes. Manufacturing process variations (e.g. driver

width, effective channel length), environmental variations (e.g., supply voltage,

temperature), and device fatigue phenomenon contribute to uncertainties. Uncertainty due

to parametric variations deeply impacts the timing characteristics of a circuit and makes

timing verification extremely difficult. This necessitates the consideration of the

parametric variations in timing analysis for accurate timing estimation.

Different macro cells within a VLSI/ULSI chip will decide the performance of a

high-speed chip. Increasing length of interconnects and clock frequency on a chip, effects

106

of interconnects cannot be restricted to RC models (Sylvester and Wu 2001; Kaushik. and

Sarkar, 2008). Importance of on-chip inductance increases with faster on-chip rise times,

wider wires, and introduction of new materials for low resistance interconnects. For

current deep sub-micrometer VLSI circuits, interconnect delay dominates the gate delay

(Sai-Halasz 1995; Sylvester and Wu 2001; Kaushik. and Sarkar 2008). This interconnect

delay becomes more dominant with the continuous scaling of technology and increased

die area of a VLSI/ ULSI chip.

The propagation delay induced by word lines, bit lines, clock lines, and bus lines

in memory or logic VLSI will remain the key concerns while designing the interconnects.

The performance of VLSI/ULSI chip becomes less predictable as device dimensions

scales down below sub-100-nm technology node (Orshansky et al., 2000; Liu et al.,

2000; Mehrotra et al., 2000). Variations in the electrical behavior of circuits depend on

the variations of interdie and intradie components which in turn depend on the layout

pattern of a VLSI chip. Variations in geometry (tox, Leff, W), doping levels and profiles

have a direct impact on the behavior of a MOSFET circuit. As for example, the line-

width variations affect the resistance and the interlayer capacitance whereas inter-wire

spacing variations may cause a significant degradation in the signal integrity.

Interconnect parasitics have significantly effect on the layout pattern dependent variations

within the interlayer oxide and chip multiprocessing process. Both the random and

systematic performance of circuit is affected by these dissimilar sources of variations in

the IC fabrication process. The accurate prediction of a circuit performance at design

107

stage becomes difficult due to these variations. The recent trends in VLSI chip exhibit

significant variations within a chip and between chips, due to the high complexity of

design and the presence of large number of correlated parameters. Therefore, fast and

efficient methods are required to compute an accurate statistical description of the

response.

As the technology reaches deep submicron or nanometer regime, the errors due to

process variations becomes prominent (Lu et al., 2004; Fabbro et al., 1995; Vrudhula et

al., 2006). Driver width of a MOSFET varies due to (1) Changes in oxide thickness; (2)

Substrate, polysilicon and implant impurity level; (3) Surface charge.

This chapter analyzes the effect of channel width variation of MOSFET due to

process variation on the propagation delay of Driver-Interconnect-Load (DIL) system as

shown in Figure 5.1. The propagation delay variations through DIL system are observed

due to process variations in driver individually for different technologies i.e 130nm,

70nm and 45nm.

108


5.2 DRIVER WIDTH DEPENDENCE IN DIFFERENT MODES OF

OPERATION

The operation of a MOSFET can be separated into three different modes, depending on

the voltages at the terminals. The current through a MOSFET is heavily dependent on its

width irrespective of the region of operation.

Cutoff, Subthreshold, or Weak-Inversion Mode (When VGS < Vth):

According to the basic threshold model, the transistor is turned off, and there is no

conduction between drain and source. In reality, the Boltzmann distribution of electron

energies allows some of the more energetic electrons at the source to enter the channel

and flow to the drain, resulting in a subthreshold current that is an exponential function of

CL τ

m12

z=ℓ

RLC Interconnect

m11

Vin

109

gate–source voltage. While the current between drain and source should ideally be zero

when the transistor is being used as a turned-off switch, there is a weak-inversion current,

sometimes called subthreshold leakage. In weak inversion the current varies

exponentially with gate-to-source bias VGS as given approximately by

𝐼𝐷 ≈ 𝐼𝐷0𝑒𝑉𝐺𝑆−𝑉𝑡ℎ𝑛𝑉𝑇

where ID0 = current at VGS = Vth, the thermal voltage VT = kT / q and the slope factor n is

given by n = 1 + CD / COX, with CD = capacitance of the depletion layer and COX =

capacitance of the oxide layer. In a long-channel device, there is no drain voltage

dependence of the current once VDS > > VT, but as channel length is reduced drain-

induced barrier lowering introduces drain voltage dependence that depends in a complex

way upon the device geometry (for example, the channel doping, the junction doping and

so on). Frequently, threshold voltage Vth for this mode is defined as the gate voltage at

which a selected value of current ID0 occurs, for example, ID0 = 1 μA, which may not be

the same Vth-value used in the equations for the following modes.

Linear Region- when VGS > Vth and VDS < ( VGS – Vth ):

The transistor is turned on, and a channel has been created which allows current to flow

between the drain and the source. The MOSFET operates like a resistor, controlled by the

gate voltage relative to both the source and drain voltages. The current from drain to

source is modeled as:

𝐼𝐷 = 𝜇𝑛𝐶𝑜𝑥𝑊𝐿�(𝑉𝐺𝑆 − 𝑉𝑡ℎ)𝑉𝐷𝑆 −

𝑉𝐷𝑆2

2�

110

where μn is the charge-carrier effective mobility, W is the gate width, L is the gate length

and Cox is the gate oxide capacitance per unit area. The transition from the exponential

subthreshold region to the triode region is not as sharp as the equations suggest.

Saturation or active mode-when VGS > Vth and VDS > ( VGS – Vth )

During saturation region, since the drain voltage is higher than the gate voltage, the

electrons spread out, and conduction is not through a narrow channel but through a

broader, two- or three-dimensional current distribution extending away from the interface

and deeper in the substrate. The onset of this region is also known as pinch-off to indicate

the lack of channel region near the drain. The drain current is now weakly dependent

upon drain voltage and controlled primarily by the gate–source voltage, and modeled

approximately as:

𝐼𝐷 =𝜇𝑛𝐶𝑜𝑥

2𝑊𝐿

(𝑉𝐺𝑆 − 𝑉𝑡ℎ)2�1 + 𝜆(𝑉𝐷𝑆 − 𝑉𝐷𝑆𝑠𝑎𝑡)�

The additional factor involving λ, the channel-length modulation parameter, models

current dependence on drain voltage due to the Early effect, or channel length

modulation. As the channel length becomes very short, these equations become quite

inaccurate. New physical effects arise. For example, carrier transport in the active mode

may become limited by velocity saturation. When velocity saturation dominates, the

saturation drain current is more nearly linear than quadratic in VGS. At even shorter

lengths, carriers transport with near zero scattering, known as quasi-ballistic transport. In

addition, the output current is affected by drain-induced barrier lowering of the threshold

voltage. Moreover, with reduced sizes the effects of process variations are also

111

pronounced. Therefore, the variation in the width of MOSFET driver results in overall

deviations in propagation delay of the DIL system.

5.3 MONTE CARLO ANALYSIS

The analysis carried out in this chapter takes into account a Driver-Interconnect-Load

(DIL) system as shown in Figure 5.1. The driver is an inverter gate driving interconnects.

MOSFETs being part of driver in the DIL system does affects the overall delay

performance of the system. The propagation delay of a DIL system is dependent on

various physical parameters which are prone to process variation. In this analysis, the

driver is subjected to process variations in reference to driver width for three different

technologies of 130nm, 70nm and 45nm. To obtain statistical information on how much

the characteristics of a circuit can be expected to scatter over the process, Monte Carlo

analysis is applied. Monte Carlo analysis performs numerous simulations with different

boundary conditions. It chooses randomly different process parameters within the worst

case deviations from the nominal conditions for each run and allows statistical

interpretation of the results. In addition to the process parameter variations, mismatch can

be taken into account as well, providing a more sophisticated estimation of the overall

stability of the performance with respect to variations in the processing steps. In most

cases the parameters on which the assumptions for the mismatch are based are worst case

parameters. A proper layout and choice of devices can significantly improve scatter due

to mismatch. In order to obtain reasonable statistical results, a large number of

112

simulations are needed, leading to quite long simulation times.

5.4 EFFECT OF DRIVER WIDTH VARIATION ON DELAY OF

DRIVER-INTERCONNECT-LOAD SYSTEM

Monte Carlo simulations are run for driver width variations in 130 nm, 70 nm and

45 nm fabrication technology. Figure 5.2 shows the SPICE input and output voltage for a

variation of 20% in driver width in NMOS and PMOS transistors in 130 nm technology.

It is observed that the output varies significantly due to the process variation parameter.

Table 5.1 accounts for the percentage variation in NMOS and PMOS driver width; delay

due to driver and interconnect line; and percentage variation in delay of driver and line. It

is observed that the variation in delay ranges from -2.39% to 4.60% for 130nm

technology.

113


0 50 100 150 200 250 300 350 400

Time (ps)

0.0

0.5

1.0

1.5

Vol

tage

(V

)


130nm

114

Table 5.1 Variation in delay due to change in driver width of NMOS & PMOS for 130nm

fabrication process technology

Variation in Wn

(%)

Variation in Wp

(%)

Driver and

Line Delay

(ps)

Variation in Delay

of Driver and line

(%)

-34.15 2.39 59.88 -2.39

-26.11 -5.68 60.36 -2.23

-4.06 -3.89 61.60 -0.47

-0.48 41.53 61.64 -0.62

0.00 0.00 61.82 0.00

4.33 1.99 62.08 0.61

6.21 -19.00 62.28 1.30

8.81 -10.14 62.40 1.54

10.54 -31.83 62.61 2.31

12.72 9.22 62.56 1.87

26.69 7.98 63.43 4.60

Similarly, Monte Carlo simulations are run for driver width variations in 70 nm

fabrication technology also. Figure 5.3 shows the SPICE input and output voltage

variations for variation in driver width for NMOS and PMOS transistors of the driver in

70nm technology. It is observed that the output varies appreciably higher than the results

observed for 130nm technology due to the process variation parameter.

115


0 50 100 150 200 250 300 350 400

Time (ps)

0.0

0.5

1.0

1.5

Vol

tage

(V)


70nm

116



Variation in Wn

(%)

Variation in Wp

(%)

Driver and

Line Delay

(ps)

Variation in

Delay of Driver

and line (%)

-34.15 2.39 44.907 -9.13

-26.11 -5.68 45.974 -6.97

-4.06 -3.89 48.879 -1.10

-0.48 41.53 49.051 0.75

0.00 0.00 49.421 0

4.33 1.99 50.014 1.20

6.21 -19.00 50.456 2.09

8.81 -10.14 50.738 2.66

10.54 -31.83 51.186 3.57

12.72 9.22 51.137 3.47

26.69 7.98 53.124 7.49

117


0 50 100 150 200 250 300 350 400

Time (ps)

0.0

0.5

1.0

1.5

Vol

tage

(V

)


45nm

118

Figure 5.4 demonstrates the Monte Carlo SPICE simulation input and output

voltage variations due to variation in driver width of NMOS and PMOS transistors of the

driver in 45 nm technology. It is observed that the output varies drastically due to the

process variation parameter in 45 nm technology compared to 130 nm and 70 nm

technologies.

Table-5.2 accounts for the percentage variation in NMOS and PMOS driver

width; delay due to driver and interconnect line; and percentage variation in delay of


70nm technology.

Table 5.3 accounts for the percentage variation in NMOS and PMOS driver

width; delay due to driver and interconnect line; and percentage variation in delay of


45nm technology.

119



Variation in

Wn (%)

Variation in

Wp (%)

Driver and

Line Delay

(ps)

Variation in

Delay of Driver

and line

(%)

-34.15 2.39 63.055 -13.90

-26.11 -5.68 65.425 -10.60

-4.06 -3.89 71.976 -1.70

-0.48 41.53 72.613 -0.83

0.00 0.00 73.22 0

4.33 1.99 74.656 1.96

6.21 -19.00 75.603 3.25

8.81 -10.14 76.337 4.26

10.54 -31.83 77.263 5.52

12.72 9.22 77.414 5.73

26.69 7.98 82.393 12.5

120

Figure 5.5 Comparison of percentage change in delay due to variations in driver width

for 130 nm, 70 nm and 45 nm technologies


process variation becomes dominant and subsequently gives rise in variation of delays.

Figure 5.5 demonstrates this claim by comparing the percentage change in delay due to

variations in driver width for 130 nm, 70 nm and 45 nm technologies. It is observed that

as feature reduces the variation in delay performance increases due to change in driver

width. Thus these simulation results reveals that process variation has large effect on the

driver delay due to variation in driver width.

-15

-10

-5

0

5

10

15

-40 -30 -20 -10 0 10 20 30

% V

aria

tion

in D

elay

% Variation in Channel Width

Variation of Delay wrt to Channel Width

130nm70nm45nm

121

5.5 CONCLUSION

Process variation represents a major challenge to design system-on-chip using nanometer

technologies, especially when it comes to interconnects. This chapter evaluated the

effects of process variation on the delay of Driver-interconnect-load system due to driver

width variations. Determining an accurate statistical description of the DIL response is

critical for designers. The random or systematic part of variations plays an important role

in deviating electrical parameter. In the presence of significant variations of device model

parameters the variations in performance parameter such as delay is severely affected.

The comparison between three technologies shows that as device size shrinks the process

variation becomes a dominant factor and subsequently raises the variation in delays.

122

Chapter 6

MONTE CARLO ANALYSIS OF PROPAGATION DELAY

DUE TO PROCESS INDUCED LINE PARASITIC

VARIATIONS

6.1 INTRODUCTION

In current deep submicron region, process variation becomes a major concern

while designing of circuits including interconnect pipelines because it results in circuit

performances uncertainties such as propagation delay. For VLSI/ULSI chip, the circuit

performance becoming less predictable as device dimensions shrinks below the sub-100-

nm scale. The poor control of the physical features of devices and interconnects during

the manufacturing process results in reduced predictability, which subsequently maps to

variations in the electrical behavior of circuits. The interconnect line resistance and

capacitance varies due to changes in interconnect width and thickness, substrate, implant

impurity level, and surface charge. This chapter provides an analysis of the effect of

interconnect parasitic variation on the propagation delay through driver-interconnect-load

(DIL) system. The impact of process induced variations on propagation delay of the

123

circuit is discussed for three different fabrication technologies i.e 130 nm, 70 nm and 45

nm. The comparison between three technologies interestingly shows that the effect of line

resistive and capacitive parasitics variation on propagation delay has almost uniform

trend as feature size shrinks. However, resistive parasitic variation in global interconnects

has very nominal effect on the propagation delay as compared to capacitive parasitic.

Propagation delay variation is from 0.01% to 0.04% and -4.32% to 18.1 % due to

resistive and capacitive deviation of -6.1% to 25% respectively.

The reduced feature size of integrated circuits leads modern VLSI/ ULSI chips

with improved speed, power, silicon area and cost characteristics (Mizuno et al., 1994;

Frank et al., 2001; Croon et al., 2004). In current deep sub nanometer technology,

semiconductor devices with feature sizes of several tens of nanometers are in the way of

development. According to International Technology Roadmap for Semiconductors

(ITRS), the future nanometer scale circuits will operate at clock speeds well over 10

GHz. It is very difficult to design a distributed robust and reliable power and ground

lines, clock, data and address, and other control signals through interconnects in such a

high-speed, high-complexity environment. The performance of a high-speed chip is

highly dependent on the interconnects, which connect different macro cells within a Very

Large Scale Integration (VLSI)/ Ultra Large Scale Integration (ULSI) chip (Kaushik et

al., 2007d; Kaushik et al., 2008; Kaushik et al., 2009; Kaushik et al., 2007e).

124

Due to increasing integration density and soaring clock, uncertainties associated

with parameter variations become a first-tier concern for VLSI chip design, especially in

nanometer regime. Aggressive scaling of CMOS technology in sub-130-nm nodes has

created huge challenges. Typically, the source of variations includes process-induced and

environmental variations. Variations due to fundamental physical limits, such as random

dopant fluctuation (RDF) and line edge roughness (LER), are increasing significantly

with technology scaling (Masuda et al., 2005; Boning and Nassif 2000; Verma et al.,

2009). Moreover, manufacturing tolerances in process technology are not scaling at the

same pace as the transistor’s channel length, due to process control limitations (e.g.,

subwavelength lithography) (Masuda et al., 2005; Boning and Nassif 2000; Verma et al.,

2009). Therefore, within-die statistical process variations worsen with successive

technology generations. This chapter considers the effect of process-induced line

parasitic variations on propagation delay.

Today, semiconductor industry is facing a major challenge of variability (Masuda

et al., 2005). In addition, digital circuits show an increased sensitivity to process

variations due to low-power and low voltage operation requirements, which can result in

failing to meet timing constraints. The on-going reduction of feature size goes together

with an increase of variability. Obviously, there are more technological opportunities for

aggressive scaling when more variability can be tolerated. This will lead to better and

cheaper products (provided the quantities are large enough). Therefore, while the

challenge of the technologists is to realize scaling while controlling the variability and the

125

challenge of designers is to make the resulting variability sufficiently harmless by using

suitable architectures and topologies, the challenge of Electronic Design Automation

(EDA) is to provide accurate and efficient procedures to enable designers to understand

the effect of the pertinent process variability on their design. Increasing process

variations can affect electrical parameters of interconnects (e.g. capacitances) and further

influence circuit performance and functionality.

Due to the process variation, interconnect technology parameters (ITP) are

varying substantially. For simplicity, the researchers consider variations in metal width

(W), metal thickness (T), and interlayer dielectric (ILD) thickness (H). The typical

distribution of interconnect technology parameters can be observed for permittivity, inter

level dielectric thickness, metal height and metal width (D. Boning and S. Nassif, 2001).

The variation is especially large in the ILD (Inter Level Dielectric) thickness and metal

line width. Their variations have a definite impact to the total line capacitance and

interline coupling capacitance and result in variation of the signal delay.

6.2 ON CHIP INTERCONNECT VARIATIONS

The source for on chip variations (OCV) is related to variation in interconnects height

and width, resulting in variation in both resistance and capacitance (Demore et al., 1996).

Since the delays attributed to interconnect are becoming more dominant as geometries

shrink, particular attention should be paid to accurate analysis of interconnect variations.

126

In advanced interconnect processes, which could involve use of multiple dielectrics, use

of different metallization on different layers could result in significant variations. Erosion

is the other mechanism and is a function of line space and density. Two additional

sources of variation are the Chemical Mechanical Polishing (CMP) process and

proximity effects in the photolithography and etch processes. Variation in the CMP

process results from the difference of hardness of the interconnect material and that of the

dielectric. Ideally the CMP process will remove the unwanted Copper, leaving only lines

and vias. The photolithography and etch proximity effects are shown in micro loading

effects as the etch process step tends to over-etch isolated lines. Diffraction effects and

local scattering in photolithography may tend to over expose densely spaced lines and

under expose isolated lines. Tiling and metal slotting have been added as design rule

requirements to mitigate these effects by minimizing the density gradient. Different tiling

algorithms will give varying results, but the smaller the density gradient, the smaller the

variations that will be seen on the die (Jarrar and Taylor, 2006).

6.3 INTERCONNECT MODELS

The Telegrapher's Equations (or just Telegraph Equations) are a pair of linear

differential equations which describe the voltage and current on an electrical transmission

line with distance and time. They were developed by Oliver Heaviside who created the

transmission line model, and are based on Maxwell's Equations.

127

The transmission line model represents the transmission line as an infinite series of two-

port elementary components, each representing an infinitesimally short segment of the

transmission line:

• The distributed resistance R of the conductors is represented by a series resistor.

• The distributed inductance L (due to the magnetic field around the wires, self-

inductance, etc.) is represented by a series inductor.

• The capacitance C between the two conductors is represented by a shunt capacitor

C.

• The conductance G of the dielectric material separating the two conductors is

represented by a shunt resistor between the signal wire and the return wire.

The model consists of an infinite series of the elements, and that the values of the

components are specified per unit length. R, L, C, and G may also be functions of

frequency.

The line voltage V(x) and the current I(x) can be expressed in the frequency domain as

𝜕𝑉(𝑥)𝜕𝑥

= −(𝑅 + 𝑗𝜔𝐿)𝐼(𝑥)

𝜕𝐼(𝑥)𝜕𝑥

= −(𝐺 + 𝑗𝜔𝐶)𝑉(𝑥)

When the elements R and G are negligibly small the transmission line is considered as a

lossless structure. In this hypothetical case, the model depends only on the L and C

element which greatly simplifies the analysis. For a lossless transmission line, the second

order steady-state Telegrapher's equations are:

128

𝜕2𝑉(𝑥)𝜕𝑥2

+ 𝜔2𝐿𝐶 ∙ 𝑉(𝑥) = 0

𝜕2𝐼(𝑥)𝜕𝑥2

+ 𝜔2𝐿𝐶 ∙ 𝐼(𝑥) = 0

These are wave equations which have plane waves with equal propagation speed in the

forward and reverse directions as solutions. The physical significance of this is that

electromagnetic waves propagate down transmission lines and in general, there is a

reflected component that interferes with the original signal. These equations are

fundamental to transmission line theory.

If R and G are not neglected, the Telegrapher's equations become:

𝜕2𝑉(𝑥)𝜕𝑥2

= 𝛾2𝑉(𝑥)

𝜕2𝐼(𝑥)𝜕𝑥2

= 𝛾2𝐼(𝑥)

Where

𝛾 = �(𝑅 + 𝑗𝜔𝐿)(𝐺 + 𝑗𝜔𝐶)

and the characteristic impedance is:

𝑍0 = �(𝑅 + 𝑗𝜔𝐿)(𝐺 + 𝑗𝜔𝐶)

The solutions for V(x) and I(x) are:

𝑉(𝑥) = 𝑉+𝑒−𝛾𝑥 + 𝑉−𝑒𝛾𝑥

𝐼(𝑥) =1𝑍0

(𝑉+𝑒−𝛾𝑥 − 𝑉−𝑒𝛾𝑥)

129

The constants 𝑉± and 𝐼± must be determined from boundary conditions. For a voltage

pulse 𝑉𝑖𝑛(𝑡), starting at x = 0 and moving in the positive x-direction, then the transmitted

pulse 𝑉𝑜𝑢𝑡(𝑥, 𝑡), at position x can be obtained by computing the Fourier Transform,

𝑉�(𝜔), of 𝑉𝑖𝑛(𝑡), attenuating each frequency component by 𝑒−𝑅𝑒(𝛾)𝑥, advancing its phase

by −𝐼𝑚(𝛾)𝑥, and taking the inverse Fourier Transform. The real and imaginary parts of γ

can be computed as

𝑅𝑒(𝛾) = (𝑎2 + 𝑏2)1/4 cos(𝑎𝑡𝑎𝑛2(𝑏,𝑎)

2)

𝐼𝑚(𝛾) = (𝑎2 + 𝑏2)1/4 sin(𝑎𝑡𝑎𝑛2(𝑏,𝑎)

2)

where atan2 is the two-parameter arctangent, and

𝑎 ≡ 𝜔2𝐿𝐶[�𝑅𝜔𝐿

� �𝐺𝜔𝐶

� − 1]

𝑏 ≡ 𝜔2𝐿𝐶(𝑅𝜔𝐿

+𝐺𝜔𝐶

)

For small losses and high frequencies, to first order in R / ωL and G / ωC one obtains

𝑅𝑒(𝛾) ≈√𝐿𝐶

2(𝑅𝐿

+𝐺𝐶

)

𝐼𝑚(𝛾) ≈ 𝜔√𝐿𝐶

Noting that an advance in phase by − ωδ is equivalent to a time delay by δ, 𝑉𝑜𝑢𝑡(𝑡) can

be simply computed as

𝑉𝑜𝑢𝑡(𝑥, 𝑡) ≈ 𝑉𝑖𝑛(𝑡 − √𝐿𝐶𝑥)𝑒−√𝐿𝐶2 (𝑅𝐿+

𝐺𝐶)𝑥

130

Interconnect can be modeled as either lumped or distributed form of RC

(resistance-capacitance) or RLC (resistance-capacitance-inductance). In deep submicron

technology, lumped models are no longer capable of satisfying the accuracy

requirements. It is well accepted that simulations of a distributed RC model of an

interconnect matches more accurately the actual behavior in comparison to lumped RC

model (Kaushik et al., 2007d; Kaushik et al., 2008; Kaushik et al., 2009; Kaushik et al.,

2007e). In similar fashion, a distributed RLC model outperforms the lumped RLC model

in terms of modeling accurately the behavior of a line. A distributed RLC model of

interconnect, known as the transmission line model, becomes the most accurate

approximation of the actual behavior (Kaushik et al., 2007d). The transmission line

analogy for interconnect considers the signal propagation to be a wave propagation over

the interconnect medium. This is in contrast to the distributed RC model, where the signal

diffuses from source to the destination governed by the diffusion equation. In the wave

mode, a signal propagates by alternatively transferring energy from the electric to

magnetic fields, or equivalently from capacitive to the inductive nodes. Interconnect

models must incorporate distributed self and mutual inductance to accurately estimate

interconnect time delay, power dissipation, crosstalk and other parameters of

significance.

The RLC model of an interconnect is shown in Figure 6.1. It is assumed that

leakage conductance ‘g’ equals 0, which is true for most insulating materials such as

SiO2, sapphire etc. Dealing with inductance requires efficient extraction methods.

131

Presence of inductance also increases the processing time of the computer-aided design

tools. Usually the interconnect circuits extracted from layouts contain a large number of

nodes that make the simulation highly CPU intensive. Distributed coupled RLC models

become necessary even for the early design stages.

(a)

(b)

Figure 6.1 (a) Single lump of an RLC model (b) N-Segment RLC interconnects with G

neglected.

LN RN RN-1 LN-1 L1 V1

C2 CN-1 CN C1

VN+1

IN+1

IN

V2 R1

132

6.4 MONTE CARLO ANALYSIS OF DIL SYSTEM

The analysis carried out in this chapter takes into account a Driver-Interconnect-

Load (DIL) system as shown in Figure 6.2. The driver which is an inverter gate drives the

interconnect. The propagation delay of a DIL system is dependent on various parasitic

which are prone to process variation. This chapter will study and analysis the driver

which is subjected to process variations for three different technologies of 130nm, 70nm

and 45nm. Monte Carlo analysis is applied to obtain statistical information on how much

the characteristics of a circuit can be expected to scatter over the process. Different

boundary conditions are applied during Monte Carlo analysis to have numerous

simulations. This is done by choosing randomly different process parameters within the

worst case deviations from the nominal conditions for each run and allows statistical

interpretation of the results. In addition to the process parameter variations, mismatch can

be taken into account as well, providing a more sophisticated estimation of the overall

stability of the performance with respect to variations in the processing steps. In most

cases the parameters on which the assumptions for the mismatch are based are worst case

parameters. A proper layout and choice of devices can significantly improve scatter due

to mismatch. In order to obtain reasonable statistical results, a large number of

simulations are needed, leading to quite long simulation times. Using Monte Carlo

simulations, this work analyzes the effect of resistive and capacitive line parasitic

variation of interconnect due to process variation on the propagation delay of DIL

133

system. The propagation delay variations through DIL system are observed for process

variations in three different technologies.


6.5 RESULTS AND DISCUSSION

Monte Carlo simulation results were observed for deviation in propagation delay

with change in line parasitic. Table 6.1 shows variation in propagation delay due to

deviations in capacitance for 130nm, 70nm and 45nm fabrication technologies. It is

clearly observed that the variation in propagation delay is almost same for all process

technologies of 130nm, 70nm and 45nm. These results which can also be noticed in

Figure 6.3, are in sharp contrast to observations made in previous research works related

to process variations in oxide thickness (Verma and Kaushik, 2010), driver width (Verma

z=ℓ

τ

m12

m11

Vin

CL

rΔz rΔz rΔz

cΔz cΔz cΔz

z

ℓ lΔz lΔz lΔz

Rtot = rℓ, Ltot=lℓ and Ctot=cℓ

134

et al., 2010), and threshold variations (Verma et al., 2010). Previously, it was observed

that in presence of significant variations of device model parameters the variations in

performance parameter such as delay is severely affected. The comparison between

different technologies showed that as feature size shrinks the process variation becomes a

dominant factor and subsequently raises the variation in delays. Contradictorily, as per

the results observed in this work it is observed that although the deviation in delay is

more pronounced with increase in line capacitance variation, but these variations have

almost same magnitude as the process technology changes from 130nm to 45nm. The

delay variations are from -4.32% to 18.1 % due to capacitive deviation of -6.1% to 25%.

135

Table-6.1 Variation in propagation delay due to deviation in capacitance for 130 nm, 70

nm and 45 nm fabrication technology

% Variation in

Capacitance

Propagation

Delay Variation

(130nm)

Propagation

Delay Variation

(70nm)

Propagation

Delay Variation

(45nm)

-6.08 -4.64 -4.65 -4.32

-2.43 -1.87 -1.88 -1.77

-2.33 -1.79 -1.8 -1.69

-0.29 -0.2 -0.22 -0.21

1.19 0.83 0.9 0.86

2.6 1.82 1.94 1.93

5.28 3.71 3.93 3.92

5.53 3.87 4.12 4.1

7.63 5.3 5.63 5.62

24.92 17.93 18.53 18.1

136

Figure 6.3 - Plot showing percentage deviation in propagation delay with respect to

process induced capacitance variation.

Now, Table 6.2 shows variation in propagation delay due to deviations in

resistance for different fabrication technologies. It is demonstrated that the variation in

propagation delay is almost same for all process technologies. These results as also

shown in Figure 6.4, are again in sharp contrast to observations made by previous

research works where the variations in performance parameter such as delay is severely

affected with reduction in feature size for higher technologies. Previous researches

illustrated that with shrinking feature sizes process variation turned out to be dominant

and subsequently raised the variation in delays. Contradictorily, our results observe that

the deviation in delay is extremely small for variation of line resistance even upto 25% in

-10

-5

0

5

10

15

20

-10 -5 0 5 10 15 20 25 30

Perc

enta

ge D

evia

tion

in P

ropa

gatio

n De

lay

Process Induced Capacitance Variation Percentage

130nm70nm45nm

137

global VLSI interconnects domain. Moreover, these variations are in same magnitude as

the process technology changes from 130nm to 45nm. The delay variations were from -

0.01% to 0.04 % due to resistive deviation of -6.1% to 25%.

Table 6.2 Variation in propagation delay due to deviation in resistance for 130 nm, 70

nm and 45 nm fabrication technology

% Variation in

Resistance

Propagation

Delay Variation

(130nm)

Propagation

Delay Variation

(70nm)

Propagation Delay

Variation (45nm)

-6.09 -0.01 -0.01 -0.01

-2.44 0 0 0

-2.33 0 0 0

-0.29 0 0 0

1.19 0 0 0

2.6 0 0.01 0.01

5.29 0.01 0.01 0.01

5.53 0.01 0.01 0.01

7.63 0.01 0.01 0.01

24.92 0.04 0.04 0.04

138

Figure 6.4 Plot showing percentage deviation in propagation delay with respect to

process induced resistance variation.

6.6 CONCLUSION

This chapter evaluated the effect of process induced interconnect resistive and

capacitive parasitic deviation on propagation delay. These effects were observed for

process corners of 130nm, 70nm and 45nm technologies. Monte Carlo simulations were

run using distributed driver-interconnect-load model. The comparison between three

technologies interestingly demonstrated that the effect of line resistive and capacitive

parasitic variation on propagation delay has almost uniform trend as device size shrinks.

-0.02

-0.01

0

0.01

0.02

0.03

0.04

0.05

-10 -5 0 5 10 15 20 25 30

Perc

enta

ge D

evia

tion

in P

ropa

gatio

n De

lay

Process Induced Resistance Variation Percentage

130nm70nm45nm

139

However, resistive parasitic variation in global interconnects has very nominal effect on

the propagation delay as compared to capacitive parasitics. Propagation delay variation is

from 0.01% to 0.04% for a variation of line resistance from -6.1% to 25%. Similarly the

delay variations were from -4.32% to 18.1 % due to capacitive deviation of -6.1% to

25%.

140

Chapter 7

CONCLUSION AND

SUGGESTIONS FOR FUTURE WORK

7.1 INTRODUCTION

Nanoscale technology scaling brings the promise of continued transistor density

and performance. Many experts predict Moore’s Law scaling to continue through the

next decade. However, the road is fraught with difficulties related to the reliability impact

of increasing power dissipation and device variability. These issues are creating

tremendous research challenges for the semiconductor industry. Addressing these

problems will require innovation from all levels in the design flow from the circuit, CAD

tools to the system architecture.

This chapter summarizes the entire work reported in this thesis and finally draws

important conclusions. The scope for future work is also discussed. Section 7.2

summarizes the important findings. Section 7.3 lists points wise the important

contributions and section 7.4 suggests and discusses the scope for future work.

141

7.2 SUMMARY OF IMPORTANT FINDINGS

Process variation has turned out to be a major design concern in many nanometer

circuits, including interconnect pipelines. A comprehensive study of types and sources of

all aspects of driver and interconnect process variations is presented in this research

work. The main aim of the present work is to analyze the effect of process variation on

propagation delay in interconnect pipelines. The contributions and important

developments are presented in this thesis in the following sequence:

7.2.1 Introduction to Problem

Process variations manifest themselves as the uncertainties of circuit performance, such

as delay, noise and power consumption. Environmental variations, such as supply voltage

and temperature variations, also impact circuit delay and noise. The present research

work focused on the important issues of process variations in CMOS gate driven

interconnects load system.

7.2.2 Process Variation and Interconnects

Interconnects have turned out to be most crucial factor of signal delays, especially, in

deep and very deep submicron designs. Timing margins have become extremely small as

frequencies increase. Even Pico-second variations can no longer be ignored, in particular

for high speed clock design. This research work thoroughly reviewed the past research

works carried out on process variation and interconnects in terms of propagation delay.

142

Various aspects of CMOS driver, interconnects and process variation have been

discussed. The role of interconnect parasitics on performance is examined. The effect of

process variation on delay and power dissipation is also discussed.

7.2.3 Effect of Process Based Oxide Thickness Variation

Chapter 3 presented an analysis of propagation delay deviation at the far ends of a CMOS

driven interconnects due to process based oxide thickness variation in Driver-

Interconnects-Load (DIL) System Using Monte Carlo Analysis.

7.2.4 Propagation Delay Analysis Under Threshold Voltage Variation

Chapter 4 presented the study of the analysis of the effects of threshold voltage variation

on propagation delay in DIL system for three fabrication technologies. This study is

demonstrated using SPICE simulation.

7.2.5 Effect of Driver Width Variations on Propagation Delay

Chapter 5 presented a complete analysis of the effect of channel width variation on the

propagation delay through driver-interconnect-load (DIL) system. The consequence of

process induced driver width variations on propagation delay of the circuit is discussed

for three different technologies i.e 130nm, 70nm and 45nm.

143

7.2.6 Analysis of Propagation Delay Due to Line Parasitic Variations

Chapter 6 presented the effect of interconnect resistive and capacitive parasitic variation

on propagation delay for different fabrication technologies. The interconnect parasitic

variations is due to changes in the width of interconnect.

7.3 MAIN CONTRIBUTIONS

A detailed literature review in the area of process variations in interconnects leads to

the conclusion that in current scenario, it is not possible to overlook the effects of process

variation. This research work focused on evaluating propagation delay deviations in long

VLSI interconnects. This work addressed the requirement through adequate in-depth

analysis and supporting computer simulations. This research work in brief words

contributed following points:

Introduction of a composite representation for CMOS-driven interconnects. The

model combines Driver-distributed RLC interconnect-Load system for evaluating

the effect of process variations on overall propagation delay.

Delay deviation at the far ends of a CMOS driven interconnects due to process

based oxide thickness variation in Driver-Interconnects-Load (DIL) System Using

Monte Carlo Analysis.

144

The driver is subjected to process variations in reference to oxide thickness for

three different technologies of 130nm, 70nm and 45nm. To obtain statistical

information on how much the characteristics of a circuit can be expected to scatter

over the process, Monte Carlo analysis is applied.

Analysis of the effects of threshold voltage variation on propagation delay in DIL

system for three fabrication technologies i.e 130nm, 70nm and 45nm.

Comprehensive analysis of the effect of channel width variation on the

propagation delay through driver-interconnect-load (DIL) system. The impact of

process induced driver width variations on propagation delay of the circuit was

evaluated for three different technologies i.e 130nm, 70nm and 45nm.

Evaluation of the effect of interconnects resistive and capacitive parasitic

variation on propagation delay for different fabrication technologies.

The propagation delay variations through DIL system are observed due to variations in

driver and interconnect parameters individually for different technologies. This

observation and comparison between three technologies is presented in Table-7.1.

145

For carrying out the research analysis, the channel width, oxide thickness,

threshold voltage, line resistance and line capacitance is varied by 20, 30, 50, 30 and 30

percents. The comparison between three technologies shows that as device size shrinks,

the process variation becomes dominant and subsequently gives rise in delays. The

simulation also reveals that process variation has large effect on the driver delay due to

variation in threshold voltage, oxide thickness and width of the gate. But there is a little

variation in delay due to interconnect resistance although large delay variation can be

observed due to interconnect capacitance variations. Furthermore, the comparison

between three

Table 7.1 Maximum and Minimum variation of delays under process variation in three technologies

Technology 130nm 70nm 45nm Max. Min. Max. Min. Max. Min.

Channel Width

(20%) 3.43 -11.50 3.67 -12.40 24.0 -15.6

Oxide Thickness (30%) 4.60 -2.39 1.71 -0.24 10.81 -14.10

Threshold Voltage (50%) 2.61 -3.14 7.49 -9.13 12.50 -13.90

Line resistance (30%) 0.04 -0.01 0.01 -0.01 0.01 -0.01

Line capacitance (30%) 17.93 -4.64 18.53 -4.65 18.10 -4.32

146

technologies show that as device size shrinks the process variation becomes a dominant

factor and subsequently raises the variation in delays.

7.4 SUGGESTIONS FOR FUTURE WORK

Research and development is an unending process. Each end of a research work

triggers opening to many further avenues for future work. However, efficient solutions

are required in near future to deal with variability. This would require joint efforts at

circuit, CAD and architecture layers. Moreover, there can be trade-offs among the

efficiency of architectural choices, robustness of circuit design and complexity of CAD

tools. Studying one aspect while ignoring the others may lead to sub-optimal designs that

can potentially waste the advantage of new technologies. Variation tolerant design

requires the researchers to have knowledge in circuit, CAD and architecture fields. The

synergy of architecture, circuit and CAD will allow researchers to seek revolutionary

solutions and to achieve integrated design environment. One possible research direction

will study the variation modeling and optimization problem on programmable platforms,

since programmable platforms like high-end FPGA become more important in modern

digital system design. Variation models can be built and prototype can be quickly

implemented on the platforms for validation. Novel mapping and routing algorithms are

necessary for “location and variation aware FPGA programming”.

Reliable memory system design, as always, will be a highly researched topic for

the coming years. Variation aware SRAM and DRAM cell design for processor core will

147

be an important design concern. Feasibility of using DRAM for architecture design and

evaluation of the performance, power and reliability trade-offs can be taken over in

future. The study may cover a wide range of research aspects from the different memory

cell structure, device sizing, array organization, to a system level access pattern, data

allocation and compiler support. Testing and reconfiguration scheme also need to be

established. An alternative approach may be to mitigate the variation problem in Chip

Multi-Processing (CMP) processor so as to use a higher level approach. Cores will then

no longer be treated as equal, and each core will have a “tag” depending on its hardware

nature. This information is fed into the dynamic compiler which can recompile the

instruction flows to best adapt to the capability of each core. Finally, a bigger picture is to

use circuit and architecture resilience and adaptability to solve the problem of any

uncertainty incurred during the design, fabrication, and chip operation. This is not

necessary limited to traditional PVT variations. For example, design rules in IC layout

are defined to guarantee the reliability of circuit operation. Sometime, the design rules are

overly strict and violating these rules may not necessary cause disastrous results. By

leverage circuit and architecture resilience to fix or bypass the unreliable components, we

can violate design rules to certain degree and potentially save area and power.

Technology evolution has provided us the capability of handing billions transistors, but

also presented us the ever-larger challenge of variation and design uncertainty. It is

strongly felt that the traditional worse-case design method may have to be altered in the

near future and this would create unlimited research opportunities.

148

All important outcome of the research needs to be verified by fabrication of silicon test

structures. This work can be extended by developing analytical models and comparing

the results with simulation and experimental works.

The impact of driver and interconnect process variations simultaneously on circuit delay

and crosstalk noises can be taken up as future work. The present composite DIL model

can be extremely useful for modeling the effect of process variations on delay and

crosstalk due to driver and interconnect simultaneously.

The present work focused on copper interconnects only. As technology moves to

deep submicron level, the interconnect width also scales down. Increasing resistivity of

copper with scaling and rising demands on current density drives the need for identifying

new wiring solutions. Recently, various alternatives to copper such as carbon nanotubes,

nanowires and optical interconnects have been explored (Banerjee and Srivastava, 2006;

Chen et al., 2007; Kapur et al., 2002; Kaushik et al., 2007c; Kreupl et al., 2002, Naeemi

et al., 2005). Metallic Carbon Nano Tubes (CNTs) and optical interconnects are

promising candidates that can potentially address the challenges faced by copper. Optical

interconnects is being considered as potential substitute to copper for reducing delay and

crosstalk. CMOS-compatible modulator is one of the most challenging elements in the

optical data path. An advantage of optical interconnect is the smaller crosstalk noise as

compared with electrical interconnect (Kapur et al., 2002). However, the main barriers to

optical onset are due to yield of the modulators; the large area and power consumption of

149

the optical components and driving circuits particularly the modulator; generation of

sufficient optical power to maintain optical operation; the on-chip fabrication of the

interconnect; and silicon optoelectronic circuit packaging. Efficient light sources and

detectors are thought-out to be crucial for the development of future on-chip optical

interconnects. In order to fully make use of the potential of optical interconnects; a set of

integrated silicon compatible WDM components has to be developed in future. Apart

from fabrication issues, delay and crosstalk analytical models of CMOS driven optical

interconnect can be taken up as future work.

Regime of CNTs in future VLSI interconnect applications is also seen

aggressively (Kreupl et al., 2002; Srivastava and Banerjee, 2005; Wei et al., 2001). The

metallic single-walled CNTs outstanding intrinsic properties coupled with encouraging

performance, power and thermal reliability of CNT bundles provide sound foundation for

further financial and research investments. Several challenges prevail in the areas of

fabrication and process integration. Although these challenges are not expected to cause

any fundamental problems, lowering of metal nanotube contact resistance would be

essential, especially for local interconnect and via applications. Moreover, rigorous

characterization and modeling of electromagnetic interactions in CNT bundles; 3D

(metal) to 1D (CNT) contact resistance; impact of defects on electrical and thermal

properties; and high-frequency effects are being seen as additional challenges. Although

optical and CNTs can be safely predicted as future interconnects, but these technologies

are still under research and therefore amateur as compared to well established fabrication

150

technique in copper. The theoretical aspects proves CNTs and optical interconnect to be

better alternative against copper on the ground of performance parameters such as power

dissipation, switching delay, area and crosstalk. However, in future, efforts can be

disseminated in developing much needed fabrication techniques. Optical interconnects

and CNTs will overcome the regime of copper in near future. Thus much of the future

research efforts can be focused on delay and crosstalk analysis using optical and carbon

nanotube (Kaushik, 2007).

151

APPENDIX A

SOME IMPORTANT WEBSITES

Some important websites, which provide useful information, practical data, design

parameters and technological issues related to interconnect design, MOS models and

simulation EDA tools in VLSI design, are given below:

1) Citeseer, http://www.citeseer.org

2) Emerald, http://www.emeraldinsight.com

3) Science Direct, http://www.elsevier.com

4) IEEE, http://www.ieee.org

5) IEE, http://www.iee.org

6) MOSIS, http://www.mosis.org

7) OrCAD, http://www.orcad.org

8) VDAT, http://www.vlsi-india.org

9) Tanner, http://www.tanner.org

10) HIT, www.hait.ac.il.

11) JAPED, http://www.oldcitypublishing.com/JAPED

12) IJSCI, http://www.ijsci.org

http://www.citeseer.org/�

http://www.emeraldinsight.com/�

http://www.elsevier.com/�

http://www.ieee.org/�

http://www.iee.org/�

http://www.mosis.org/�

http://www.orcad.org/�

http://www.vlsi-india.org/�

http://www.tanner.org/�

http://www.hait.ac.il/�

http://www.oldcitypublishing.com/JAPED�

http://www.ijsci.org/�

152

REFERENCES

Acar E., Odabasioglu A., Celik M. and Pileggi L., (1999) “S2P: A stable 2-pole RC

delay and coupling noise metric for IC interconnects,” in Proc. Great Lakes

Symp. VLSI, Ann Arbor, MI, pp. 60–63.

Acar E., Nassif S.N., Ying L. and Pileggi, L. T., (2001) “Assessment of true worst

case circuit performance under interconnect parameter variations,” International

Symposium on Quality Electronic Design (ISQED), pp. 431–436.

Achar R. and Nakhla M., (2001) “Simulation of high-speed interconnects,” Proceed.

IEEE, vol. 89, no. 5, pp. 693–728.

Adler V. and Friedman E.G., (1998) “Repeater design to reduce delay and power in

resistive interconnect,” IEEE Trans. on Circuits and Systems-II, vol. 45, no. 5,

pp. 607–616.

Agarwal A., Blaauw D. and Zolotov V. (2003) “Statistical timing analysis for intra-

die process variations with spatial correlations,” International Conference on

Computer-Aided Design (ICCAD), pp. 271–276.

Agarwal D., (2002) “Optical interconnects to silicon chips using short pulses”, Phd.

Thesis submitted at Stanford University.

Agarwal K., Sylvester D. and Blaauw D., (2004) “A library compatible driver output

model for on-chip RLC transmission lines,” IEEE Trans. on Computer-Aided

Design of Integrated Circuits and Systems, vol. 23, no. 1, pp. 128-136.

Agarwal K., Sylvester D., and Blaauw D., (2006a) “Modeling and analysis of

crosstalk noise in coupled RLC interconnects,” IEEE Trans. on Computer-Aided

Design of Integrated Circuits and Systems, vol. 25, no. 5, pp. 892-901.

Agarwal K., Agarwal M., Sylvester D. and Blaauw D., (2006b) “Statistical

Interconnect Metrics for Physical-Design Optimization” IEEE Transactions on

CAD of Integrated Circuits and Systems, Vol. 25, No. 7, pp.1273-1288.

Alers C., Sukamto J., Park S., Harm C., and Reid J., (2006) “Containing the finite size

effect in copper lines," Semiconductor International, vol. 29, no. 5, pp. 38-42.

153

Alpert C. J., (1997) “Wire segmenting for improved buffer insertion,” in Proc.

IEEE/ACM Design Automation Conf., pp. 588–593.

Alpert C. J., Devgan A., and Quay S. T., (1998) “Buffer insertion for noise and delay

optimization,” in Proc. of the ACM/IEEE Design Automation Conference, pp.

362–367.

Alpert C. J., Devgan A. and Quay S. T., (1999) “Buffer insertion for noise and delay

optimization,” IEEE Trans. on Computer-Aided Design of Integrated Circuits

and Systems, vol. 18, no. II, pp. 1633-1645.

Anderson C., Petrovick J., Keaty J., Warnock J., Nussbaum G., Tendler J., Carter C.,

Chu S., Clabes J., DiLullo J., Dudley P., Harvey P., Krauter B., LeBlanc J., Lu

P.-F., McCredie B., Plum G., Restle P., Runyon S., Scheuermann M., Schmidt

S., Wagoner J., Weiss R., Weitzel S., and Zoric B., (2001) “Physical design of a

fourth-generation power GHz microprocessor," in Digest of Technical Papers -

IEEE International Solid-State Circuits Conference. Institute of Electrical and

Electronics Engineers Inc., pp. 232-233.

Anderson F. E., Wills J. S. and Berta E. Z. (2002), “The core clock system on the next

generation Itanium™ microprocessor,” in Proc. ISSCC, San Francisco, pp.

146–147.

Asenov A., Kaya S., and Davies J. H. (2002), “Intrinsic threshold voltage fluctuations

in decanano MOSFETs due to local oxide thickness variations,” IEEE

Transactions on Electron Devices, vol. 49, no. 1, pp. 112–19.

Azuma A., Oishi A., Okayama Y., K Kasai. and Toyoshima K. (1998), “Methodology

of MOSFET characteristics fluctuation description using BSIM3V3 SPICE

model for statistical circuit simulations," International Workshop on Statistical

Metrology, Proceedings, IWSM, pp. 14-17.

Bai P., Auth C., Balakrishnan S., Bost M., Brain R., Chikarmane V., Heussner R.,

Hussein M., Hwang J., Ingerly D., James R., Jeong J., Kenyon C., Lee E., Lee

S.-H., Lindert N., Liu M., Ma Z., Marieb T., Murthy A., Nagisetty R., Natarajan

S., Neirynck J., Ott A., Parker C., Sebastian J., Shaheed R., Sivakumar S.,

Steigerwald J., Tyagi S., Weber C., Woolery B., Yeoh A., Zhang K., and Bohr

M. (2005), “A 65nm logic technology featuring 35nm gate lengths, enhanced

channel strain, 8 cu interconnect layers, low-k ILD and 0.57 M2 SRAM cell,"

154

2004 International Electron Devices Meeting (IEEE Cat. No.04CH37602), pp.

657-660.

Bakoglu H. B., (1990) Circuits, Interconnections, and Packaging for VLSI, Reading,

MA: Addison-Wesley.

Bakoglu H. B. and Meindl J. D. (1985), “Optimal interconnection circuits for VLSI,”

IEEE Trans. on Electron Devices, vol. ED-32, pp. 903–909.

Banerjee K. and Mehrotra A., (2001a) “Accurate analysis of on-chip inductance

effects and implications for optimal repeater insertion and technology scaling,”

in Proc. IEEE Symp. VLSI Circuits, Kyoto, Japan, pp. 195–198.

Banerjee K. and Mehrotra A., (2001b) “Accurate analysis of on-chip effects using a

novel performance optimization methodology for distributed RLC

interconnnects,” in Proc. Design Automation Conf., Las Vegas, NV, pp. 798–

803.

Banerjee K. and Mehrotra A., (2002) “Analysis of on-chip inductance effects for

distributed RLC interconnects,” IEEE Trans. on Computer-Aided Design of

Integrated Circuits and Systems, vol. 21, pp. 904–915.

Banerjee, K. and Srivastava, N., (2006) "Are carbon nanotubes the future of VLSI

interconnections?," in Proc. ACM/IEEE Design Automation Conf., San

Francisco, CA, pp.809-14.

Barnat E. and Lu T.-M., (2001) “Real time copper resistivity measurements during

sputter deposition," in Proceedings of the IEEE 2001 International Interconnect

Technology Conference, Burlingame, CA, USA: IEEE, pp. 24-26.

Benini L., Macii A., Macii E., Poncino M. and Scarsi R., (1999) “Synthesis of low-

overhead interfaces for power-efficient communication over wide buses,” in

Proc. ACM/IEEE Design Automation Conf., pp. 128–133.

Besling W., Broekaart M., Arnal V., and Torres J., (2004) “Line resistance behaviour

in narrow lines patterned by a tin hard mask spacer for 45 nm node

interconnects," in European Workshop on Materials for Advanced Metallization

2004, 7-10 March 2004 Microelectronic Engineering, vol. 76. Brussels,

Belgium: Elsevier, pp. 167-174.

155

Bhardwaj S., Vrudhula S. B. K. and Blaauw D., (2002) “Estimation of signal arrival

times in the presence of delay noise,” in Proc. Int. Conf. Computer Aided

Design, San Jose, CA, pp. 418–422.

Boning D. (2003), “Pattern dependent characterization of copper interconnect,"

presented at the International Conference on Microelectronic Test Structures,

116.

Boning D.S. and Nassif S., (2000) “Models of Process Variations in Device and

Interconnect”, in Chandrakasan A., Bowhill W. and Fox F., editors, Design of

High Performance Microprocessor Circuits, chapter 6. IEEE Press,

Borkar S., Kamik T., Narendra S., Tschanz J., Keshavarzi A. and De V. (2003)

“Parameter variations and impact on circuits and microarchitecture,” Design

Automation Conference (DAC), pp. 338–342.

Boulejfen N., Kouki A. and Ghannouchi F., (2000) “Frequency and time domain

analysis of nonuniform lossy coupled transmission lines with linear and

nonlinear terminations,” IEEE Trans. on Microwave Theory and Techniques,

vol. 48, no. 3, pp. 367–379.

Bowman K., (2001) “A circuit-level perspective of opportunities and limitations for

gigascaleintegration (GSI)," Ph.D. dissertation, Georgia Institute of Technology.

Bowman K., Duvall S., and Meindl J., (2002) “Impact of die-to-die and within-die

parameter fluctuations on the maximum clock frequency distribution for

gigascale integration," IEEE Journal of Solid-State Circuits, vol. 37, no. 2, pp.

183-190.

Brain R., Agrawal S., Becher D., Bigwood R., Buehler M., Chikarmane V., Childs

M., Choi J., Daviess S., Ganpule C., He J., Hentges P., Jin I., Klopcic S.,

Malyavantham G., McFadden B., Neulinger J., Neirynck J., Neirynck Y., Pelto

C., Plekhanov P., Shusterman Y., Van T., Weiss M., Williams S., Xia F., Yashar

P., and Yeoh A., (2009) “Low-K interconnect stack with a novel self-aligned via

patterning process for 32 nm high volume manufacturing," IEEE International

Interconnect Technology Conference - IITC, pp. 249-251.

Branin Jr .F. H., (1967) “Transient analysis of lossless transmission lines,” Proc.

IEEE, vol. 55, pp. 2012–2013.

156

Brawhear R.B., Menezes N., Oh C., Pillage L.T. and Mercer M.R., (1994) “Predicting

circuit performance using circuit-level statistical timing analysis,” Design,

Automation, and Test in Europe (DATE) Conference, pp. 332–337.

Campbell S. A., (2001) “The science and engineering of microelectronic fabrication”,

2nd ed.ser. The Oxford Series in Electrical and Computer Engineering. New

York: Oxford University Press.

Cao Y., Huang X., Sylvester D., Chang N. and Hu C., (2000) “A new analytical delay

and noise model for on-chip RLC interconnect,” in Proc. IEDM, San Francisco,

CA, pp. 823–826.

Cases M. and Quinn D. M., (1980) “Transient response of uniform distributed RLC

transmission lines,” IEEE Trans. Circuits and Syst., vol. 27, pp. 200–980.

Cassan E., Dollfus P., Galdin S. and Hesto P., (2000) “Calculation of direct tunneling

gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and

HMOSFETs,” Microelectronics Reliability, vol. 40, no. 4, pp. 585–588..

Chandra G., Kapur P. and Saraswat K. C., (2002) “Scaling trends for the on chip

power dissipation” in Proc. IEEE Interconnect Technology Conf., pp. 170–172.

Chandrakasan A., Bowhill W.J. and Fox F., (2001) Design of High Performance

Microprocessor Circuits, IEEE Press, ISBN 0-7803-6001-X.

Chang H. and Sapatnekar S. S., (2003) “Statistical timing analysis considering spatial

correlations using a single PERT-like traversal,” International Conference on

Computer-Aided Design (ICCAD), pp. 621–625.

Chatzigeorgiou A., Nikolaidis S. and Tsoukalas I., (2001) “Modeling CMOS gates

driving RC interconnect loads,” IEEE Trans. on Circuits Systems—II: Analog

Digital Signal Process, vol. 48, no.4, pp. 413–418.

Chaudhary K., Onozawa A. and Kuh E.S., (1993) “A spacing algorithm for

performance enhancement and cross-talk reduction,” in Dig. Tech. Papers

IEEE/ACM Int. Conf. Computer-Aided Design, pp. 697–702.

Chen F. and Gardner D., (1998) “Influence of line dimensions on the resistance of Cu

interconnections," IEEE Electron Device Letters, vol. 19, no. 12, pp. 508-510.

Chen G., Chen H., Haurylau M., Nelson N.A., Albonesi D.H., Fauchet P.M. and

Friedman E.G., (2007) “Predictions of CMOS compatible on-chip optical

157

interconnect,” Integration, the VLSI Journal, Elsevier Pub., Netherlands, vol.

40, no.4, pp. 434-446.

Chen G. and Friedman E. G., (2005) “An RLC interconnect model based on Fourier

analysis” IEEE Trans. on Computer-Aided Design of Integrated Circuits and

Systems, vol. 24, no. 2, pp.170 -183.

Chen H.-C., Chen H.-W., Jeng S.-P., Wu C.-H., and Sun J.-C., (2006) “Resistance

increase in metal nano-wires," in 2006 International Symposium on VLSI

Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan: IEEE,

2006, pp.129-130.

Chen L.H. and Marek-Sadowska M., (2002) “Closed-form crosstalk noise metrics for

physical design applications,” in Proc. Design Automation and Test Eur. Conf.,

Paris, France, pp. 812–819.

Cheng C.-K., Lillis J., Lin S. and Chang N., (1999) Interconnect Analysis and

Synthesis. New York: Wiley.

Chern J.-H., Huang J., Arledge L., Li P.-C., and Yang P., (1992) “Multilevel metal

capacitance models for cad design synthesis systems," IEEE Electron Device

Letters, vol. 13, no. 1, pp. 32-34.

Cong J., (1999) “An interconnect-centric design flow for nanometer technologies” in

Proc. Int. Symp. VLSI Technology, Systems, and Applications, pp. 54–57.

Cong J. and He L., (1995) “Optimal wire sizing for interconnects with multiple

sources,” Proc. IEEE/ACM Design Automation Conf., pp. 568-574.

Cong J., He L., Koh C. and Madden P.H., (1996) “Performance optimization of VLSI

interconnect layout,” Integration, the VLSI Journal, Elsevier Pub., Netherlands,

vol. 21, no.1-2, pp. 1-94.

Cong J., He L., Koh C.-K. and Pan Z., (1997a) “Global interconnect sizing and

spacing with consideration of coupling capacitance,” in Proc. ACM/IEEE Int.

Conf. Computer-Aided Design, pp.628-633.

Cong J., Kahng A.B., Koh C., and Tsao C.-W.A., (1995) “Bounded-slew clock and

Steiner routing under Elmore delay,” Proc. IEEE Int. Conf. Computer-Aided

Design, pp. 66-71.

158

Cong J., Lei Het J., Kahng A.B., Noice D., Shirali N. and Yen S.H.-C., (1997b)

“Analysis and justification of a simple, practical 2 1/2-D capacitance extraction

methodology,” in Proc. Design Automation Conf., pp. 627–632.

Cong J. and Leung K.-S., (1993) “Optimal wire sizing under the distributed Elmore

delay model,” in Dig. Tech. Papers IEEE lnt. Conf. Computer- Aided Design,,

pp. 634-639.

Cong J., Leung K.-S. and Zhou D., (1993) “Performance-driven interconnect design

based on distributed RC delay model,” in Proc. 30th ACMLEEE Design

Automation Conf., pp. 606-611.

Coulibaly L.M. and Kadim H.J., (2004) “Analytical ramp delay model for distributed

on-chip RLC interconnects” in Proc. IEEE Midwest Symposium on Circuits and

Systems, vol. 1, pp. 457-460.

Coulibaly L. M. and Kadim H.J., (2005) “Analytical crosstalk noise and its induced-

delay estimation for distributed RLC interconnects under ramp excitation” Proc

IEEE International Sym on Circuits and Systems, vol. 2, pp. 1254-1257.

Croon J. A., Storms G., Winkelmeier S. and Pollentier I., (2002) “Line-Edge

Roughness: Characterization, Modeling, and Impact on Device Behavior,” in

Proceedings of International Electron Devices Meeting, pp. 307–310.

Croon J., Decoutere S., Sansen W. and Maes H., (2004) “Physical modeling and

prediction of the matching properties of MOSFETs,” in Proc. 34th European

Solid-State Device Research Conference (ESSDERC), pp. 193–196.

Cullum J., Ruehli A. and Zhang T., (2000) “A method of reduced-order modeling and

simulation of large interconnect circuits and its application to PEEC models

with retardation,” IEEE Trans. on Circuits and Systems-II: Analog and Digital

Signal Processing, vol. 47, no.4, pp. 261–273.

Dai W. and Ji H., (2001a) “Timing Analysis Taking into Account Interconnect

Process Variation”, Procd. IEEE Statistical Methodology, Japan, pp.51-53.

Dai W. and Ji H., (2001b) “Timing analysis taking into account interconnect process

variation," in 2001 6th International Workshop on Statistical Methodology,

Kyoto, Japan: IEEE, 2001, pp. 51-53.

159

Das, B.P. (2009) “Random Local Delay Variability: On-chip Measurement and

Modeling” PhD. Thesis submitted at Centre for Electronics Design and

Technology, Indian Institute of Science, Bangalore.

Davis J. A. and Meindl J. D., (2000a) “Compact distributed RLC interconnect

models—Part I: Single line transient, time delay and overshoot expressions,”

IEEE Trans. on Electron Devices, vol. 47, pp. 2068–2077.

Davis J. A. and Meindl J. D., (2000b) “Compact distributed RLC interconnect

models—Part II: Coupled line transient expressions and peak crosstalk in

multilevel interconnect networks,” IEEE Trans. on Electron Devices, vol. 47,

pp. 2078–2087.

Delorme N., Belleville M. and Chilo J., (1996) “Inductance and capacitance analytic

formulas for VLSI interconnects”, Electronics Letters, vol. 32, no. 11, pp. 996-

997.

Deutsch A., Kopcsay G.V., Restle P.J., Smith H.H., Katopis G., Becker W.D., Coteus

P.W., Surovic C.W., Rubin B.J., Dunne R.P., Jr., Gallo T., Jenkins K.A.,

Terman L.M., Dennard R.H., Sai-Halasz G.A., Krauter B.L. and Knebel D.R.,

(1997) “When are transmission-line effects important for on-chip

interconnections?,” IEEE Trans. on Microwave Theory and Techniques, vol.

45, no. 10, part-2, pp.1836 – 1846.

Devgan A., (1997) “Efficient coupled noise estimation for on-chip interconnects,” in

Proc. Int. Conf. Computer-Aided Design, San Jose, CA, pp. 147–153.

Dhar S. and Franklin M. A., (1991) “Optimum buffer circuits for driving long

uniform lines,” IEEE Jour. Solid-State Circuits, vol. 26, pp. 32–40..

Ding L., Blaauw D. and Mazumder P., (2003) “Accurate crosstalk noise modeling for

early signal integrity,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,

vol. 22, no. 5, pp. 627–634.

Djordjevic A. R., Sarkar T. K., and Harrington R. F., (1987) “Time domain response

of multiconductor transmission lines,” Proceedings IEEE, vol. 75, pp. 743-764.

Dobberpuhl D.W., Witek R.T., Allmon R., Anglin R., Bertucci D., Britton S., Chao

L., Conrad R.A., Dever D.E., Gieseke B., Hassoun S.M.N., Hoeppner G.W.,

Kuchler K., Ladd M., Leary B.M., Madden L., McLellan E.J., Meyer D.R.,

Montanaro J., Priore D.A., Rajagopalan V., Samudrala S. and Santhanam S.,

160

(1992) “A 200-MHz 64-b dual-issue CMOS microprocessor”, IEEE Jour. of

Solid State Circuits, vol. 27, no. 11, pp. 1555-1567.

Dounavis A., Li X., Nakhla M. and Achar R., (1999) “Passive closed-form

transmission-line model for general-purpose circuit simulators,” IEEE Trans. on

Microwave Theory Tech., vol. 47, pp. 2450–2459.

Dounavis A., Achar R. and Nakhla M., (2000) “Efficient passive circuit models for

distributed networks with frequency-dependent parameters,” IEEE Trans. on

Advanced Packaging, vol. 23, pp. 382–392.

Dounavis A., Nakhla N., Achar R. and Nakhla M., (2003) “Delay extraction and

passive macromodeling of lossy coupled transmission lines,” in Proc. IEEE 12th

Topical Meeting on Electrical Performance of Electronic Packaging, Princeton,

NJ, pp. 295–298.

Duvall S., (2000) “Statistical circuit modeling and optimization," 5th International

Workshop on Statistical Metrology, 11 June 2000. Honolulu, HI, USA: IEEE,

pp. 56-63.

Edahiro M., (1993) “Delay minimization for zero-skew routing,” in Dig. Tech. Papers

IEEE Int. Conf. Computer-Aided Design, pp. 563-566.

Elgamel M.A., Tharmalingam K.S. and Bayoumi M.A., (2003) “Crosstalk noise

analysis in ultra deep submicrometer technologies,” in Proc. IEEE Computer

Society Annu. Symp .on VLSI (ISVLSI’2003), Tampa, FL, pp. 189-192.

El-Moursy M.A. and Friedman E.G., (2003a) “Shielding effect of on-chip

interconnect inductance,” in Proc. IEEE Great Lakes Symposium on VLSI, pp.

165–170.

El-Moursy M.A. and Friedman E.G., (2003b) “Inductive interconnect width

optimization for low power” Proc. IEEE Symp. Circuits and Systems, pp. 5.273-

5.276.

El-Moursy M.A. and Friedman E.G., (2004a) “Optimum wire sizing of RLC

interconnect with repeaters”, Integration, the VLSI Journal , Elsevier Pub.,

Netherlands, vol. 38, no. 2, pp. 205 – 225.

El-Moursy M.A. and Friedman E.G., (2004b) “Power characteristics of inductive

interconnect,” IEEE Trans. on Very Large Scale Integration (VLSI) Syst., vol.

12, no. 12, pp. 1295-1306.

161

El-Moursy M.A. and Friedman E.G., (2004c) “Exponentially tapered H-Tree clock

distribution networks”, Proc. IEEE International Symposium on Circuits and

Systems II, pp. 601–604.

El-Moursy M.A. and Friedman E.G., (2005a) “Shielding effect of on-chip

interconnect inductance,” IEEE Trans. on Very Large Scale Integration (VLSI)

Syst., vol. 13, no.3, pp. 396–400.

El-Moursy M.A. and Friedman E.G., (2005b) “Exponentially tapered H-Tree clock

distribution networks”, IEEE Trans. on Very Large Scale Integration (VLSI)

Syst., vol. 13, no.8, pp. 971–975.

El-Moursy M.A. and Friedman E.G., (2007) “Wire shaping of RLC interconnects”

Integration, the VLSI Journal, Elsevier Pub., Netherlands, vol. 40, no.4, pp. 461-

472.

Engelhardt M., Schindler G., Steinhogl W., Steinlesberger G., and Traving M., (2004)

“Investigation of nano interconnects for an early experimental assessment of

future interconnect challenges," in 2004 International Conference on Integrated

Circuit Design and Technology, 17-20 May 2004. Austin, TX, USA: IEEE, pp.

113-116.

Eo Y. and Eisenstadt W. R., (1993) “High-speed VLSI interconnect modeling based

on S-parameter measurement” IEEE Trans. on Comp., Hybrids, Manufact.

Technol., vol. 16, pp. 555–562.

Eo Y., Shim J. and Eisenstadt W. R., (2002a) “A traveling-wave-based waveform

approximation technique for the timing verification of single transmission

lines,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and

Systems, vol. 21, pp. 723–730.

Eo Y., Shin S., Eisenstadt W. R. and Shim J., (2002b) “Generalized traveling-wave-

based waveform approximation technique for the efficient signal integrity

verification of multi-coupled transmission line system,” IEEE Trans. on

Computer-Aided Design of Integrated Circuits and Systems, vol. 21, pp. 1489–

1497.

Ercken M., Leunissen L.H.A., Pollentier I., Patsis G.P., Constantoudis V. and

Gogolides E., (2004) “Effects of different processing conditions on line-edge

162

roughness for 193nm and 157nm resists,” in Proceedings of SPIE, vol. 5375, pp.

266–275.

Ertugrul D., (2006) “Effects of Interconnect Process Variations on Signal Integrity”,

Proceed. IEEE International SOC Conference, pp. 281-284.

Fabbro A.D., Franzini B., Croce L. and Guardiani C., (1995) “An assigned probability

technique to derive realistic worst-case timing models of digital standard cells,”

Design Automation Conference (DAC), pp. 702– 706.

Fayolle M. and Romagna F., (1997) “Copper CMP evaluation: Planarization issues,"

Micro-electronic Engineering Second European Workshop on Materials for

Advanced Metallization. MAM'97, vol. 37-38, pp. 135-141.

Frank D., Dennard R., Nowak E., Solomon P., Taur Y. and Wong H.-S., (2001)

“Device scaling limits of Si MOSFETs and their application dependencies,”

Proc. IEEE, vol. 89, no. 3, pp. 259–288.

Friedberg P., Cao Y., Cain J., Wang R., Rabaey J., and Spanos C., (2005a) “Modeling

within field gate length spatial variation for process-design co-optimization," in

Design and Process Integration for Microelectronic Manufacturing III,

Proceedings of the SPIE - The International Society for Optical Engineering,

vol. 5756. San Jose, CA, USA: SPIE-Int. Soc. Opt. Eng, pp.178-188.

Friedberg P., Cao Y., Cain J., Wang R., Rabaey J. and Spanos C., (2005b) “Modeling

within-die spatial correlation effects for process-design co-optimization," in

Proceedings. 6th International Symposium on Quality Electronic Design, San

Jose, CA, USA: IEEE Comput. Soc, pp. 516-521 BN- 0 7695 2301 3.

Gasteier M., Munch M. and Glesner M., (1998) “Generation of interconnect

topologies for communication synthesis,” in Proc. Design, Automation and Test

in Europe, pp. 36 – 42.

Gattiker A., Nassif S., Dinakar R. and Long C., (2001) “Timing yield estimation from

static timing analysis,” International Symposium on Quality Electronic Design

(ISQED), pp. 437–442.

Ginneken L. P., (1990) “Buffer placement in distributed RC-tree networks for

minimal Elmore delay,” in Proc. IEEE Int. Symp. Circuits Syst., pp. 865–868.

163

Goodnick S. M., Ferry D. K., Wilmsen C.W., Liliental Z., Fathy D. and Krivanek O.

L., (1985) “Surface roughness at the Si(100) - SiO interface,” Phys. Rev. B, vol.

32, pp. 8171-8186.

Griffith R. and Nakhla M., (1990) “Time-domain analysis of lossy coupled

transmission lines,” IEEE Trans. on Microwave Theory Tech., vol. 38, pp. 1480-

1487.

Guillaumond J., Arnaud L., Mourier T., Fayolle M., Pesci O., and Reimbold G.,

(2003) “Analysis of resistivity in nano-interconnect: full range (4.2-300 k)

temperature characterization," in IEEE International Interconnect Technology

Conference, Burlingame, CA, USA: IEEE, pp. 132-4. 115

Gupta R., Tutuianu B. and Pileggi L.T., (1997) “The Elmore delay as a bound for RC

trees with generalized input signals”, IEEE Trans. on Computer-Aided Design of

Integrated Circuits and Systems, vol. 16, no. 1, pp. 95-104.

Hao Yu, and Lei He, (2005) “Staggered twisted-bundle interconnect for crosstalk and

delay reduction,” in Proc. International Symposium on IEEE Quality of

Electronic Design, pp. 682 – 687.

Hara T., Namiki K., and Shimura Y., (2004) “Low resistivity copper interconnection

layers," in 2004 7th International Conference on Solid-State and Integrated

Circuits Technology Proceedings, vol.1. Beijing, China: IEEE, 2005, pp. 514-

519.

Havemann R.H. and Hutchby J.A., (2001) “High performance interconnects: An

integration overview”, Proceed. IEEE, vol. 89, no. 5, pp. 586-601.

He L., Chang N., Lin S. and Nakgawa O. S., (1999) “An efficient inductance

modeling for on-chip interconnects”, in Proc. Custom Integrated Circuits

Conference, pp. 457-460.

He L. and Lepak K.M., (2000) “Simultaneous shield insertion and net ordering for

capacitive and inductive coupling minimization,” IEEE/ACM International

Symposium on Physical Design, San Diego, CA, pages: 55-60.

Hiraki M., Kojima H., Misawa H., Akazawa T. and Hatano Y., (1995) “Data-

dependent logic swing internal bus architecture for ultra low power LSI’s,”

IEEE J. of Solid State Circuits, vol. 30, no.4, pp. 397-402.

164

Huang H.Y. and Chen S.L., (2004) “Interconnect accelerating techniques for sub-100-

nm gigascale systems,” IEEE Trans. on Very Large Scale Integration (VLSI)

Systems, vol. 12, no. 11, pp. 1192-1200.

Huang X., Restle P., Bucelot T., Cao Y., King T.J. and Hu C., (2003) “Loop-based

interconnect modeling and optimization approach for multigigahertz clock

network design,” IEEE Jour. of Solid State Circuits, vol. 38, no. 3, pp. 457-463.

ITRS- International Technology Roadmap for Semiconductors. Semiconductor

Industry Association. [Online]. Available: http://public.itrs.net

Ismail Y. I., Friedman E. G. and Neves J. L., (1999a) “Dynamic and short circuit

power of CMOS gates driving lossless transmission lines,” IEEE Trans. on

Circuits and Systems I: Fundamental Theory and Applications, vol. CAS-46, no.

8, pp. 950-961.

Ismail Y. I., Friedman E. G. and Neves J. L., (1999b) “Figures of merit to characterize

the importance of on-chip inductance,” IEEE Trans. on Very Large Scale

Integration (VLSI) Systems, vol.7, pp.442-449.

Ismail Y. I., Friedman E. G. and Neves J. L., (2000a) “Equivalent Elmore delay for

RLC trees,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and

Systems, vol. 19, no. 1, pp.83-97.

Ismail Y. I. and Friedman E. G., (2000b) “Effects of inductance on the propagation

delay and repeater insertion in VLSI circuits,” IEEE Trans. on Very Large Scale

Integration (VLSI) Systems., vol. 8, pp. 195–206.

Ismail Y. I., Friedman E.G. and Neves J. L., (2001) “Exploiting the on-chip

inductance in high-speed clock distribution networks”, IEEE Trans. on Very

Large Scale Integration (VLSI) Systems, vol. 9, no. 6, pp. 963-973.

Ismail Y. I. and Friedman E. G., (2002) “DTT: Direct truncation of the transfer

function- an alternative to moment matching for tree structured interconnect,”

IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.

21, No. 2.

Izumikawa M. and Yamashina M., (1996) “A current direction sense technique for

multiport SRAM’s”, IEEE Jour. of Solid State Circuits, vol. 31, no. 4, pp. 546–

551.

165

Jaeger R. C., (2002) “Introduction to microelectronic fabrication”, 2nd ed., ser.

Modular series on solid state devices ; v. 5. Upper Saddle River, N.J.: Prentice

Hall, vol. 5.

Jan C.-H., Bielefeld J., Buehler M., Chikamane V., Fischer K., Hepburn T., Jain A.,

Jeong J., Kielty T., Kook S., Marieb T., Miner B., Nguyen P., Schmitz A.,

Nashner M., Scherban T., Schroeder B., Wang P.-H., Wu R., Xu J., Zawadzki

K., Thompson S. and Bohr M., (2003) “90 nm generation, 300 mm wafer low k

ild/cu interconnect technology," Proceedings of the IEEE International

Interconnect Technology Conference, pp. 15-17.

Jarrar A. and Taylor K., (2006) “On-Chip Variation and Timing Closure”, EDN,

http://www.edn.com/article/464316On_chip_variation_and_timing_closure.php)

.

Jarvis D. B., (1963) “The effects of interconnections on high-speed logic circuits,”

IEEE Trans. on Electron. Computers, vol. EC-10, pp. 476–48.

Jiang Q.-T., Tsai M.-H., and R. Havemann, (2001a) “Line width dependence of

copper resistivity," in Proceedings of the IEEE 2001 International Interconnect


Jiang Q.-T., Frank A., Havemann R., Parihar V., and Nowell M., (2001b)

“Optimization of annealing conditions for dual damascene cu microstructures

and via chain yields," in Symposium on VLSI Technology. Digest of Technical

Papers, Kyoto, Japan: Japan Soc. Appl. Phys, pp. 139-40.

Jin W., Yoon S., Eo Y. and Kim J., (2000) “Experimental characterization and

modeling of transmission line effects for high-speed VLSI circuits

interconnects,” IEICE Trans. on Electronics, vol. E83-c, no. 5, pp. 728–735.

Jin W., Eo Y., Eisenstadt W. R. and Shim J., (2001) “Fast and accurate quasi three-

dimensional capacitance determination of multilayer VLSI interconnects,” IEEE

Trans. on Very Large Scale Integration (VLSI) Systems., vol. 9, pp. 450–460.

Kahng A.B. and Muddu S., (1996) “Efficient gate delay modeling for large

interconnect loads,” IEEE Multi-Chip Module Conf., 1996, pp. 202–207.

Kahng A. B. and Muddu S., (1997) “An analytical delay model for RLC

interconnects,” IEEE Trans. on Computer-Aided Design of Integrated Circuits

and Systems, vol. 16, no. 12, pp. 1507-1514.

166

Kahng A. and Pati Y., (1999) “Subwavelength lithography and its potential impact on

design and eda," in Proceedings 1999 Design Automation Conference, New

Orleans, LA, USA, pp. 799-804.

Kamon, M., Ttsuk M.J. and White J.K., (1994) “FASTHENRY: A multipole-

accelerated 3-D inductance extraction program,” IEEE Trans. on Microwave

Theory and Techniques, pp 1750-1758.

Kang S.M. and Leblebici Y., (2003) CMOS Digital Integrated Circuits— Analysis

and Design, TMH, New York,

Kapur P. and Saraswat K.C., (2002) "Optical interconnects for future high

performance integrated circuits", Physica E: Low-dimensional Systems and

Nanostructures, vol. 16, no.3/4, pp.620-7.

Kapur P., J McVittie., and Saraswat K., (2001) “Realistic copper interconnect

performance with technological constraints," in Proceedings of the IEEE 2001

International Interconnect Technology Conference, Burlingame, CA, USA:

IEEE, pp. 233-235.

Kaushik B.K., Sarkar S. and Agarwal R.P., (2006) “Width optimization of global

inductive VLSI interconnects” Microelectronics International, Emerald Pub.

U.K., vol. 23, no. 1, pp.26–30.

Kaushik B.K., Sarkar S., Agarwal R.P. and Joshi R.C., (2007a) “Crosstalk reduction

by voltage scaling in global VLSI interconnects” Journal of Active and Passive

Devices, USA, vol. 2, no. 3, pp.199-221.

Kaushik B.K., Sarkar S., Agarwal R.P. and Joshi R.C., (2007b) “Voltage scaling-A

novel approach for crosstalk reduction in global VLSI interconnects”

Microelectronics International, Emerald Pub. U.K., vol.24, no. 1, pp. 40 – 45.

Kaushik B. K., Goel S. and Rauthan G., (2007c) “Future VLSI interconnects: optical

fiber or carbon nanotube – a Review” Microelectronics International, Emerald

Pub. U.K., vol. 24, no. 2, pp.53 – 63.

Kaushik B.K., Sarkar S. and Agarwal R.P., (2007d) “Waveform Analysis and Delay

Prediction for a CMOS Gate Driving RLC Interconnect Load”, Integration, the

VLSI Journal, Elsevier Pub., Netherlands, vol. 40, no. 4, pp. 394-405.

167

Kaushik B.K., Sarkar S., Agarwal R.P. and Joshi, R.C., (2007e) “Effect of Line

Resistance and Driver Width on Crosstalk in Coupled VLSI Interconnects”

Microelectronics International, Emerald Pub. U.K., vol. 24, no. 3, pp. 42-45.

Kaushik B.K., (2007f) “Delay and Cross Talk Analysis for a CMOS Driven Global

Inductive VLSI Interconnects" PhD Thesis submitted at Indian Institute of

Technology-Roorkee.

Kaushik B.K. and Sarkar S., (2008) “Crosstalk Analysis for a CMOS-Gate-Driven

Coupled Interconnects,” IEEE Trans. on Computer-Aided Design of Integrated

Circuits and Systems, vol. 27, no. 6, pp. 1150-1154.

Kaushik B.K., Sarkar S., Agarwal R.P. and Joshi R.C., (2009) “Crosstalk Analysis of

Simultaneously Switching Interconnects” International Journal of Electronics,

Taylor and Francis (UK), vol. 96, no.10, pp. 1095-1114.

Khellah M.M. and Elmasry M.I., (1999) “Low power design of high capacitive

CMOS circuits using a new charge sharing scheme,” in Proc. IEEE

International Solid State Circuits Conf., pp. 286-287.

Kil J., Gu J. and Kim C. H., (2006) “A High-Speed Variation-Tolerant Interconnect

Technique for Sub-Threshold Circuits using Capacitive Boosting” Proceedings

International Symposium on Low Power Electronics and Design (ISLPED), pp.

67-72.

Kitada H., Suzuki T., Kimura T., Kudo H., Ochimizu H., Okano S., Tsukune A., Suda

S., Sakai S., Ohtsuka N., Tabira T., Shirasu T., Sakamoto M., Matsuura A.,

Asada Y. and T. Nakamura, (2007) “The influence of the size effect of copper

interconnects on RC delay variability beyond 45nm technology," in Proceedings

of the IEEE 2007International Interconnect Technology Conference, 4-6 June

2007. Burlingame, CA, USA: IEEE.

Kleveland B., Qi Z., Madden L., Furusawa T., Dutton R.W., Horowitz M.A. and

Wong S.S., (2002) “High-frequency characterization of on-chip digital

interconnects”, IEEE Jour. of Solid State Circuits, vol. 37, no. 6, pp. 716-725.

Kondo S., Sakuma N., Homma Y., Goto Y., Ohashi N., Yamaguchi H. and Owada N.,

(2000) “Complete-abrasive-free process for copper damascene interconnection,"

in Proceedings of the IEEE International Interconnect Technology Conference,.

Burlingame, CA, USA: IEEE, pp. 253-255.121

168

König A. and Glesner M., (1994) “VLSI-implementation of associative memory

systems for neural information processing” In VLSI for Neural Networks and

Artificial Intelligence, Jose G. Delgado-Frias, William R.~Moore (Eds.), Plenum

Press New~York and London.

Kopcsay G.V., Krauter B., Widiger D., Deutsch A. Rubin B.J. and Smith H.H., (2002)

“A comprehensive 2-D inductance modeling approach for VLSI interconnects –

frequency – dependent extraction and compact circuit model synthesis”, IEEE

Trans. on Very Large Scale Integration (VLSI) Systems, vol. 10, no. 6, pp. 695-

711.

Kowalczyk A., Adler V., Amir C., Chiu F., Choon Chug, De Lange, W., Dubler S.,

Yuefei Ge, Ghosh S., Tan Hoang, Hu R., Baoqing Huang, Kant S., Kao Y.S.,

Cong Khieu, Kumar S., Chung Lau, Lan Lee, Liebermensch A., Xin Liu, Malur

N., Hiep Ngo, Sung-Hun Oh, Orginos I., Pini D., Shih L., Sur B., Tzeng A., Vo

D., Zambare S. and Jin Z., (2001) “First generation MAJC dual

microprocessor,” in Proc. IEEE International Solid State Circuits Conf., San

Francisco, CA, pp. 236–237.

Krauter B., Gupta R., Willis J. and Pileggi L.T., (1995) “Transmission line synthesis,”

in Proc. IEEE Design Automation Conf., pp. 358-363.

Krauter B. and Mehrotra S., (1998) “Layout based frequency dependent inductance

and resistance extraction for on-chip interconnect timing analysis,” in Proc.

IEEE Design Automation Conf., June 1998, pp. 303-308.

Kreupl F., Graham A.P., Duesberg G.S., Steinhögl W., Liebau M., Unger E. and

Hönlein W., (2002) “Carbon nanotubes in interconnect applications”,

Microelectronic Engineering, Elsevier Pub., Netherlands, vol. 64, no.1-4, pp.

399-408.

Krstic A., Wang L. C., Cheng K. T. and Liou, J. J., (2003) “Diagnosis of delay defects

using statistical timing models,” IEEE VLSI Test Symposium (VTS), pp. 339–

344.

Kumar D.V., Narasimhulu K., Reddy P.S., Shojaei-Baghini M., Sharma D.K., Patil

M.B. and Rao V.R., (2005) “Evaluation of the impact of layout on device and

analog circuit performance with lateral asymmetric channel MOSFETs”, IEEE

Trans. on Electron Devices, vol. 52, no. 7, pp. 1603 – 1609.

169

Kurd N., Barkarullah J. S., Dizon R. O., Fletcher T. D., and Madland P. D., (2001) “A

multigigahertz clocking scheme for the pentium® 4 microprocessor,” IEEE

Jour. Solid-State Circuits, vol. 36, pp. 1647–1653.

Kuznetsov D. and Schutt-Aine J.E., (1996) “Optimal transient simulation of

transmission lines,” IEEE Trans. on Circuits and Syst., vol. 43, no. 2, pp. 110–

121.

Lakshminarayanan S., Wright P. and Pallinti J., (2003) “Electrical characterization of

the copper CMP process and derivation of metal layout rules," IEEE

Transactions on Semiconductor Manufacturing, vol. 16, no. 4, pp. 668-676.

Lampropoulos M., Al-Hashimi B.M. and Rosinger P., (2004) “Minimization of

crosstalk noise, delay and power using a modified bus invert technique” in Proc.

of Design, Automation and Test in Europe Conference and Exhibition, vol. 2,

pp.1372 - 1373.

Lepak K.M., Luwandi I. and He L., (2001) “Simultaneous shield insertion and net

ordering under explicit RLC noise constraint,” in Proc. Design Automation

Conf., pp. 199–202.

Leunissen L., Ercken M. and Patsis G., (2005) “Determining the impact of statistical

fluctuations on resist line edge roughness," Microelectronic Engineering, vol.

78-79, pp. 2-10.

Leunissen L., Zhang W., Wu W., and Brongersma S., (2006) “Impact of line edge

roughness on copper interconnects," Journal of Vacuum Science and

Technology B (Microelectronics and Nanometer Structures), vol. 24, no. 4, pp.

1859-1862.

Levenson L., (1989) “Grain boundary diffusion activation energy derived from

surface roughness measurements of aluminum thin films," Applied Physics

Letters, vol. 55, no. 25, pp. 2617-2619.

Li B., Sullivan T. D., Lee T. C., and Badami D., (2004) “Reliability challenges for

copper interconnects," Microelectronics Reliability, vol. 44, no. 3, pp. 365-380.

Lillis J., Cheng C.K. and Lin T.T.Y., (1996) “Simultaneous routing and buffer

insertion for high performance interconnect,” in Proc. 6th Great Lakes Symp.

VLSI, pp. 7-12.

170

Lin S. and Kuh. E.S., (1990) “Transient simulation of lossy interconnect,” in Proc.

29th ACM/IEEE Design Automation Conf., pp. 81-86.

Liou J. J., Krstic A., Wang L. C. and Cheng K. T., (2002) “False path-aware statistical

timing analysis and efficient path selection for delay testing and timing

validation,” Design Automation Conference (DAC), pp. 566–569.

Liu D. and Svensson C., (1993) “Trading speed for low power by choice of supply

and threshold voltages,” IEEE Jour. of Solid State Circuits, vol. 28, pp. 10-17.

Liu Y., Nassif S. R., Pileggi L. T. and Strojwas A. J., (2000) “Impact of interconnect

variations on the clock skew of a gigahertz microprocessor,” Design Automation

Conference (DAC), pp. 168–171.

Lopez, G.G. (2009) “The Impact of Interconnect Process Variations and Size Effects

for Gigascale Integration” Phd. Thesis submitted at School of Electrical and

Computer Engineering, Georgia Institute of Technology, USA.

Lopez G., Murali R., Sarvari R., Bowman K., Davis J., and Meindl J., (2007) “The

impact of size effects and copper interconnect process variations on the

maximum critical path delay of single and multi-core microprocessors," in

Proceedings of the IEEE 2007 International Interconnect Technology

Conference, 4-6 June 2007. Burlingame, CA, USA: IEEE, 2007.

Lu X., Li Z., Qiu W., Walker D. M. H. and Shi W., (2004) “Longest path selection for

delay test under process variation,” Asia and South Pacific Design Automation

Conference, pp 99-103.

Lu X., Li Z., Qiu W., Walker D. M. H., Shi W., (2004) “PARADE: PARAmetric

Delay Evaluation under Process Variation”, International Symposium on Quality

Electronic Design (ISQED), pp. 276-280.

Lu Y., Banerjee K., Celik M. and Dutton R.W., (2001) “A fast analytical technique

for estimating the bounds of on-chip clock wire inductance,” in Proc. IEEE

Custom Integrated Circuits Conf., pp. 241–244.

Luman H. and Davis J., (2004) “Inductance enhancement in global clock distribution

net-works," in Proceedings of the IEEE 2004 International Interconnect

Technology Conference, Burlingame, CA, USA: IEEE, 2004, pp. 119-121.

Luong G. M. and Walker D. M. H., (1996) “Test generation for global delay faults,”

Proceedings of the International Test Conference (ITC), pp. 433–442.

171

Maheshwari A. and Burleson W., (2004) “Differential current-sensing for on-chip

interconnects,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems,

vol. 12, no.12, pp. 1321-1329.

Maheshwari S.K. and Visweswaran G.S., (2000) “A 3.3 V compatible 2.5 VTTL to

CMOS bi-directional I/O buffer,” in Proc. IEEE 13th Int. Conf. VLSI Design,

pp.484-487.

Malavasi E., Zanella S., Uschersohn C. Min J., Misheloff M. and Guardiani, C.,

(2002) “Impact analysis of process variability on clock skew,” International

Symposium on Quality Electronic Design (ISQED), pp. 129–132.

Manney S., Nakhla M. S. and Zhang Q. J., (1992) “Time domain analysis of non

uniform frequency dependent high-speed interconnects,” in Proc. IEEE Int.

Conf. Computer-Aided Design, pp. 449–453.

Marom H. and Eizenberg M., (2006) “The effect of surface roughness on the

resistivity increase in nanometric dimensions," Journal of Applied Physics, vol.

99, no. 12, pp. 123 705-1.

Massoud Y., Majors S., Bustami T. and White J., (1998) “Layout techniques for

minimizing on-chip interconnect self-inductance,” in Proc. ACM/IEEE Design

Automation Conf., pp 566-571.

Masuda H., Ohkawa S., Kurokawa A. and Aoki M., (2005) “Challenge: Variability

characterization and modeling for 65- to 90-nm processes,” in Proc. IEEE

Custom Integrated Circuits Conference (CICC), pp. 593–599.

Mead C.A. and Rem M., (1979) “Cost and performance of VLSI computing

structures,” IEEE Jour. of Solid State Circuits, vol. SC-14, no.2, pp. 455-462.

Mead C.A. and Rem M., (1982) “Minimum propagation delays in VLSI,” IEEE Jour.

of Solid State Circuits, vol. SC-17, no.4, pp. 773-775.

Mehrotra V. and Boning D., (2001) “Technology scaling impact of variation on clock

skew and interconnect delay," in Proceedings of the IEEE 2001 International

Interconnect Technology Conference, Burlingame, CA, USA: IEEE, pp. 122-

124.

Mehrotra V., Sam S. L., Boning D., Chandrakasan A., Vallishayee R. and Nassif S.,

(2000) “A methodology for modeling the effects of systematic within-die

172

interconnect and device variation on circuit performance,” Design Automation

Conference, pp. 172–175.

Meindl J. D., Venkatesan R., Davis J. A., Joyner J., Naeemi A., Zarkesh-Ha P., Bakir

M., Mule T., Kohl P. A. and Martin K. P., (2001) “Interconnecting device

opportunities for gigascale integration (GSI),” in Proc. IEEE Int. Electron

Devices Meeting (IEDM) Tech. Dig., pp. 525–528.

Mekie J., Chakraborty S. and Sharma D.K., (2004) “Evaluation of pausible clocking

for interfacing high speed IP cores in GALS framework” in Proc. IEEE 17th

International Conference on VLSI Design, pp. 559 – 564.

Mekie J., Chakraborty S., Venkataramani G., Thiagarajan P.S. and Sharma D.K.,

(2006) “Interface design for rationally clocked GALS systems” in Proc. 12th

IEEE International Symp. on Asynchronous Circuits and Systems, pp. 12.

Mezhiba A. V. and Friedman E. G., (2002) “Inductive properties of high-performance

power distribution grids,” in IEEE Trans. on Very Large Scale Integration

(VLSI) Systems, vol. 10, no.6, pp. 762–776.

Mezhiba A. V. and Friedman E. G., (2004) “Impedance characteristics of power

distribution grids in nanoscale integrated circuits” in IEEE Trans. on Very Large

Scale Integration (VLSI) Systems, vol. 11, 1148-1155.

Mishra Divya, Mishra Shailendra, Agnihotry Praggya and Kaushik B.K., (2010)

“Crosstalk Scenario in Multiline VLSI Interconnects” International Journal of

Recent Trends in Engineering [ISSN 1797-9617], Academy Publishers, Finland,

vol. 3 no. 4, pp. 80-83.

Mistry K., Allen C., Auth C., Beattie B., Bergstrom D., Bost M., Brazier M., Buehler

M., Cappellani A., Chau R., Choi C.-H., Ding G., Fischer K., Ghani T.,Grover

R., Han W., Hanken D., Hattendorf M., He J., Hicks J., Huessner R., Ingerly D.,

Jain P., James R., Jong L., Joshi S., Kenyon C., Kuhn K., Lee K., Liu H.,Maiz

J., B McIntyre., Moon P., Neirynck J., Pae S., Parker C., Parsons D., Prasad C.,

Pipes L., Prince M., Rarade P., Reynolds T., Sandford J., Shifren L., Sebastian

J., Seiple J., Simon D., Sivakumar S., Smith P., Thomas C., Troeger T.,

Vandervoorn P.,Williams S., and Zawadzki K., (2007) “A 45nm logic

technology with high-k+ metal gate 118 transistors, strained silicon, 9 cu

173

interconnect layers, 193nm dry patterning, and 100% pb-free packaging,"

Technical Digest - International Electron Devices Meeting, IEDM, pp. 247-250.

Mizuno T., Okumtura J. and Toriumi A., (1994) “Experimental study of threshold

voltage fluctuation due to statistical variation of channel dopant number in

MOSFET’s,” IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 2216–2221.

Mohsen A.M., and Mead C.A., (1979) “Delay-time optimization for driving and

sensing of signals on high-capacitance paths of VLSI systems,” IEEE Jour. of

Solid State Circuits, vol. 14, no.2, pp. 462-470.

Moll F., Roca M. and Rubio A., (1998) “Inductance in VLSI interconnection

modeling,” in IEEE Proc. Circuits Devices Syst., vol. 145, no.3, pp. 175-179.

Murgan T., Schlachta C., Petrov M., Indrusiak L., Garcia A., Glesner M. and Reis R.,

(2004a) “Accurate capture of timing parameters in inductively-coupled on-chip

interconnects” in Proc. IEEE Symposium on Integrated Circuits and Systems

Design, pp.117 – 122.

Murgan T., Ortiz A. Garcia, Schlachta C., Zimmer H., Petrov M., and Glesner M.,

(2004b) “On timing and power consumption in inductively coupled on-chip

interconnects” in Proc. Lecture Notes in Comp Science (Springer), Intl.

Workshop on Power and Timing Modeling, Optimization and Simulation, pp.

819-828

Murgan T., Ortiz, A.G., Petrov M. and Glesner M., (2005a) “A linear model for high-

level delay estimation in VDSM on-chip interconnects” in Proc. IEEE

International Symposium on Circuits and Systems, vol. 2,pp. 1078 – 1081.

Murgan T. and Glesner M., (2005b) “Limits for switching power consumption in

encoded interconnects,” in Proc. IEEE International Symposium on Signals,

Circuits and Systems, vol. 1, pp.27 – 30.

Naeemi A., Venkatesan R. and Meindl J.D., (2003) “Optimal global interconnects for

GSI,” in IEEE Trans. on Electron Devices, vol. 50, no.4, pp. 980-987..

Naeemi A., Davis J. A., and Meindl J. D., (2004) “Compact physical models for

multilevel interconnect crosstalk in gigascale integration (GSI)”, in IEEE Trans.

on Electron Devices, vol. 51, no. 11, pp. 1902-1912..

174

Naeemi A., Sarvari R. and Meindl J.D., (2005) "Performance comparison between

carbon nanotube and copper interconnects for gigascale integration (GSI)",

IEEE Electron Device Letters, vol. 26, no.2, pp. 84-86..

Nagaraj N.S., Poras B. and Cyrus C., (2001) “Crosstalk Noise Verification in Digital

Designs with Interconnect Process Variations” Procd. 14th IEEE International

conference on VLSI, pp 365.

Nagel L. W., (1975) “SPICE2: A computer program to simulate semiconductor

circuits”. Univ. California, Berkeley, CA, Tech. Report ERL-M520.

Nakagome Y., Itoh K., Isoda M., Takeuchi K. and Aoki M., (1993) “Sub-IV swing

internal bus architecture for future low-power ULSI’s,” IEEE Jour. of Solid

State Circuits, vol. 28, no.4, pp. 414-419.

Nakhla N., Ruehli A., Nakhla M. and Achar R., (2004) “Simulation of coupled

interconnects using waveform relaxation and transverse partitioning,” in Proc.

IEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging,

Portland, OR, pp. 25–28.

Nakhla N. M., Ruehli A. E., Nakhla M. S. and Achar R., (2006) “Simulation of

coupled interconnects using waveform relaxation and transverse partitioning,”

IEEE Trans. on Advanced Packaging, vol. 29, no. 1, pp. 78-87.

Narasimha U., Abraham B. and Nagaraj N.S., (2006) “Statistical Analysis of

Capacitance Coupling Effects on Delay and Noise”, International Symposium

on Quality Electronic Design (ISQED), pp. 795-800.

Narasimhulu K., Sharma D.K. and Rao V.R., (2003) “Impact of lateral asymmetric

channel doping on deep submicrometer mixed-signal device and circuit

performance” IEEE Trans. on Electron Devices, vol. 50, no. 12, pp. 2481 –

2489.

Nassif N., Desai M.P. and Hall D.H., (1998) “Robust Elmore delay models suitable

for full chip timing verification of a 600MHz CMOS microprocessor”, in Proc.

35th ACM/IEEE Design Automation Conf., pp 230-235.

Nassif S., (1998) “Within-chip variability analysis," in International Electron Devices

Meeting, Technical Digest, San Francisco, CA, USA: IEEE, pp. 283-286.

175

Nassif S., (2000a) “Delay variability: sources, impacts and trends," in IEEE

International Solid-State Circuits Conference. Digest of Technical Papers, San

Francisco, CA, USA: IEEE, pp. 368-369.

Nassif S., (2000b) “Modeling and forecasting of manufacturing variations," in 5th

International Workshop on Statistical Metrology, Honolulu, HI, USA: IEEE, pp.

2-10.

Nassif S., (2001a) “Modeling and forecasting of manufacturing variations," in

Proceedings of the ASP-DAC. Asia and South Pacific Design Automation

Conference, Yokohama, Japan: IEEE, pp. 145-149.

Nassif S., (2001b) “Modeling and analysis of manufacturing variations in Proceedings

of the IEEE 2001 Custom Integrated Circuits Conference” San Diego, CA,

USA: IEEE, pp. 223-228.

Neiroukh S. and Song X., (2005) “Improving the process-variation tolerance of digital

circuits using gate sizing and statistical techniques," in Proceedings. Design,

Automation and 111 Test in Europe, vol. Vol. 1. Munich, Germany: IEEE

Comput. Soc, pp. 294-299.

Nekili M. and Savaria Y., (1992) “Optimal methods of driving interconnections in

VLSI circuits”, in Proc. IEEE International Symposium on Circuits and Systems

(ISCAS), pp. 21-23.

Nekili M. and Savaria Y., (1993) “Parallel regeneration of interconnection in VLSI &

ULSI circuits”, in Proc. IEEE International Symposium on Circuits and

Systems, Chicago, vol. 3, pp.2023-2026.

Odabasioglu A., Celik M. and Pileggi L.T., (1997) “PRIMA: Passive reduced order

interconnect macromodeling algorithm,” in Proc. IEEE International

Conference on Computer-Aided Design, pp. 58–65.

Odabasioglu A., Celik M. and Pileggi L.T., (1998) “PRIMA: Passive reduced order

interconnect macromodeling algorithm,” IEEE Trans. on Computer-Aided

Design of Integrated Circuits and Systems, vol. 17,no.8, pp. 645–654.

Okada K., Yamaoka K., and Onodera H., (2003) “A statistical gate delay model for

intra-chip and inter-chip variabilities," in Conference of Asia and South Pacific

Design Automation 2003, Kitakyushu, Japan: IEEE, pp. 31-36.

176

Orshansky M., Milor L., Chen P., Keutzer K. and Hu C., (2000) “Impact of

systematic spatial intra-chip gate length variability on performance of high-

speed digital circuits,” International Conference on Computer-Aided Design

(ICCAD), pp.62–67.

Ousterhout J. K., (1984) “Switch-level delay models for digital MOS VLSI,” in Proc.

Design Automation Conf. , pp. 542–548.

Palusinski O. and Lee A., (1989) “Analysis of transients in nonuniform and uniform

multiconductor transmission lines,” IEEE Trans. on Microwave Theory and

Technique, pp. 127–138.

Pan J., Li P., Wijekoon K., Tsai S. and Redeker F., (1999) “Copper CMP integration

and time dependent pattern effect," in Proceedings of the IEEE International

Interconnect Technology Conference, San Francisco, CA, USA: IEEE, pp.164-

166.

Pandey S., Glesner M. and Mühlhäuser M., (2005) “Performance aware on-chip

communication synthesis and optimization for shared multi-bus based

architecture” in Proc. of ACM 18th Annual Symposium on Integrated Circuits

and System Design SBCCI, pp. 230 – 235.

Park T., Tugbawa T., Boning D., Chung J., Hymes S., Muralidhar R., Wilks B.,

Smekalin K., and Bersuker G., (1999) “Electrical characterization of copper

chemical mechanical polishing," in CMP-MIC, Santa Clara, CA, pp. 184-191.

Paul C., (1994) Analysis of Multiconductor Transmission Lines. New York: Wiley.

Penfield P. and Rubinstein J., (1981) “Signal delay in RC tree networks”, in Proc of

IEEE Design Automation Conf., pp. 613-617.

Pereira G., Lubaszewski M., Andrade A., Jr. Balen T.R., Azais F. and Renovell M.,

(2005) “Testing the interconnect networks and I/O resources of field

programmable analog arrays” in Proc. 23rd IEEE VLSI Test Symposium, pp. 389

– 394.

Plombon J., Andideh E., Dubin V., and Maiz J., (2006) "Influence of phonon,

geometry, impurity, and grain size on copper line resistivity," Appl. Phys. Lett.

(USA), vol. 89, no. 11, pp. 113 124-1.

177

Poechmueller P., Sharma G.K. and Glesner M., (1991) “A CAD tool for designing

large, fault-tolerant VLSI arrays”, in Proc. First Great Lakes Symposium on

VLSI, pp. 132 – 137.

Priore D. A., (1993) “Inductance on silicon for sub-micron CMOS VLSI,” in Proc.

IEEE Symp. VLSI Circuits, pp. 17–18.

Pucknell D.A. and Eshraghian K. (1988) Basic VLSI Design: Systems and Circuits,

Prentice-Hall, Inc., USA.

Pullela S., Menezes N. and Pillage L. T., (1993) “Reliable nonzero skew clock trees

using wire width optimization,” in Proc. 30th ACM/IEEE Design Automation

Conf, pp. 165-170.

Qian J., Pullela S. and Pillage L.T., (1994) “Modeling the effective capacitance for

the RC interconnect of CMOS gates,” IEEE Trans. on Computer-Aided Design

of Integrated Circuits and Systems, vol. CAD-13, pp. 1526-1535.

Rabaey J. M., (1996) Digital Integrated Circuits, A Design Perspective. Englewood

Cliffs, NJ: Prentice-Hall.

Renovell M., Figueras J. and Zorian Y., (1997) “Test of RAM-based FPGA:

methodology and application to the interconnect” in Proc. 15th IEEE VLSI Test

Symposium, pp. 230 – 237.

Renovell M., Portal J.M., Figueras J. and Zorian Y., (1998) “Testing the interconnect

of RAM-based FPGAs” in Proc. IEEE Design & Test of Computers, vol. 15, no.

1, pp.45 – 50.

Renovell M., Portal J.M., Figueras J. and Zorian Y., (1999) “Testing the configurable

interconnect/logic interface of SRAM-based FPGA's” in Proc. Design,

Automation and Test in Europe Conference and Exhibition, pp. 618 – 622.

Renovell M., Faure P., Prinetto P. and Zorian Y., (2002) “Testing the unidimensional

interconnect architecture of symmetrical SRAM-based FPGA” in Proc. IEEE

International Workshop on Electronic Design, Test and Applications, pp. 297 –

301.

Romagna F. and Fayolle M., (1997) “Copper CMP evaluation: slurry chemical effect

on planarization," in European Workshop Materials for Advanced Metallization.

MAM'97 Abstracts Booklet, Villard de Lans, France: Soc. Francaise du Vide, pp.

32-35.

178

Rosa E. B., (1908) “The self and mutual inductances of linear conductors,” Bull.Nat.

Bur. Stand., vol. 4, no. 2, pp. 301–344.

Rossello J.L. and Segura J., (2004) “A compact propagation delay model for deep-

submicron CMOS gates including crosstalk”, in Proc. IEEE Design, Automation

and Test in Europe Conference and Exhibition, vol.2, pp. 954-959.

Rossello J.L. and Segura J., (2006) “A compact model to identify delay faults due to

crosstalk” in Proc Design, Automation and Test in Europe, vol. 1, pp. 5.

Rubinstein J., Penfield P. and Horowitz M.A., (1983) “Signal delay in RC tree

networks,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and

Systems, vol. 2, no.3, pp. 202-211.

Ruehli A.E., (1972) “Inductance calculations in a complex integrated circuit

environment,” IBM Journal of Research and Development, pp 470-481.

Sai-Halasz G.A., (1995) “Performance trends in high-end processors”, Proceed. of

IEEE, vol.84, pp. 20-36.

Sakurai T., (1983) “Approximation of wiring delay in MOSFET LSI,” IEEE Jour.

Solid-State Circuits, vol. SC-18, pp. 418–426.

Sakurai T., (1993) “Closed form expressions for interconnection delay, coupling and

crosstalk in VLSI’s,” IEEE Trans. on Electron Devices, vol. 40, pp. 118–124.

Sarvari R. and Meindl, J., (2003) “On the study of anomalous skin effect for GSI

interconnections," in IEEE International Interconnect Technology Conference,

Burlingame, CA, USA: IEEE, pp. 42-44.

Sato T., Cao Y., Agarwal K., Sylvester D. and Hu C., (2003) “Bidirectional closed-

form transformation between on-chip coupling noise waveforms and

interconnect delay-change curves,” IEEE Trans. Comput.-Aided Des. Integr.

Circuits Syst., vol. 22, no. 5, pp. 560–572.

Sauter S., Cousinard D., Thewes R., Schmitt-Landsiedel D. and Weber W., (1999)

“Clock skew determination from parameter variations at chip and wafer level,"

in Proceedings of the 4th International Workshop on Statistical Metrology

(1999 IWSM)” Kyoto, Jpn: IEEE, Piscataway, NJ, USA, pp. 7-9.

Sauter S., Schmitt-Landsiedel D., Thewes R. and Weber W., (2000a) “Effect of

parameter variations at chip and wafer level on clock skews," IEEE

Transactions on Semiconductor Manufacturing, vol. 13, no. 4, pp. 395-400,

179

Sauter S., Rein A., Frerichs M., Schmitt-Landsiedel D., Thewes R. and Weber W.,

(2000b) “Measurement and simulation of interconnect capacitance variations,"

in 5th International Workshop on Statistical Metrology, Honolulu, HI,

USA:IEEE, pp. 64-67.

Schindler G., Steinhogl W., Steinlesberger G., Traving M. and Engelhardt M.,

(2003a) “Scaling of parasitics and delay times in the backend-of-line,"

Microelectronic Engineering, vol. 70, no. 1, pp. 7-12, 2003.

Schindler G., Steinlesberger G., Engelhardt M., and Steinhogl W., (2003b) “Electrical

characterization of copper interconnects with end-of-roadmap feature sizes,"

Solid-State Electronics 3rd International Workshop on Ultimate Integration of

Silicon, Munich, Germany, vol. 47, no. 7, pp. 1233-1236.

Schindler G., V. Klandzevski, G. Steinlesberger, W. Steinhogl, M. Traving, and M.

En-gelhardt, (2003) “A morphology study of copper and aluminum

interconnects," in Advanced Metallization Conference (AMC), pp. 213-217.

Schindler G., Meyer M., Steinlesberger G., Engelhardt M., and Zschech E., (2004)

“Grain orientation of copper nano interconnects," in Advanced Metallization

Conference 2003 (AMC 2003), pp. 205-211.

Sharifzadeh S., Koehler J., Owen A. and Shott J., (1989) “Using simulators to model

trans-mitted variability in ic manufacturing," IEEE Transactions on

Semiconductor Manufacturing, vol. 2, no. 3, pp. 82-93.

Shepard K. L. and Narayanan V., (1996) “Noise in deep submicron digital design,” in

Proc. International Conference Computer-Aided Design, pp. 524–531.

Shih T., Yao C., Huang L., Jang S., Yu C. and Liang M., (2001) “Pattern dependence

study of copper planarization using linear polisher for 0.13/spl mu/m

applications," in Proceedings of the IEEE International Interconnect


Shimada M., Moriyama M., Ito K., Tsukimoto S. and Murakami M., (2006)

“Electrical resistivity of polycrystalline cu interconnects with nano-scale

linewidth," Journal of Vacuum Science and Technology B (Microelectronics and

Nanometer Structures), vol. 24, no. 1, pp. 190-4.

Shin S., Eo Y., Eisenstadt W. R. and Shim J., (2004) “Analytical models and

algorithms for the efficient signal integrity verification of inductance-effect-

180

prominent multicoupled VLSI circuit interconnects” IEEE Trans. on Very Large

Scale Integration Systems, vol. 12, no. 4, pp.395-407.

Shoji M., (1996) High-Speed Digital Circuits. Reading, MA: Addison- Wesley.

Sim S.P., Krishnan S., Petranovic D.M., Arora N.D., Lee K. and Yang C.Y., (2003)

“A unified RLC model for high speed on-chip interconnects,” IEEE Trans. on

Electron Devices, vol. 50, no. 6, pp. 1501-1510.

Sim S.P., Lee K., Cary Y. and Yang C.Y., (2002) “High-frequency on chip inductance

model,” IEEE Electron Device Letters, vol. 23, no. 12, pp. 740-742.

Sinha A. and Chowdhury S., (1999) “Mesh-structured on-chip power/ground: design

for minimum inductance and characterization for fast R, L extraction,” Proc. of

IEEE Custom Integrated Circuits, pp 461-464.

Sinha, A., Gupta, S.K. and Breuer M.A., (2002) “Validation and test issues related to

noise induced by parasitic inductances of VLSI interconnects”, IEEE Trans. on

Advanced Packaging, vol. 25, no. 3, pp. 329-339.

Sorooshian J., DeNardis D., Charns L., Li Z., Shadman F., Boning D., Hetherington

D. and Philipossian A., (2004) “Arrhenius characterization of ILD and copper

CMP processes," Journal of the Electrochemical Society, vol. 151, no. 2, pp. 85-

88.

Srivastava A., Sylvester D. and Blaauw D., “Statistical analysis and optimization for

VLSI: Timing and Power”. USA: Springer 2005, X, 279 p. 105 illus., ISBN:

978-0-387-25738-9

Srivastava N. and Banerjee K., (2005) “Performance analysis of carbon nanotube

interconnects for VLSI applications”, in Proc. IEEE International Conference

on Computer-Aided Design, pp.383 – 390.

Stan M.R. and Burleson W.P., (1995) “Bus-invert coding for low-power I/O,” IEEE

Trans. on Very Large Scale Integration Systems, vol.3, no. 1, pp. 49–58.

Steinhogl W., Schindler G., Steinlesberger G., and Engelhardt M., (2002) “Size-

dependentresistivity of metallic wires in the mesoscopic range," Physical

Review B (Condensed Matter and Materials Physics), vol. 66, no. 7, pp. 075

414-1.

Steinhogl W., Schindler G., Steinlesberger G., M. Traving, and M. Engelhardt, (2004)

“Impact of line edge roughness on the resistivity of nanometer-scale

181

interconnects," Micro-electronic Engineering European Workshop on Materials

for Advanced Metallization, vol. 76, no. 1-4, pp. 126-130.

Steinhoegl W., Schindler G., and Engelhardt M., (2005) “Unraveling the mysteries

behind size effects in metallization systems," Semiconductor International, vol.

28, no. 5, pp. 34-38.

Steinhogl W., Schindler G., Steinlesberger G., Traving M., and Engelhardt M., (2005)

“Comprehensive study of the resistivity of copper wires with lateral dimensions

of 100 nm and smaller," Journal of Applied Physics, vol. 97, no. 2, pp. 023 706-

1.

Steinlesberger G., Engelhardt M., Schindler G., Steinhogl W., Von Glasow A., Mosig

K. and Bertagnolli E., (2002a) “Electrical assessment of copper damascene

interconnects down to sub-50 nm feature sizes," Microelectronic Engineering

European Work-shop on Materials for Advanced Metallization, vol. 64, no. 1-

4,120pp. 409-16.

Steinlesberger G., Von Glasow A., Engelhardt, Schindler M. G., Honlein W., Holz M.

and E. Bertagnolli, (2002b) “Copper damascene interconnects for the 65 nm

technology node: a first look at the reliability properties," in Proceedings of the

IEEE International Interconnect Technology Conference, Burlingame, CA,

USA: IEEE, pp. 265-267.

Steinlesberger G., Engelhardt M., Schindler G., Steinhogl W., Traving M., Honlein

W., and Bertagnolli E., (2003) “Impact of annealing on the resistivity of

ultrafine Cu damascene interconnects," in Materials, Technology and Reliability

for Advanced Interconnects and Low-k Dielectrics - Symposium, San Francisco,

CA, USA: Mater. Res. Soc, pp. 379-384.

Steinlesberger G., Schindler G., Engelhardt M., Steinhogl W., and Traving M., (2004)

“Aluminum nano interconnects," in Proceedings of the IEEE 2004 International

Interconnect Technology Conference, Burlingame, CA, USA: IEEE, pp.51-3.

Su H. , Liu F., Devgan A., Acar E. , Nassif S., (2003) “Full chip leakage

estimation considering power supply and temperature variations,” in

International Symposium on Low Power Electronics and Design (ISLPED).

182

Sun T., Yao B., Warren A., Kumar V., Barmak K. and K. R. Coffey, (2008)

“Resistivity size effect in encapsulated Cu thin films," 2008 IEEE International

Interconnect Technology Conference, IITC, pp. 141-143.

Sylvester D. and Shepard K. L., (2001) "Electrical integrity design and verification for

digital and mixed-signal systems-on-a-chip ", Tutorial - Intl. Conf. Computer

Aided Design.

Sylvester D. and Wu C., (2001) “Analytical modeling and characterization of deep-

submicrometer interconnect,” Proceed. of IEEE, vol.89, no.5, pp. 634-664.

Tam S., Rusu S., Desai U.N., Kim R., Zhang J. and Young I., (2000) “Clock

generation and distribution for the first IA-64 microprocessor,” IEEE Jour. Solid

State Circuits, vol. 35, no.11, pp. 1545-1552.

Tang K. T. and Friedman E. G., (1999) "Interconnect coupling noise in CMOS VLSI

circuits", in Proc. International Symp. on Physical Design, pp. 48-53.

Teene A., Davis B., Castagnetti R., Brown J. and Ramesh S., (2005) “Impact of

interconnect process variations on memory performance and design," in

Proceedings. 6th International Symposium on Quality Electronic Design, San

Jose, CA, USA: IEEE Comput. Soc, pp. 694-699.110

Tokei Z., Roussel P., Stucchi M., Versluijs J., Ciofi, L., Carbonell L., Beyer G.,

Cockburn A., Agustin M., and Shah K., (2009) “Impact of LER on BEOL

dielectric reliability: a quantitative model and experimental validation," IEEE

International Interconnect Technology Conference - IITC, pp. 228-230.

Traving M., Schindler G., Steinlesberger G., Steinhogl W., and Engelhardt M., (2003)

“Nanoscale diffusion barriers for copper metallization," Semiconductor

International, vol. 26, no. 8, pp. 73-78.

Tseng H.P., Scheffer L. and Sechen C., (1998) “Timing and crosstalk driven area

routing,” in Proc. Design Automation Conf., pp. 378–381.

Tyagi S., Alavi M., Bigwood R., Bramblett.T, Brandenburg J., Chen W., Crew B., M.

Hussein, P. Jacob, C. Kenyon, C. Lo, B. Mcintyre, Z. Ma, P. Moon, P. Nguyen,

Rumaner L., Schweinfurth R., Sivakumar S., Stettler M., Thompson S., Tufts B.,

Xu J., Yang S., and M. Bohr, (2000) “A 130 nm generation logic technology

featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnects,"

Technical Digest -International Electron Devices Meeting, pp. 567-570.

183

Van Olmen J., List S., Tokei Z., Carbonell L., Brongersma S., Volders H., Kunnen E.,

Heylen N., Ciofi I., Khandelwal A., Gelatos J., Mandrekar T. and Boelen P.,

(2007) “Cu resistivity scaling limits for 20nm copper damascene lines," in


Conference, Burlingame, CA, United States, pp. 49-51.

Venkatesan R., Davis J. A. and Meindl J. D., (2003a) “Compact distributed RLC

interconnect models—Part III: Transients in single and coupled lines with

capacitive load termination,” IEEE Trans. on Electron Devices, vol. 50, pp.

1081–1093.

Venkatesan R., Davis J. A. and Meindl J. D., (2003b) “Compact distributed RLC

interconnect models—Part IV: Unified models for time delay, crosstalk, and

repeater insertion”, IEEE Trans. on Electron Devices, vol. 50, pp. 1094–1102.

Verma K.G., Kaushik B. K. and Singh R., (2009) “Effects of process variation in

VLSI interconnects - a technical review” Microelectronics International, vol.

26, No. 3, pp. 49-55.

Verma K.G. and Kaushik B.K., (2010a) “Effect of process based oxide thickness

variation on the delay of DIL system using Monte Carlo analysis” International

Journal of Recent Trends in Engineering. Academy Publishers, Finland, vol. 3,

no. 4, pp. 27-31.

Verma K.G., Kaushik B.K. and Singh Raghuvir, (2010b) “Propagation delay variation

due to process induced threshold voltage variation” Communications in

Computer and Information Science, 1, Information and Communication

Technologies, Springer, vol.101, Part 3, pp. 520-524.

Verma K.G., Kaushik B.K. and Singh R., (2010c) "Propagation delay variations under

process deviation in driver interconnect load system," International Conference

on Advances in Recent Technologies in Communication and Computing

(ARTCom), vol., no., pp.408-410.

Vittal A. and Marek-Sadowska M., (1997) “Crosstalk reduction for VLSI”, IEEE

Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 16,

no. 3, pp.290-298.

184

Vittal A., Chen L.H., Marek-Sadowska M., Wang K. P. and Yang S., (1999)

“Crosstalk in VLSI interconnections,” IEEE Trans. on Computer-Aided Design

of Integrated Circuits and Systems, vol. 18, no. 12, pp. 1817–1824.

Vrudhula S., Wang J. M. and Ghanta P., (2006) “Hermite Polynomial Based

Interconnect Analysis in the Presence of Process Variations” IEEE Trans. on

CAD of Integrated Circuits And Systems, vol. 25, No. 10, pp. 2001-2011.

Wann D.F. and Franklin M.A., (1983) “Asynchronous and clocked control structures

for VLSI based interconnection networks,” IEEE Trans. on Computers, vol. C-

32, no.3, pp. 284-293.

Warnock J. D., Keaty J. M., Petrovick J., Clabes J. G., Kircher C. J., Krauter B. L.,

Restle P. J., Zoric B. A., and Anderson C. J., (2002) “The circuit and physical

design of the power4 microprocessor," IBM Journal of Research and

Development, vol. 46, no. 1, pp. 27-51.

Wei B.Q., Vajtai R. and Ajayan P.M., (2001) “Reliability and current carrying

capacity of carbon nanotubes”, Appl. Phys. Lett. vol. 79, no. 8, pp. 1172-1174.

Weste N.H.E. and Eshraghian K., (1992) Principles of CMOS VLSI Design, 2nd

edition, Addision-Wesley Publishing Company, “Empirical Delay Models”, pp.

213.

Wisniewski M. Y., Yashchin E., Franch R. L., Conrady D. P., Maynard D. N.,

Fiorenza G. and Noyan I. C., (2003a) “The physical design of on-chip

interconnections," IEEE Transactions on Computer-Aided Design of Integrated

Circuits and Systems, vol. 22, no. 3, pp. 254-276.113

Wisniewski M., Yashchin E., Franch, R. Conrady D., Fiorenza G. and Noyan I.,

(2003b) “Estimating the efficiency of collaborative problem-solving, with

applications to chip design," IBM Journal of Research and Development, vol.

47, no. 1, pp. 77-88.

Wong S.C., Lee T.G.Y., Ma D.J., and Chao C.J., (2000) “An empirical three-

dimensional crossover capacitance model for multilevel interconnect VLSI

circuits,” IEEE Trans. on Semiconductor Manufacturing, vol. 13, No.2, pp. 219-

227.

185

Wood J., Edwards T. C. and Lipa S., (2001) “Rotary traveling-wave oscillator arrays:

A new clock technology,” IEEE Jour. of Solid-State Circuits, vol. 36, pp. 1654–

1665.

Wyatt Jr. J.L., (1985) “Signal delay in RC mesh networks,” IEEE Trans. on Circuits

and Systems, vol. CAS-32, no. 5, pp. 507-510.

Xiong J., Tam K., and He L., (2005) “Buffer insertion considering process variation,"

in Proceedings. Design, Automation and Test in Europe” vol. Vol. 2. Munich,

Germany: IEEE Comput. Soc, pp. 970-975.

Yacoub G.Y., Pham H. and Friedman E.G., (1988) “A system for critical path

analysis based on back annotation and distributed interconnect impedance

models,” Microelectronic Journal, Elsevier Pub., Netherlands, vol. 18, no. 3, pp.

Yamaguchi A., Ryuzaki D., Takeda K. and Kawada H., (2009) “Evaluation of line-

edge roughness in Cu/low-k interconnect patterns with CD-SEM," IEEE

International Interconnect Technology Conference - IITC, pp. 225-227.

Yamauchi H. and Matsuzawa A., (1996) “A signal swing suppressing strategy for

power and layout area savings using time multiplexed differential data transfer

scheme”, IEEE Jour. Solid-State Circuits, vol..31, no.9, pp.1285-1294,

Yamaguchi H., Ohashi N., Imai T., Torii K., Noguchi J., Fujiwara T., Saito T., Owada

N., Homma Y., Kondo S. and Hinode K., (2000) “A 7 level metallization with

cudamascene process using newly developed abrasive free polishing," in


Conference, Burlingame, CA, USA: IEEE, pp. 264-266.

Yamaguchi K., Fukaishi M., Sakamoto T., Akiyama N. and Nakamura K., (2001) “A

2.5-GHz four-phase clock generator with scalable no-feedback-loop

architecture,” IEEE Jour. Solid-State Circuits, vol. 36, pp. 1666–1672.

Yang S., Ahmed S., Arcot B., Arghavani R., Bai P., Chambers S., Charvat P., Cotner

R., Gasser R., Ghani T., Hussein M., Jan C., Kardas C., Maiz J., Mc-Gregor P.,

McIntyre B., Nguyen P., Packan P., Post I., Sivakumar S., Steigerwald J., Taylor

M., Tufts B., Tyagi S., and Bohr M., (1998) “A high performance 180 nm

generation logic technology," International Electron Devices Meeting.

Technical Digest, pp. 197-200.117

186

Yin L. and He L., (2001) "An efficient analytical model of coupled on-chip RLC

interconnects", in Proc. Asia South Pacific Design Automation Conference, pp.

385-390.

Ymeri H., Nauwelaers B. and Maex K., (2002) “On the frequency-dependent line

capacitance and conductance of on-chip interconnects on lossy silicon

substrate,” Microelectronics International, Emerald Pub. U.K., vol. 19, no. 1,

pp. 11-18.

Yu C., Liu H.Y. and Spanos C.J., (1996) “Patterning tool characterization by causal

variability decomposition," IEEE Trans. on Semi. Manuf., vol. 9, no. 4, pp. 527-

535.

Zaage S. and Groteluschen E., (1993) “Characterization of the broadband

transmission behavior of interconnections on silicon substrates,” IEEE Trans. on

Components, Hybrids, and Manufacturing Technology, vol. 16, no. 7, pp. 686-

691.

Zanella S., Nardi A., Neviani A., Quarantelli M., Saxena S., and Guardiani C., (2000)

“Analysis of the impact of process variations on clock skew," IEEE

Transactions on Semiconductor Manufacturing, vol. 13, no. 4, pp. 401-407.

Zarkesh-Ha P. and Meindl J., (1999) “Optimum chip clock distribution networks," in


Conference, San Francisco, CA, USA: IEEE, pp. 18-20.112

Zarkesh-Ha P., Mule T. and Meindl J., (1999) “Characterization and modeling of

clock skew with process variations," in Proceedings of the IEEE 1999 Custom

Integrated Circuits Conference, San Diego, CA, USA: IEEE, pp. 441-444.

Zarkesh-Ha P., Lakshminarayanan S., Doniger K., Loh W., and Wright P., (2003a)

“Impact of interconnect pattern density information on a 90 nm technology

ASIC design flow," in ISQED 2003: 4th International Symposium on Quality

Electronic Design, San Jose, CA, USA: IEEE Comput. Soc, pp. 405-409.

Zarkesh-Ha P., Wright P., Lakshminarayanan S., Cheng C.-C., Loh W., and Lynch

W., (2003b) “Backend process optimization for 90 nm high-density ASIC

chips," in IEEE International Interconnect Technology Conference, Burlingame,

CA, USA:IEEE, pp. 123-125.

187

Zheng J., Hahm Yeon-Chang, Tripathi V.K. and Weisshaar A., (2000) “CAD-oriented

equivalent-circuit modeling of on-chip interconnects on lossy silicon substrate”

IEEE Trans. on Microwave Theory and Techniques, vol. 48, no. 9, pp.1443 –

1451.

Zhou B. and Khouas A., (2005) “Measurement of delay mismatch due to process

variations by means of modified ring oscillators,” in IEEE International

Symposium on Circuits and Systems (ISCAS), pp. 5246–5249.

Zhou D., Su S., Tsui F., Gao D.S. and Cong J.S., (1994) “A simplified synthesis of

transmission lines with a tree structure” Analog Integrated Circuits and Signal

Processing, Kluwer Academic Publishers, vol. 5, no.1, pp. 19-30.

188

LIST OF PUBLICATIONS

INTERNATIONAL JOURNALS

1. K. G. Verma, B. K. Kaushik and R. Singh, “Effects of Process Variation in

VLSI Interconnects- a Technical Review” Microelectronics International,

Emerald Pub. U.K., vol. 26, no. 3, pp. 49-55, 2009. (Available on line at

http://www.emeraldinsight.com)

2. K. G. Verma, B. K. Kaushik, “Effect of Process Based Oxide Thickness

Variation on the Delay of DIL System Using Monte Carlo Analysis,”

International Journal of Recent Trends in Engineering. Academy Publishers,

Finland, vol. 3, no. 4, pp. 27-31, 2010.

(http://www.searchdl.org/journal/IJRTET2010)

3. K. G. Verma, B. K. Kaushik and R. Singh, “Interconnect Based Process

Variation in VLSI,” International Journal of Computer Science &

Management System (IJCSMS-2009), vol. 1, no. 1, pp. 19-26, June 2009.

4. K. G. Verma, Brajesh Kumar Kaushik and Raghuvir Singh, “Analysis of

Propagation Delay Deviation under Process Induced Threshold Voltage

Variation,” International Journal of Computer Applications, vol. 17, no. , pp.,

March 2011. (Available on line at http://www.ijcaonline.org).

http://www.emeraldinsight.com/�

http://www.searchdl.org/journal/IJRTET2010�

http://www.ijcaonline.org/�

189

5. K. G. Verma, Brajesh Kumar Kaushik and R .Singh, “Process Variation Issues

in VLSI Interconnects-A Case Study,” Journal of Active and Passive Devices,

USA, (Accepted). (http://www.oldcitypublishing.com/JAPED/JAPED.html)

6. K. G. Verma, B. K. Kaushik, and R. Singh, “Deviation in Propagation Delay

Due to Process Induced Driver Width Variation” International Journal on

Electronics and Communication Technology (IJECT), vol. 2, iss. 1, March

2011. (Available on line at http://iject.org/).

7. K. G. Verma, Brajesh Kumar Kaushik and Raghuvir Singh, “Monte Carlo

Analysis of Propagation Delay Deviation due to Process Induced Line Parasitic

Variations in Global VLSI Interconnects,” International Journal of Computer

Applications vol. 20, no. 1, pp. 26-29, April 2011. (Available on line at

http://www.ijcaonline.org).

8. K. G. Verma, Brajesh Kumar Kaushik and Raghuvir Singh, “Propagation Delay

Variation due to Process Induced Threshold Voltage Variation”

Communications in Computer and Information Science, Information and

Communication Technologies -2010, Springer, vol.101, Part 3, pp. 520-524,

2010. (Available at http://www.springerlink.com/content/j438523317971424/

INTERNATIONAL CONFERENCES

9. K. G. Verma, B. K. Kaushik, R. Singh, "Propagation Delay Variations under

Process Deviation in Driver Interconnect Load System," International

Conference on Advances in Recent Technologies in Communication and

Computing (ARTCom- 2010), pp. 408-410, 16-17 Oct. 2010. (Available on line

at IEEE Xplore®).

http://www.oldcitypublishing.com/JAPED/JAPED.html�

http://iject.org/�

http://www.ijcaonline.org/�

http://www.springerlink.com/content/j438523317971424/�

190

10. B. K. Kaushik, K. G. Verma, “Process Variations in Driver Interconnect Load

System-Keynote Address," International Conference on Recent Trends in

Information, Telecommunication and Computing (ITC- 2010), pp.xvi-xx, 12-

13 March 2010. (Available on line at IEEE Xplore®).

11. K. G. Verma, B. K. Kaushik, Raghuvir Singh, and Brijesh Kumar, “Monte Carlo

Analysis of Propagation Delay due to Process Induced Line Parasitic Variations

in VLSI Interconnects,” Proc. IEEE Int. Conf. on Emerging Trends in

Networks and Computer Communications (ETNCC- 2011), Udaipur, 22nd -24th

April, 2011. (Available on line at IEEE Xplore®).

12. K. G. Verma, B. K. Kaushik, Raghuvir Singh, and Brijesh Kumar, “Propagation

Delay Deviations Due to Process Tempted Driver Width Variations,” Proc.

IEEE Int. Conf. on Emerging Trends in Networks and Computer

Communications (ETNCC-2011), Udaipur, 22nd -24th April, 2011. (Available

on line at IEEE Xplore®).

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