EEWeb Pulse - Issue 52, 2012

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    PULSE

    EEWeb.c

    Issue

    June 26, 20

    Beth CooperNASA GlennResearch Center

    Electrical Engineering Commun

    EEWeb

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    TABLE OF CONTENTS

    Beth CooperNASA GLENN RESEARCH CENTER

    The Development of NASA Auditory

    Demonstrations Laboratory for Testing

    of Hearing Protection DevicesBY JEFF SCHMITT, BETH COOPER AND DAVID NELSON

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    Interview with Beth Cooper - NASA Internal Agency Hearing Conservation Consultant

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    INTERVIEW

    Co perBeth

    NASA Glenn ResearchInternal Agency HearingConservation Consultant

    How did you get intoengineering and when didyou start?

    I became involved in engineering

    through acousticsthe science of

    sound. When I was a child, I guess

    you could say that I had some

    musical talent. I was able to pick out

    melodies on the piano at a young

    age, and I taught myself to play

    several musical instruments. As I

    got older, I would write harmoniesfor tunes that I learned in school

    or camp. This interest propelled

    me into an involvement in music,

    and that was how I spent most of

    my time in high school. The focus

    of many school projects was the

    science of music studying how

    it was produced and why people

    perceived music the way they did.

    I was especially interested in the

    relationships between sounds,

    which is one aspect of the disciplineof music theory.

    When I started to apply to colleges I

    very nearly became a music theory

    major. It wasnt until the very last

    minute that I realized that there was

    a name for what I really liked, which

    was the physics of musicintervals,

    tones, and those kinds of things. Thetechnical field that encompasses

    all of that is acoustics. So, to find

    a college, I did what, today, would

    be an Internet searchI went to

    the libraryand found that there

    were four schools in the country that

    offered undergraduate programs

    in acoustics, one of them being the

    University of Hartford. The program

    there was a Bachelor of Science in

    Engineering (B.S.E.) program inAcoustics and Music. Students in

    this program took most of the same

    coursework as a music performance

    major at the conservatory, Hartt

    College of Music, as well as the

    core coursework of an engineering

    major. It sounded like the perfect

    program for me, so thats what I did.

    For the first two years of my college

    education I was a double major in

    music and acoustics.

    I eventually switched my major

    to mechanical engineering, only

    because the B.S.E. program at

    that time was not accredited, and

    I didnt want to have any concerns

    about the validity of my degree

    while job hunting later. But I still

    took all the same courses over and

    above what was required for myB.S.M.E. degree, so I also earned

    the equivalent of a B.S.E. in Music

    and Acoustics.

    From there I went on to Penn

    State because it had the most

    acclaimed program in the country

    that awarded graduate degrees in

    acoustics. The program was very

    broad: it covered everything from

    underwater acoustics to speech

    science and audiology. I hadhoped to study musical acoustics,

    but I needed to focus on an area

    where there was ample funding

    for assistantships. I modified my

    academic approach to emphasize

    speech science and speech

    processing, which was probably

    about as close as I could get to

    musical acoustics. The connection

    is really human perception, which

    links speech and hearing sciencesto musical acoustics. So its not hard

    to imagine the link between that and

    being a hearing conservationist,

    which is what I am now.

    Where did you frst go to workafter you graduated?

    I worked in private industry for about

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    INTERVIEW

    four years, but it wasnt what I really

    wanted to do, since my ambition was

    always to work for the government

    in a research capacity. It took a

    while to get an acoustics position at

    NASA, but as soon as I heard there

    was an opening at Glenn Research

    Center in Cleveland, thats where I

    went. Ive worked here for nearly my

    entire professional careerabout

    25 years.

    Can you tell us about whatyou do at NASA?

    Since Ive been at NASA Ive had

    four major assignments, each

    lasting from about five to seven

    years. My first assignment was

    on a team doing research on the

    noise produced by jet nozzles

    from aircraft exhaust engines. The

    program included both analytical

    and experimental research; the

    work I was doing specifically

    involved testing scale models of

    exhaust nozzles in wind tunnels and

    other laboratories.

    As a typical researcher in a wind

    tunnel, you have a fairly cyclic work

    routine. You take data, analyze the

    data, then write a paper and go to

    a conference to present your work.

    But because I had a slightly different

    interest area than most of the other

    people in my group, I was asked if

    I would take a look at a community

    noise problem that had developed

    with one of our test facilities, where

    researchers were doing aircraft

    engine component testing in an

    open parking lot. Obviously, it was

    generating a lot of noise, and since

    the testing was being done during

    third shift to save money on power,

    some residents of the nearby

    communities had begun to regularly

    call and complain. It had become a

    pretty significant community noise

    issue that was threatening the

    success of the research program,

    and so my boss said, We know that

    human perception of sound is one

    of your interests, so will you take a

    look at what we can do to solve this

    problem? One thing led to another,

    Over the span of mycareer, I have cometo be acknowledged

    as NASAs noiseperson, and now

    my responsibility isto advise our senior

    environmentalhealth officer and theoccupational health

    personnel at our fieldcenters about noise

    exposure issues,particularly relatedto noise control and

    hearing conservation

    program policies.

    and we ended up building a

    geodesic-dome-shaped enclosure

    that severely reduced the noise that

    could be heard in the surrounding

    community. The facility also has an

    anechoic interior lining that keeps

    the noise from reverberating inside

    the dome; this allows the space

    to be used for noise emission

    measurements on various aircraft

    components.

    After leading the acoustical design

    and managing the construction

    of this facility, I realized that I

    didnt want to go back to being a

    researcher. I really enjoyed facility

    design and noise control, and I

    had, at that point, developed a bit

    of a reputation as a noise control

    person, leading me to take on

    other smaller noise control-related

    tasks. Eventually, I knew I wanted tocontinue working on noise control

    projects, which inspired me to find

    my next home in the Health and

    Safety organization.

    During my interview for that

    position, the person interviewing

    mewho would eventually become

    my bosssaid, We would love to

    have you work on noise control,

    but its really just one element of

    a hearing conservation programand needs to be approached that

    way. Would you like to manage the

    hearing conservation program?

    So I did that from about 1994 to

    1999, establishing the hearing

    conservation program here at NASA

    Glenn Research Center. It ended up

    being a very high-quality program,

    and I think that is partly because

    there was a significant emphasis

    on noise control, which typicallygets neglected in the context of

    a classical program. As part of

    that assignment, I implemented

    an aggressive campaign of noise

    control solutions for our test facilities

    and infrastructure buildings. I

    also developed a number of novel

    programs that NASA has since

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    INTERVIEW

    adopted on an agency-wide basis.

    By 1999 the Glenn hearing

    conservation program was

    mature and had developed a lot

    of momentum, so I started lookingfor a new challenge. Just like in my

    previous assignment, I realized that

    one capability we needed, but didnt

    have, was an anechoic chamber

    dedicated to performing small-

    scale testing of equipment destined

    for the International Space Station.

    All flight hardware is required to

    go through a series of qualification

    tests. One of those tests verifies

    that the equipment doesnt maketoo much noise, with the goal of

    preventing hearing loss as well as

    ensuring a comfortable working

    environment for the astronauts.

    Payload developers here at NASA

    Glenn were always looking for quiet

    places where they could take the

    required noise measurements on

    their science payloads to get them

    qualified for flight. It was pretty

    clear that we needed a proper test

    facility to do that, so I proposed to

    the engineering organization that I

    come and work for them and help

    build one.

    It took about a year to find funding to

    build the chamber, but another year

    later, we opened a commercially

    viable state-of-the-art anechoic test

    laboratory that was specifically

    designed to accommodate a

    couple of major projects that were

    planned for the International Space

    Station. I led the facility design and

    managed the construction project

    and then became the manager ofthe lab. The lab provided acoustic

    emissions testing services, but we

    also developed and provided other

    related services, like low-noise

    design consulting and education

    for payload developers on how to

    design low-noise flight hardware.

    This acoustic emissions testing

    laboratory later earned accreditation

    by the National Voluntary Laboratory

    Accreditation Program for the tests

    we performed; we also became the

    only laboratory accredited for the

    specific test required for acoustic

    emissions verification of large flight

    racks for the International Space

    Station.

    Over the span of my career, I

    have come to be acknowledged

    as NASAs noise person, and

    now my responsibility is to advise

    our senior environmental health

    officer and the occupational health

    personnel at our field centers about

    noise exposure issues, particularlyrelated to noise control and hearing

    conservation program policies. My

    fourth major assignmentthe work

    that Im primarily involved in right

    nowis focused on developing

    programs and resources for

    helping employees identify and

    purchase equipment that is

    inherently quiet. This approach

    also has a component that requires

    our in-house designers to design

    equipment and systems that are

    quiet. It makes good economic

    sense to avoid being in a situation

    where you are spending money

    to fix pre-existing noise problems

    while purchasing and building

    new equipment that may produce

    the very same problems. Noise

    emissions should be considered

    along with other criteria when

    youre purchasing or designing

    equipment. This is the essence of aBuy-Quiet program, and NASAs is

    leading the way in the United States.

    Do you have any tips forelectronics hardwaredesigners regarding noise?

    Electronic components dont usually

    contribute much noise themselves.

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    INTERVIEW

    But if you have to provide cooling or

    ventilation for a piece of equipment

    youre designing, you should

    think about those requirements at

    the earliest possible stage of the

    design process to avoid creating

    unnecessary noise that then

    requires the addition of noise control

    treatments that will consume space

    and may create other problems for

    your design. Often, the worst noise

    problems are the result of airflow

    issues. Anything that restricts airflow

    or causes very sharp turns or bends

    in the airflow path is going to cause

    noise. This noise is very hard to get

    rid of after the fact, but it can belargely prevented if the challenge

    is addressed early enough in the

    design.

    Another piece of advice for designers

    is to be very explicit and intentional

    in demanding low-noise-emission

    products from manufacturers. NASA

    has developed a tool for Buy Quiet

    Purchasing called the Buy Quiet

    Roadmap. Basically, the Roadmap

    is an online process that helps end

    users identify an appropriate noise

    emission criterion for a particular

    item to be purchased and then to

    evaluate the total long-term cost of

    different manufacturers products

    that may differ in both cost and noise

    emission. The heart of the Roadmap

    is a calculation that quantifies the

    total long-term cost of occupational

    exposure to various noise levels.

    Its the only tool of its kind, and

    it has been commended by the

    Occupational Safety and Health

    Administration (OSHA) and the

    National Institute for Occupational

    Safety and Health (NIOSH) as

    well as international regulatory

    agencies, and it has been adopted

    by a number of organizations in

    the private sector. The Roadmap,

    as well as a number of other free

    and publicly available NASAresources that support hearing loss

    prevention, can be accessed here.

    I am a strong advocate of Buy

    Quiet Purchasing, and I encourage

    people to use this resource.

    What are some of the toolsand approaches that youuse when diagnosing noiseproblems?

    Its important to look at the boththe frequency spectrum and the

    temporal characteristics of the

    sound, not just the volume (how loud

    the sound is), because the quality

    of the sound is very important to

    human perception, especially

    when it comes to providing a work

    environment that will be comfortable

    and foster productivity. NASAs noise

    emission and noise exposure limits

    are based on volume, but even if we

    satisfy those requirements, there

    can still be tones, hissing, rumbling

    or intermittent events that attract

    attention and cause discomfort and

    annoyance. A piece of equipment

    can produce an acceptable

    volume of sound, but if the

    spectrum has a significant high or

    low frequency component or one or

    more tones, it will likely be perceived

    as annoying or distracting. For

    this reason, you have to look at theentire spectrum as well as how it

    varies with time. This approach,

    which considers the sound quality,

    is more comprehensive and

    considers human factors that are

    not accommodated by the classical

    approach that addresses only the

    volume of the noise emission.

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    The Development of NASAAuditory Demonstrations

    Laboratory for Testing ofHearing Protection Devices

    Editors Note: The following article is a synthesis of

    two separate papers written by members of the ADL

    development team and arranged by an EEWeb editor

    [1] [2]. Each paper can be accessed in the References

    section.

    This article will outline the design of NASAs Auditory

    Demonstration Laboratory (ADL) for performing

    Real Ear Attenuation at Threshold (REAT) measurements

    to meet industry standards for the Noise Reduction

    Rating (NRR) of personal hearing protective devices.

    The calculation of an NRR implies highly specific testrequirements for the conditions in the room in which the

    test is conducted, the signal generation equipment and

    the processing of normal hearing subjects. This article

    will also profile the development of NASAs REATMaster

    software as well as its key features that will aid in signal

    generation and data acquisition for all REAT testing

    facilities in which the system is employed.

    Development of REAT Facility

    The development of the REAT test facility began in the fall

    of 2007. The primary goals of this project were to design

    Figure 1: NASA GRC Auditory Demonstration Laboratory controlroom with NASA REATMaster and Stimulus Presentation SoundSystem Rack (left) and Auditory Demonstrations Rack (right).

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    PROJECT

    an acoustic test chamber and signal generation systemfor REAT testing in accordance with industry standards.

    In order that the human test subject receive accurate data

    from signal generations, the laboratory needed to have

    very low background noise levels to accommodate the

    hearing of a normal hearing subject. At the same time,

    it needed to be equipped with a sound system capable

    of generating spacecraft launch-level sound fields to test

    the performance of the hearing protection technology.

    The site for the ADL was chosen in the basement of a

    building with ideal conditions for conducting low-noise

    acoustic measurementsconcrete walls, a roof cap and

    heavy steel doors. A pre-fabricated ETS-Lindgren steel

    reverberant test chamber was installed in the basement

    laboratory to ensure a diffuse sound field environment.

    Both the test chamber and isolation within the basement

    provided optimal sound isolation levels at relevant test

    frequencies with the addition of several massive silencer

    units to reduce external effects on the testing.

    With the establishment of an isolated and secure ADL

    chamber came the need for the proper sound system to

    perform the signal generation tests. The sound system

    would need to create diffuse field sound pressure levels

    to allow REAT testing and provide stable gain and high

    slew rate output throughout. With these specifications,it would also need to operate quietly when operated at

    full gain while at the same time attenuating any system-

    generated noises. For the ADL, we implemented a three-

    channel system, utilizing ElectroVoiceT251 horn loaded

    loudspeakers that are driven by a Bryston 6BSST power

    amplifier. This amplifier delivers 300 watts per channel,

    more than 110 dB of signal to noise ratio and has a fixed

    gain input setting that facilitates system calibration. This

    system also employs a high-power 30 dB L-pad load box

    attenuator that achieves the desired low background

    noise levels needed for testing. If very high sound levels

    are needed, the L-pad attenuator can be removed.

    For the signal generation and data acquisition technology

    in the ADL, we selected the National Instruments PXI

    platform. We used two NI PXI-4461 dual-input, dual-

    output, 24-bit digital dynamic signal acquisition (DSA)

    and generation modules, which provided three channels

    of signal generation and uncorrelated outputs needed to

    drive the sound system, and one to four input channels for

    sound pressure level monitoring and measurement. For

    detection of subject response, via a variety of response

    switch options, we used a National Instruments PXI-6220 digital I/O board with a custom response switch

    interface.

    NASA REATMaster Software

    The NASA REATMaster software was developed by

    Nelson Acoustics to provide the ADL with a software

    application that would conduct calibrated real ear

    attenuation at threshold (REAT) measurements using the

    Figure 2: Interior View of NASA GRC Auditory DemonstrationsLaboratory REAT Test chamber, showing diffusing panel, intercom

    speaker system and subject instruction video display.

    Figure 3: The fabric panels in the ADL test chamber are removedfrom the test chamber when it is used for REAT testing. The fabricpanels add the absorption needed to make the chamber convertiblefor use in presenting auditory demonstrations using the secondaryaudio sound system.

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    PROJECT

    National Instruments hardware. National Instruments

    LabView is the programming language used in the

    signal generation, user interface, system calibration and

    test automation software. REATMaster allows flexible

    configuration of system hardware for one to four channels

    of signal generation and provides system calibration

    tools that allow for both level and frequency calibration

    of each channel. It has a manual operating mode that

    supports system function verification, calibration and

    subject training, yet also has an automated threshold-

    seeking feature. All of the audio files produced by signal

    generations are in WAV format, and all of the threshold

    data can be exported to Microsoft Excel spreadsheets

    for post-process analysis.

    On completion of the test chamber and equipment

    installation and software development phases of theproject, the entire system was calibrated and qualified

    per the requirements outlined in ANSI S12.6. Using a

    GRAS 40AQ random incidence microphone and the

    analog inputs on the National Instruments Digital Signal

    Analysis boards, the Nelson Acoustics Trident acoustic

    measurement application was used to conduct the level

    calibration and frequency equalization of the sound

    system.

    The diffuse sound field properties of the chamber

    were evaluated for sound pressure level uniformity and

    directionality at the location of the subjects head. ANSIS12.6 outlines a measurement procedure and criteria

    for these parameters, with the intent being the creation

    of a very uniform and highly omni-directional sound

    field in the region surrounding the subjects head so as

    to minimize the measurement uncertainty associated

    with the hearing protector attenuation as a result of

    uncertainties in the measurement presented to the

    subject.

    The NASA GRC ADL REAT and hearing protector testsystems have been successfully designed, installed, and

    qualified to the ANSI S12.6 test method for measuring

    the real-ear attenuation of hearing protectors. The NASA

    REATMaster software development project resulted in

    a software tool that the ADL and other qualified hearing

    protection laboratories can employ using industry

    standard computer-based digital signal generation

    and data acquisition hardware. The system is currently

    being used at NASA GRC, the National Institute for

    Occupational Safety and Health (NIOSH), the U.S.

    Army Aeromedical Research Laboratory, and severalcommercial hearing protector evaluation laboratories in

    the US and internationally.

    References

    [1] Jeff Schmitt, Beth Cooper and David Nelson. The

    Development of NASA Auditory Demonstrations

    Laboratory for Measurement of Real Ear Attenuation

    of Hearing Protection Devices. NOISE-CON 2010, 19-

    21/04/2010.

    [2] Jeff Schmitt. NASA Auditory Demonstration

    Laboratory Uses LabVIEW and PXI to Test Hearing

    Protection Devices. . National Instruments, n.d. Web.

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    TECHNICAL ARTICLE

    These are interesting times for

    the engineering profession.

    On the surface, there are signs

    of a real engineering Renaissance.Technological magic seems to generate

    ever-more impressive gadgets, our cars

    are achieving near miraculous efficiency

    at affordable prices for the consumer,

    and modern engineering disciplines

    like biomedical engineering are

    offering new hope to countless people

    who would have been functionally

    marginalized in decades past. So why

    are engineering educators so grumpy

    these days?

    Tom LeeChief Education Officer

    WhyCant

    JohnnyDesign?Part 1: Challenges in Modern

    Engineering Education

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    TECHNICAL ARTICLE

    No, there is no scientific study that

    has tracked a grumpiness index

    among our professors, but in recent

    years, there definitely seems to be

    some sense of angst among the

    academic community. Recently, at

    a conference of Innovation Centers

    for Engineering Education (ICEE)

    on Jeju Island in Korea, Korean

    professors gathered as part of

    a regular sequence of meetings

    among a network of 60 Korean

    engineering universities. These

    universities were charged by the

    national government to close the

    gap that exists between Korean

    engineering programs and the

    needs of Korean industry. Today,

    it is widely believed that Korean

    industry can legitimately claim the

    hard-fought title of the next Japan.

    Certainly on the consumer side, the

    products of the Korean electronics

    and automotive industries like

    Samsung and Hyundai, by any

    measure, command brand respect

    approaching, if not equaling,

    legendary Japanese brands such as

    Sony and Toyota.

    The Korean ICEE initiative is

    significant in that it is a focused, well-funded initiative by an engineering

    community that is targeting the

    future driven by engineering

    creativity and innovation rather

    than manufacturing quality and

    aggressive labor costs. The

    sessions at this conference focused

    not so much on graduating more

    engineers to meet increasing

    demands; it tackled the more

    challenging, big-picture, questions

    on what qualities the engineers

    of tomorrow should embody and

    how the academic community can

    deliver the appropriate training.

    ICEE is currently concluding its first

    five-year mandate from the national

    government of Korea indicating

    that funding will be renewed, if not

    increased.

    Grand Challenges of

    Modern Engineering

    The Korean ICEE experience

    is a case study in a regional

    response to the larger issue of

    the readiness of engineering

    Figure 1: Engineering deans gather in Beijing to explore avenues to transform the undergraduate curriculum

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    TECHNICAL ARTICLE

    graduates. The most ambitious

    statement of the significance of

    engineering requirements of the

    future is best articulated by the

    so-called Grand Challenges for

    Engineering. In 2008, the National

    Academy of Engineering in the

    United States presented fourteen

    major technological issues that

    vex humankind and encouraged

    the global engineering community

    to use these as a framework for

    assessing education, research,

    policy, and industrial strategies.

    The grand challenges are: make

    solar energy economical, provide

    energy from fusion, develop carbonsequestration methods, manage

    the nitrogen cycle, provide access

    to clean water, restore and improve

    urban infrastructure, advance

    health informatics, engineer better

    medicines, reverse-engineer the

    brain, prevent nuclear terror, secure

    cyberspace, enhance virtual reality,

    advance personalized learning,

    and engineer the tools of scientific

    discovery.

    For many in the academic

    community, these challenges

    have precisely articulated the

    significance of the work of modern

    engineers but unfortunately, it also

    highlights how difficult it will be to

    prepare our students to tackle these

    immense challenges.

    The current engineering

    curriculum, delivered by the greatmajority of institutions worldwide,

    had its genesis in the mid-twentieth

    century. Largely motivated by then

    urgent requirements of the so-called

    Space Race and its darker flipside,

    the Cold War, a large number of

    engineers had to be trained to

    meet the needs. The response

    from the academic community

    was a curriculum that one might

    consider to be linear start

    with mathematical and scientific

    foundations in the early years,

    progress to application courses

    in the middle years, then cap it

    off with a rigorous thesis or senior

    project. Additionally, the tradition

    of separating students into well-

    defined engineering disciplines

    (electrical, mechanical, chemical,

    civil, etc.) became entrenched.

    Although one cannot deny that this

    approach was effective in that the

    needs of society were largely met,

    it left this generation with lingeringmemories of being completely lost

    for four or more years and eventually

    seeing the light once they began

    experiencing the real world.

    The mismatch for the modern

    context often sites two very

    significant issues. First, as anyone

    that graduated from engineering

    programs during this period, is the

    simple reality of keeping students

    motivated through the very intensive

    and often abstract, theory-heavy

    gauntlet of the first years of the

    undergraduate program. Many of

    us asked, What is the significance

    of this calculus theorem proof in

    the real world? as we struggled

    through the process. In some

    sense, this is the easier problem

    as many successful techniques

    have emerged within the past

    few decades that have attemptedto introduce more applications,

    hands-on labs and case studies to

    help soften the blow.

    The trickier issue is the latter

    the disconnect between

    the traditional structure of the

    engineering disciplines and the

    emerging complexities of modern

    engineering systems. With the pace

    of innovation and the increasing

    sophistication of products and

    infrastructure, many consider

    the techniques represented by

    the traditional curriculum out-of-

    date. Modern engineering teams

    are typically cross-functional

    with contributions from a variety

    of specializations. This included

    technical and non-technical

    specializations, including business

    and human factors. The shortening

    project time-lines also demand

    greater project parallelization and

    cross-functional tasks that simply donot map cleanly to the disciplines.

    Simply put, engineers need to know

    more and do more, all with less time

    and resources.

    Technologically, such pressures

    have triggered highly innovative

    techniques often facilitated by

    modern information and digital

    technology. A clear testament to

    this trend is the academic migration

    of the traditional departments of

    Electrical Engineering (EE) to

    the more contemporary hybrid

    departments of Electrical and

    Computer Engineering (ECE).

    In another important corner of

    the engineering world, many

    departments of Mechanical

    Engineering (ME) are starting to

    express themselves as Mechanical

    and Mechatronic Engineering

    (MME). This sort of trend is oneof the modern responses of the

    academic community; creating new

    departments to accommodate new

    techniques. Is this sufficient?

    The reality is: this will generate a

    relatively small specialized group

    of engineers skilled in even more

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    TECHNICAL ARTICLE

    specialized and narrow fields. It

    also leaves the vast majority of

    our students in the framework of

    the traditional disciplines. A very

    practical example of the deficiency

    in this approach becomes clear in a

    very familiar context: modern cars.

    A Practical Example:

    The Green Car

    Virtually all consumer vehicles

    produced today are electronically

    fuel-injected. More precisely, they

    are typically computer-controlled,

    deploying the same semiconductor

    technology we use in our general

    purpose computers. The electroniccontrol unit (ECU) manages the fuel

    injection and ignition timing and

    other key parameters that influence

    the burning and energy release

    of the engine. For many cars,

    there will also be some computer

    control through the drivetrain (e.g.

    traction control). Within the rapid

    development cycles of todays

    auto industry, it becomes essential

    for the engineering team to workwith the system in its totality. In the

    case of the engine, you will need

    to consider mechanical, chemical,

    and electrical characteristics as

    a minimum. You will also need

    computing knowledge, as the

    engines are computer-controlled.

    From a workflow perspective, new

    techniques such as hardware in

    the loop testing (HIL), offer a rapid,

    highly accurate and cost-effectiveway of testing the performance

    of control systems for engines or

    any other computer-controlled

    subsytem. This is a way of testing

    key components without having

    to physically prototype the entire

    system only to find a critical design

    flaw. This type of sophisticated

    simulation and control systems

    design will demand a system-level

    approach that blends techniques

    and knowledge from many of

    the specialized disciplines.

    Extrapolating further to green

    vehicle design, the same problems

    become greatly amplified for

    hybrid electric vehicles (HEV), fully

    electric (EV), and fuel-cell powered

    vehicles. For these applications,

    chemical engineering knowledge

    becomes increasingly important as

    battery design and alternative fuels

    become the big variables.

    The Renaissance Engineer

    The professors at the Korean

    conference expressed keen

    interest in techniques that

    introduce such multidisciplinary

    and system-level approaches to

    an engineering education. It may

    seem simple enough to begin

    merging select techniques from

    other disciplines into programs,

    but the actual implementation is

    substantially more difficult. Thecurriculum legacy is entangled

    within a large complex system of

    organizations and suborganizations

    with bureaucratic structures and

    decision-making processes that

    ensures academic freedom but

    hinders coordinated transformation.

    Furthermore, the recent focus

    on the research function of the

    engineering university also needs

    to be tempered to allow greatercreativity and energy to revitalize

    the teaching function.

    The Korean context was used to

    highlight the level of commitment

    and vision required to educate the

    modern Renaissance engineer.

    This particular group would be the

    first to admit that they have only

    taken a baby step. But that first

    step is literally a doozy. Korea is

    a nation of fifty million people for

    whom the engineering community

    has literally lifted the population out

    of mass poverty within a generation.

    For this country, the revitalization

    of the engineering community

    is an issue of national priority

    and government, industry, and

    academic institutions seem to be

    in-sync to implement the changes.

    They are not alone, however. At

    another recent conference in Asia,

    approximately three hundred

    deans of engineering and other

    senior engineering educationadministrators met in Beijing at

    the 2011 Global Engineering

    Deans Conference presented by

    the International Federation of

    Engineering Education (IFEES).

    In the audience were significant

    contingents from North American

    institutions who are also anxious

    to learn from their global peers

    and trigger positive action in their

    respective juristictions.

    Throughout North America and

    elsewhere, a generation of children

    have embraced robotics as a hobby

    and even an obsession. These same

    children also lose sleep at night

    wondering whether their world will

    provide sufficient food, clean water,

    and livable environments when

    they take the helm. In many ways,

    the scene is fundamentally different

    from the concerns of Westernnations on whether we are training

    enough engineers to compete

    against emerging economic

    superpowers. The demands on

    the engineering community are

    becoming deeply personal and we

    witness an empowered generation

    ready to take on the challenges

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    TECHNICAL ARTICLE

    but they can only succeed if our

    generation can structure our

    institutions and methods to guide

    them wisely.

    Part two of this article will explorespecific techniques and case

    studies on education innovation

    and key trends that are aimed at

    the revitalization of the engineering

    curriculum.

    About the Author

    Dr. Lee has been an active contributor

    in the global engineering and control

    systems community for over twenty

    years. As Chief Education Officer atQuanser, a leader in realtime control

    and mechatronics solutions for

    education, research, and industry,

    Dr. Lee develops and implements

    the companys strategy for enriching

    and increasing the educational

    effectiveness of technology in the

    modern engineering education

    context. Prior to his appointment at

    Quanser, Dr. Lee was Vice President

    of Applications Engineering

    at Maplesoft, creators of the

    renowned Maple mathematical

    software system. In that capacity,

    he helped the company transform

    the mathematical technology to a

    complete engineering modeling

    and simulation solution. He also

    serves as an Adjunct Professor of

    Systems Design Engineering at

    the University of Waterloo, noted

    for its leadership in engineering,

    computer science, and

    mathematics. Dr. Lee earned his

    Ph.D. in Mechanical Engineering

    at the University of Waterloo, andhis M.A.Sc. and B.A.Sc. in Systems

    Design Engineering at the University

    of Waterloo. He has published

    numerous papers and is a frequent

    invited speaker in the areas of

    engineering education, engineering

    modeling and simulation, and

    engineering computation.

    Join Today

    www.eeweb.com/register

    Electrical Engineering Community

    EEWeb

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    Rad Hard and SEE Hard 12A Synchronous Buck

    Regulator with Multi-Phase Current Sharing

    ISL70002SEHThe ISL70002SEH is a radiation hardened and SEE hardened

    high efficiency monolithic synchronous buck regulator with

    integrated MOSFETs. This single chip power solution operates

    over an input voltage range of 3V to 5.5V and provides a tightly

    regulated output voltage that is externally adjustable from 0.8V

    to ~85% of the input voltage. Output load current capacity is

    12A for TJ +150C. Two ISL70002SEH devices configured to

    current share can provide 19A total output current, assuming

    27% worst-case current share accuracy.

    The ISL70002SEH utilizes peak current-mode control with

    integrated error amp compensation and pin selectable slope

    compensation. Switching frequency is also pin selectable to

    either 1MHz or 500kHz. Two ISL70002SEH devices can besynchronized 180 out-of-phase to reduce input RMS ripple

    current.

    High integration makes the ISL70002SEH an ideal choice to

    power small form factor applications. Two devices can be

    synchronized to provide a complete power solution for large

    scale digital ICs, like field programmable gate arrays (FPGAs),

    that require separate core and I/O voltages.

    Applications FPGA, CPLD, DSP, CPU Core and I/O Voltages

    Low-Voltage, High-Density Distributed Power Systems

    Features DLA SMD#5962-12202

    12A Output Current for a Single Device (at TJ = +150C)

    19A Output Current for Two Paralleled Devices

    1MHz or 500kHz Switching Frequency

    3V to 5.5V Supply Voltage Range

    1% Ref. Voltage (Line, Load, Temp. & Rad.)

    Pre-Biased Load Compatible

    Redundancy/Junction Isolation: Exceptional SET Performance

    Excellent Transient Response

    High Efficiency > 90%

    Two ISL70002SEH Synchronization, Inverted-Phase

    Comparator Input for Enable and Power-Good

    Adjustable Analog Soft-Start

    Input Undervoltage, Output Undervoltage and Adjustable

    Output Overcurrent Protection

    QML Qualified per MIL-PRF-38535

    Full Mil-Temp Range Operation (-55C to +125C)

    Radiation Environment

    - High Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 krad(Si)

    - ELDRS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 krad(Si)*

    *Level guaranteed by characterization; EH version is

    production tested to 50 krad(Si).

    SEE Hardness

    - SEL and SEB LETTH . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2

    - SEFI LETTH. . . . . . . . . . . . . . . . . . . . . . . . . . . . 43MeV/mg/cm2

    - SET LETTH . . . . . . . . . . . . . . . . . . . . . . . . . . 86.4MeV/mg/cm2

    70

    75

    80

    85

    90

    EFFICIENCY(%)

    LOAD CURRENT (A)

    0 1 2 3 4 5 6 7 8 9

    FIGURE 1. EFFICIENCY 5V INPUT TO 2.5V OUTPUT, TA = +25C

    10 11 12

    CH4 SYNC

    CH3 VOUT x 10

    CH2 SLAVE LX + 15V

    CH1 MASTER LX + 20V

    -6 -4 -2 0 2 4 6 8 10 12 14

    TIME (s)

    AMPLITUDE

    (V)

    25

    20

    15

    10

    5

    0

    FIGURE 2. 2-PHASE SET PERFORMANCE at 86.4MeV/mg/cm2

    April 5, 2012FN8264.1

    Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2012All Rights Reserved. All other trademarks mentioned are the property of their respective owners.

    Get the Datasheet and Order Samples

    http://www.intersil.com

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    TECHNICAL ARTICLE

    TDR:Reading the Tea Leaves

    MichaelSteinberger

    LeadArchitect,SerialChannelProducts

    Time domain reflectometry (TDR) is an essential

    microwave measurement technique and also anessential technique for analyzing measured S

    parameters. However, extracting as much information as

    possible from a TDR trace can resemble the work of a

    fortune teller. There is a lot of information that escapes

    the casual observer but is readily apparent if one knows

    what to look for. This article reviews the basic techniques

    for interpreting TDRs and then adds a couple of simple

    techniques that are not as well known.

    What Happens Where

    The goal of time domain reflectometry (TDR) is tocorrelate the electrical behavior of a transmission line

    circuit with its physical features. Once one understands

    which physical features have the most significant effect

    on electrical behavior, its a lot easier to improve the

    design.

    TDR is almost always associated with measured data-

    either the TDR data is measured directly or else its

    computed from measured S parameters. Either way, the

    goal is to determine the magnitude and location of the

    transmission line discontinuities that are in the actualcircuit, independent of what any model might predict.

    TDR data can also be generated for models, and thats

    useful for comparison to measured data.

    Figure 1 and Figure 2 are examples of TDR data

    computed from measured S parameters. Each figure

    shows a time domain waveform which approximates the

    reflection coefficient as a function of time (and therefore

    distance). The two figures show TDR data looking from

    opposite ends of the same interconnect network. As will

    be explained in the following sections, the individual

    elements such as vias, traces, and connectors areclearly visible in the TDR trace. Some of these features

    are labeled in the figures.

    How TDR Data is Measured

    Time domain reflectometry measures the voltage step

    response at the input to the device under test. The source

    impedance is typically a standard reference impedance

    such as 50 ohms single ended or 100 ohms differential.

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    TECHNICAL ARTICLE

    Nonetheless, these approximations are good enough to

    obtain some useful information.

    If one assumes that the three simplifying approximations

    are valid, then for a transmission path with varying

    impedance , the reflection coefficient for a short length

    --- of that path is:

    Taking the limit as and applying the

    approximation of constant impedance,

    Applying the second and third approximations (low loss

    and constant velocity) to the calculation of the impulse

    response at the driving end, and assuming that the

    propagation velocity is y,

    One can then get the step response (that which is actually

    measured) by integrating with respect to time. The result

    is:

    In other words, the amplitude of the step response at

    a particular time is approximately proportional to the

    impedance at some corresponding distance along the

    transmission path. This is the desired result.

    As each of the approximations breaks down, however,

    the step response exhibits additional artifacts.

    1. Impedance Variations

    a. As the impedance variations become more and more

    extreme, the impedance scale in the TDR waveform

    becomes distorted. For example, an open circuit

    (essentially infinite impedance) does not result in an

    infinite step response amplitude; it results in a doubling

    of the step response amplitude.

    Therefore the amplitude scale of a TDR waveform is

    really incident wave plus a reflection coefficient

    between 0 and 2 rather than a linear impedance scale.

    b. If there are multiple discontinuities in the transmission

    path, then the step response edge reflected by a

    disontinuity which is further from the measurement point

    will be reflected by the nearer discontinuities and then

    reflected again by the further discontinuity, resulting in

    multiple reflections arriving at the measurement point.

    2. Transmission Loss

    As the step response edge propagates along the

    transmission path, it encounters loss, especially at

    higher frequencies. This loss smooths out the edge that

    is incident on discontinuities which are further from the

    measurement point. The step response edge that is

    reflected also gets smoothed out on its way back to the

    measurement point. Therefore features which are further

    from the measurement point become less distinct.

    For example, the features on the right hand side of Figure

    1 and Figure 2 are much less distinct than those on the

    left hand side, even though the features on the left hand

    side of one figure are exactly those of the right hand sidein the other figure.

    3. Propagation Velocity Variations

    If the propagation velocity changes, for example because

    the transmission medium changes from PC board to

    cable, then the translation from time to distance will be

    distorted accordingly.

    Interpreting the TDR Trace

    Figure 4 shows a view of the example TDR in Figure 1 that

    has been plotted on an impedance scale and expandedto show some detail at the beginning of the TDR trace.

    Measurement/calculation setup

    The first two nanoseconds of the TDR trace show some

    details about how the TDR was calculated, or how the

    equivalent trace would be measured in the lab.

    Since the original S parameter data was supplied to

    Figure 3: Time domain reflectometry measurement of interconnect

    network

    InterconnectNetwork

    Z0

    Z0

    Z0

    StepStimulus Measure Step

    Response

    +

    +

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    TECHNICAL ARTICLE

    impedance. That is,

    For example, the via in Figure 4 increases the conductance

    of the transmission line from 1/52.5 Semens to 1/49.6Semens, for an increase of 0.00114 Semens. One half of

    the round trip delay of 72pS in the TDR trace is 36pS, so

    the excess capacitance of the via is approximately 41fF.

    Steady State Values

    It is often observed that the steady state value of a TDR

    trace is higher than the initial stimulus amplitude. This

    is apparent in Figure 1 and Figure 2, and is illustratedagain using an impedance scale in Figure 5.

    This feature of the TDR trace is not a numerical artiface;

    its a fundamental behavior of the interconnect network

    and a useful piece of information. Consider that when

    the TDR trace (as a step response) settles to a long term

    value, the equivalent circuit is

    Figure 5: Example TDR with series resistance shown

    Figure 6: Steady state measurement of interconnect network

    Therefore from Figure 5, the series resistance of that

    particular interconnect network is approximately 3.

    For another view of the measurement of interconnect

    network behavior at low frequencies, see [2].

    References

    [1] Matthei, Young and Jones, Microwave Filters,

    Impedance Matching Networks, and Coupling

    Structures, section 5.02, equation 5.02-5, page 164,

    McGraw-Hill, copyright 1964.

    [2]h t tp : / / rea lt imewi th .com/pages/ r twvprof i le .

    cgi?rtwvcatid=13&rtwvid=1691

    About the Author

    Michael Steinberger, Ph.D., is responsible for leading

    SiSofts ongoing tool development effort for the design

    and analysis of serial links in the 5-30 Gbps range. Dr.

    Steinberger has over 30 years experience in the design

    and analysis of very high speed electronic circuits.

    Dr. Steinberger began his career at Hughes Aircraft

    designing microwave circuits. He then moved to Bell

    Labs, where he designed microwave systems that

    helped AT&T move from analog to digital long-distance

    transmission. He was instrumental in the development of

    high speed digital backplanes used throughout Lucents

    transmission product line. Prior to joining SiSoft, Dr.Steinberger led a group of over 20 design engineers at

    Cray Inc. responsible for SerDes design, high speed

    channel analysis, PCB design and custom RAM design.

    That is, at steady state, the only relevant circuit elements

    are the resistances in the circuit. For most interconnect

    networks (those with negligible DC leakage), the

    resistances are the source resistance, the load resistance,

    and the series resistance of the interconnect network.

    Time (ns)

    0.0

    70.0

    65.0

    60.0

    55.0

    50.0

    45.0

    40.0

    2.0

    Ohms

    4.0 6.0 8.0 10.0 12.0 14.0

    y1: (50.0)y2: (53.010)dy: 3.012

    Interconnect

    Network

    Z0

    Z0

    StepStimulus Measure Step

    Response

    R

    +

    +

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    TECHNICAL ARTICLE

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    TECHNICAL ARTICLE

    Introduction

    In digital circuit design, a clock signal is one that

    oscillates between a high and a low state and directs a

    circuits performance. Logic may toggle on the rising

    edge, falling edge or both edges in an application.

    With thousands of instances running off of a given clock

    domain, it is necessary to insert a tree of buffering to

    adequately drive the logic. Clock trees often have delay,

    skew, minimum power, and signal integrity requirements

    that the layout engineer must meet.

    Arguably clock descriptions and diagrams are the most

    critical information that must be communicated when

    a circuit is transferred from a front-end designer to the

    back-end layout engineer. Hours, days, and even weeks

    of design work has been lost over the years due to

    miscommunications, misunderstandings, and needs for

    complete re-synthesis involving clock trees.

    Before layout, ideal clocks are used for synthesis and

    timing constraints. Clock definition constraints may

    appear on top-level pads or pins of a block; on the

    output of a macro such as a delay-locked loop (DLL) or

    phase-locked loop (PLL); or as a generated clock on a

    dividing register. These clock definitions may or may not

    be where the layout engineer needs to define clock roots

    to attain optimal latencies, balancing and skew across

    various modes of operation. A high level of information

    exchange between the front end and layout along with anunderstanding of what layout will do with that information

    will greatly improve the CTS process of the physical

    design flow.

    Design Tips for Successful CTS

    Some of the following tips have been circling around the

    industry for quite a while, but based on experience over

    the last few years, they are worth repeating.

    Billie JohnsonPhysical Design Engineer

    YourClocks,My Layout

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    TECHNICAL ARTICLE

    Establish a naming convention for clock muxes or

    instances that you know will be a start point for a clock

    tree. This provides a nice sanity check for layout because

    it is easy to search and count in a layout database based

    on strings.

    Use medium- to high-strength drivers for clock root

    instances. This allows the clock tree to get off to the right

    start. Do not use the highest drive strength available in

    your library, however, because it is useful to be able to

    upsize later in the design if issues are uncovered with

    signal integrity (SI) analysis or on-chip variation (OCV)

    analysis.

    Make certain that clock divide registers and their sync

    registers are purposely driven by muxing logic if they are

    to run in a separate test mode. This allows the capability

    to add delay on the input side of the mux for a test mode

    without pushing out all of the other registers clocked by

    the generated clock in functional mode.

    Figure 1 shows two register clock divide registers.

    Without additional muxing logic, a functional clock

    will most likely not work for a test mode. The divide-by

    registers wont be balanced with any of the registers

    downstream. The fewer registers in the green domain

    would likely lead to a much faster clock than in that of the

    purple domain.

    Figure 2 illustrates a muxing scheme that would allow for

    each clump of downstream registers and the divide-bys

    to have a minimized clock through one input of a mux

    AND a balanced one through the other.

    Insert a reset-specific driver if necessary. Sometimes a

    couple of registers will be used to synchronize a reset. It

    may not be necessary for those registers to be balanced

    to all of the other ones also driven by that clock. In Figure

    3, without a focused strategy, software will try to balance

    the blue registers after the gating logic with each of the

    pink registers contained in the reset synchronizing logic.

    This scenario can be easily handled in the layout if they

    are split from the rest of the registers with their own

    exclusive driver.

    Figure 4 demonstrates how a place-holder or excluding

    buffer can be inserted and easily identified in the hand-

    off communication so the layout engineer knows where

    balancing attempts can diverge.

    Figure 1

    Figure 4

    Figure 3

    Figure 2

    50

    810SQ

    11

    10SQ

    11

    10SQ

    11

    10S

    Q

    11

    Clock

    Root

    Rst_out

    ClockRoot #2

    excludedfrom

    CTS of#1

    Rst_out

    k#1

    500

    8

    10SQ

    11

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    TECHNICAL ARTICLE

    clock root insertion points, latency, skew and transition

    targets, and specifics for gating logic, through-registers,

    and cross-domain relationships can be ported directly

    into the CTS tool. The layout engineer will then use their

    discretion concerning buffer types to use, optimization

    iterations and requirements for the router like spacing,

    shielding, and metal layers.

    Before clock trees are inserted, a trace can be performed

    to ensure endpoints that are intended to be balanced

    will be. Gating logic, excluded legs off of a clock root,

    IO endpoints, and reconvergent instances can also be

    revealed and assessed.

    Clock trees can consist of buffering cells only or series

    of inverters. Most technologies today have special clock

    buffering and clock inverting cells that have a balanced

    rise and fall time to help ensure an uncompromised duty

    cycle. Other requirements like levels in a tree or max

    fanout of each clock cell can also be incorporated.

    Conclusion

    In addition to everything discussed so far, the layout

    engineer will likely experiment with clock-gate-aware

    placements, clock routing guides and floorplan tweaks.

    Iterations of CTS will often be run with minor modifications

    for the skew, latency, and transition targets. Trial and

    error helps achieve the perfect blend. If the front end

    understands how CTS works, and communicates the

    clock structure at the onset, then the layout engineer can

    embark upon the task more proficiently. Time for CTS

    in the schedule can be spent tuning and improving your

    clocks rather than simply trying to insert them into my

    layout.

    About the Author

    Billie Johnson is a Physical Design Engineer at ON

    Semiconductor. Her work experience spans test, design,

    technical marketing and layout, and she holds a B.S. in

    Engineering and an MBA from Idaho State University inPocatello, Idaho. She has participated in numerous K-12

    math and engineering outreach programs throughout her

    career including MATHCOUNTS ,FIRSTLEGO

    League (FLL) , Wind for Schools and Introduce a Girl

    to Engineering Day.

    Provide a better-than-you-think-you-need clock diagram

    and extensive written description. When front end

    design is ready to deliver the netlist to layout, they

    are already widely familiar with the design and clock

    requirementsor at least they should be. Sometimes

    initial CTS efforts will uncover that the ideal values

    used in pre-layout timing constraints are not physically

    achievable. Problems leading to this can be revealed

    sooner rather than later if an accurate clock diagram is

    provided with the netlist handoff along with information

    about the clocking scheme.

    An overall diagram or diagrams representing all of the

    designs clocks including gating logic is ideal. This could

    be software-generated either with a drawing program or

    a schematic capture tool. It can even be drawn by hand

    and saved in a PDF or faxed to the layout engineer. Thispicture could be worth a thousand words spread over

    dozens of phone calls and e-mails trying to get the clock

    formats straight.

    Since diagrams can get complicated and messy,

    accompanying written descriptions are needed. This

    includes explanations of generated clocks, details of

    any clock gating or muxing patterns, and requirements

    for skew balancing and latencies. These particulars are

    necessary for each mode of operation because each

    mode must be addressed during clock tree insertion.

    Registers may wind up balanced beautifully for functionalmode but miserably unbalanced for test modes if we are

    not careful.

    If the clocks utilize a DLL or another macro or if it

    passes through gating logic, these details are necessary.

    Macros purposes must be explained. It is possible to

    synthesize and balance through those types of macros

    if that is what is desired. As for gating logic, if a scenario

    exists in which one pin is accessed in one mode, but

    another pin of the same cell is accessed in another mode

    the trace tool will identify this as a Reconvergent Clock.

    Although layout tools can resolve these cases, it may be

    better to force the tool to look through one pin instead of

    the other during the clock insertion.

    CTS Within Industry Tools

    Industry software facilitates clock tree synthesis with

    powerful tools driven by designers specifications and

    guidelines. Information from the front end pertaining to

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