Ee443 phase locked loop - paper - schwappach and brandy

CTU: EE443-Communication Systems I: Phase-Locked Loop 1

Colorado Technical University EE 443- Communication Systems I

Phase-Locked Loop Research Paper September 2010

Loren Schwappach & Crystal Brandy

ABSTRACT: This lab report was completed as a course requirement to obtain full course credit in EE443, Communications 1 at Colorado Technical University. This report examines the components of phase-locked loop system and its practical application in FM signal demodulation.

If you have any questions or concerns in regards to this laboratory assignment, this laboratory report, the process used in designing the indicated circuitry, or the final conclusions and recommendations derived, please send an email to [email protected].

I. INTRODUCTION

This paper provides a simple outline of the phase-locked loop process and its use and application in communication systems. Understanding of the complicated phase-locked loop process can be simplified through the simulation and modeling of a phase-locked loop system in a simulation program such as MATLAB. The process of demodulating a frequency modulated (FM) signal is a perfect model for simulating this concept and thus was chosen as the focus of this research paper. Finally, this research paper provides a short summary of the properties inherent in a PLL system as well as applications of the PLL.

II. PHASE-LOCKED LOOP

A Phase-Locked Loop (PLL) is a negative feedback control system. The operation of a PLL system is closely related to frequency demodulation. In a PLL frequency demodulation scheme the voltage controlled oscillator’s control frequency is automatically adjusted to match a provided input signal in frequency and phase. The PLL is also commonly used for carrier synchronization, clocking, buffering, jitter reduction, and advanced signal processing. The phase-locked loop system consists of three major components, a Voltage-controlled oscillator (VCO) which performs frequency modulation on its internally generated carrier signal, a phase detector which multiplies an incoming FM wave by the output of the VCO, and finally a loop filter which removes the high-frequency components contained in the multiplier’s output signal. A loop amplifier further aids in ensuring the demodulated output is at a desired gain.

A. Modeling a PLL

A simple block diagram outlining the components of a simple PLL system as used in FM demodulation is shown by Figure 1 below. The PLL frequency multiplier (Phase Detector) shown in the block diagram in Figure 1 takes in a provided message input and multiplies it with an error voltage produced by a VCO. The Phase Detector outputs a voltage proportional to the phase difference between two inputs in the form of equation (5) below. This output is then fed into a loop filter which is a high order low pass filter. The loop filter removes the unwanted high frequency components reducing the output into the form of equation (6). This loop filter output then feeds into a loop amplifier which aids in restoring the signal into a desired amplitude. If the carrier produced by the voltage controlled oscillator is the same in frequency and phase as the modulated signal then the output of the loop amplifier is the final demodulated signal output multiplied by some factor. However, if the VCO carrier (control frequency) is not the same in frequency or phase as the modulated signal an corrective error signal will attempt to drive the VCO carrier into alignment by driving the VCO carrier either up or down in phase. This may seem a complicated process but can be simplified if viewing the phase correction in a linear manner. If equation (7) below is viewed as a x-y graph with the y-axis representing the VCO frequency and the x-axis representing an input error signal. If the input error signal is positive it will increase the slope of the VCO frequency deviation. If the input error signal is negative in value it will decrease the slope of the VCO frequency deviation. This change in slope will push the frequency into alignment until the error signal is null representing a phase-locked loop.

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Figure 1: Block Diagram of a PLL System used in FM demodulation.

The error signal produced by the phase detector is

proportional to a phase error between the VCO and a

modulated signal. The error signal represents whether the

VCO correction will increase or decrease the VCO control

frequency as illustrated in equation (7).

Figure 2: Phase Detector represented as a multiplier.

Simple equations used for representing the inputs of the phase detector in a FM demodulating PLL system:

s t cos fct t

The output of the phase detector contains a high frequency component and a low frequency component, this is due to simple triginometry.

fct t t

t t

t t

The VCO produces an output whose frequency

deviation depends directly upon the input error voltage just

like the equation for the production of an FM signal. So the

VCO can be modeled exactly the same. Figure 3 shows an

example of how a VCO is commonly used. VCOs can be

implemented in numerous ways. Some of the common

methods of VCO implementation include: Crystal Oscillators

and RLC oscillators, although they are just the beginning. The

time-domain equation for most common VCOs is:

Figure 3: Commonly used VCO configuration

Comprehending the operations of a PLL system can be a very complex, high level mathematical nightmare when viewed as a non-linear system (out of phase). However, when viewed as a linear system (In-Phase lock) the mathematics become easy and thus the understanding of how the PLL ensures FM demodulation and how phase lock


occurs. Thus said, Figure 4 below shows the non-linear model of a PLL assuming that the PLL is not in phase lock.

Figure 4: Non-Linear Mathematical Model of PLL Figure 5 below explains the linearized model showing the production of the demodulated signal once the VCO and modulated signal are in syncronization lock.

Figure 5: Linearized Mathematical Model of Locked PLL

B. Properties of PLL

Some of the commonly referred to properties of a PLL are: Step Response, or the PLL ability to phase / frequency step onto its input (the quicker the better). Setting Time; the amount of time needed to lock-on to a signal after receiving an input (the smaller the better). Phase Jitter; a short-term frequency instability that causes small, rapid movements in phase, often referred to as phase noise. The last item is one of the major strengths of PLL systems in imaging and tracking communication systems.

C. Simulating & Testing

Now that we have discussed some of the properties of PLL systems and how a PLL system can be used in PM demodulation, we can take all of this information about a PLL system and use it to test a simple PLL in a FM demodulation scheme created for this paper using MATLAB Simulink software. Suppose we are given a composite sinusoidal wave as illustrated by equations (11) and (12).

Furthermore, let us assume our VCO quiescent (unmoved) frequency is at 10e3 Hertz. The transmission bandwidth (BT) is not allowed to exceed 3e3 Hertz.

D. Design Considerations

Now to fully simulate the demodulation process, we need to evaluate some setup options for our VCO and Loop filter using our design constraints above and the equations below.

Using these equations the following values were obtained for our initial design in Simulink.

Carrier frequency (fc) = 10e3 (Hz);

BT < 3e3 (Hz) so kf < 132 (Hz/V) {using max values}; Thus..

Let kf = 1e2 (Hz/V) then Beta = approx 5.5 (wideband)

Let the LP filter cutoff at approx 1e4 (Hz) (carrier) & use a 10

th order Butterworth LP filter.

E. Testing Phase

Now that all of the main design considerations are taken into account we can build the system in Simulink as demonstrated by Figure 6a. If the design works we will then test the system using the following criteria:

Test 1: Initial design

Test 2: kf << 1e2

Test 3: kf >> 1e2

Test 4: LP Filter cutoff is < 1e4 (Hz)

Test 5: LP Filter cutoff is > 1e4 (Hz)

Test 6: 1st

Order Butterworth LP Filter


1) Initial Design

The initial design used in constructing the FM modulator and demodulator is below. The FM modulator portion was constructed during a previous lab in EE443 communications 1 at Colorado Technical University and verified as a valid FM modulation scheme.

Figure 6a: Initial Design of FM Modulation and FM Demodulation using a PLL system.

Figure 6b: Message signal prior to FM modulation.

Figure 6c: Message signal successfully recovered using PLL system.

Figure 6d: Frequency components (frequency spectrum) of the PLL demodulated signal. Notice the two major components (above 0dBm) are the original message frequency components.

2) Initial Design Observations

It worked! The FM signal was successfully demodulated using the negative phase-locked loop feedback to lock the VCO to the modulated signal.

The kf value of 1e2 (Hz/V) provided enough sensitivity to accurately reproduce the message, ensuring a quick phase lock as observed by equation (12) while keeping the BT < 3e3 (Hz).

The 10th

order Butterworth low pass Loop Filter produced a clean output signal by removing the high frequency component garbage produced by the phase detector (multiplier).

3) Test 2, kf << 1e2 (smaller bandwidth)

By decreasing the value of kf (VCO frequency sensitivity or input sensitivity) we should decrease the ability of the PLL system to handle larger changes in deviation between the VCO and the modulated signal. This should appear as an averaging of our message signal. The results are shown by Figure 7a.


Figure 7a: Time domain result of our demodulated wave recovered when the PLL VCO sensitivity kf value is too low. Notice the output signal appears almost averaged, and notice the time it takes for our VCO to look onto the incoming signal.

Figure 7b: Frequency spectrum results of setting the PLL VCO kf value too low. Notice the drastic attenuation of our second message component (180 Hertz).

4) Test 2, kf << 1e2 (smaller bandwidth) Observations

It failed! The FM signal was not successfully demodulated due to the PLL VCO inability to track the dynamically changing input.

The kf value of 1e1 (Hz/V) (B < .1), was not sensitive enough to accurately reproduce the message signal in the time domain. Furthermore, the second message component (180 Hz) displayed major attenuation compared to the first message component (36 Hz).

The Loop Filter produced a clean output signal and removed the unwanted high frequency components produced by the phase detector (multiplier).

5) Test 3, kf >> 1e2 (larger bandwidth)

By increasing the value of kf we increase the capability of our PLL VCO in tracking the phase deviations of the modulated signal. This should increase our chances of message recovery. However, by increasing kf we also approach exceeding our message bandwidth and could end up pushing the PLL outside of the frequency spectrum window (past 0Hz) as shown by equation (14). The results of this test are shown by figures 8a and 8b.

Figure 8a: By pushing kf too high our recovered signal looks like noise in the time domain.

Figure 8b: Results of a high kf in the frequency domain.

6) Test 3, kf >> 1e2 (larger bandwidth) observations

It failed! The FM signal was not successfully demodulated.

The kf value of 1e3 (Hz/V) (B > 50), was sensitive enough to accurately reproduce the message signal in the time domain. However, the increased value of kf pushed the transmission bandwidth way above the carrier frequency and exceeding our bandwidth requirement, ensuring a complete loss of information required for phase locking onto the modulated signal.

Also, The Loop Filter would need to be adjusted (If the BT didn’t exceed the carrier, which it did) to


account for the increased frequency components now present by the multiplier (Phase detector).

7) Test 4, LP Filter cutoff is < 1e4 (Hz)

In this phase the effects of a lower LP filter corner frequency are verified on our PLL system. By lowering the Loop Filters corner frequency we could cutoff several of the components representing our message signal within our FM modulated wave. Removing these components could have drastic effects on signal recovery. The results of this filter change are reflected by Figures 9a and 9b below.

Figure 9a: Output Signal of a LP Filter with reduced corner frequency (1e3 Hertz).

Figure 9b: Output of a LP Filter with reduced corner frequency in the frequency domain. Notice our message signal components are gone.

8) Test 4, LP Filter cutoff is < 1e4 (Hz) observations

It failed! The FM signal was not successfully demodulated.

The kf value of 1e2 (Hz/V) provided enough sensitivity to accurately reproduce the message while keeping the BT < 3e3 (Hz).

The Loop Filter failed! The LP cutoff frequency of 1 kHz was to low and removed several of the pieces (starting at the carrier) needed to accurately represent the message.

9) Test 5, LP Filter cutoff is > 1e4 (Hz)

By increasing our LP filter corner frequency we increase the amount of unwanted frequency components entered into the system as a result of the Phase Detector (equation 5). The results of this are illustrated by Figures 10a and 10b.

Figure 10a: Output signal of LP Filter cutoff at 1.5e4 (HZ).

Figure 10b: Frequency Domain output of our reduced corner LP Filter. Notice the increased amount of undesirable signals.

10) Test 5, LP Filter cutoff is > 1e4 (Hz) observations

It failed! The FM signal was not successfully (cleanly) demodulated.


The Loop Filter failed! The LP cutoff frequency of 1.5 kHz was too high and allowed several of the unwanted high frequency components into the system.


11) Test 5, Using a 1st Order Butterworth LP Filter

By decreasing the order of the Butterworth low pass filter we decrease the attenuation of unwanted high frequencies present as a result of the Phase Detector. This should show the same results as test 5, however this may be even more drastic due to the poorer attenuation. The results are shown by Figures 12a and 12b.

Figure 11a: Time Domain output signal of 1st order Butterworth.

Figure 1b: Frequency Domain output of a first order Butterworth.

12) Test 5, Using a 1st Order Butterworth LP Filter

observations

It failed! The FM signal was not successfully (cleanly) demodulated.


The Loop Filter failed! The first order Butterworth filter allowed several of the unwanted high frequency components into the system.

F. Other Applications of PLL

Phase-locked loop systems are essential to thousands of

analog and digital communication devices. Among the

thousands are some of the following broad and commonly

used applications which include:

Frequency Synthesizers

Jitter reducers

Clock Generation-

Zero Delay Buffers

Spread Spectrum Frequency Synthesizers

Demodulators (QPSK, QAM, FM, FSK, SSB)


III. CONCLUSION

A Phase-Locked Loop (PLL) system is a negative feedback control system whose operation is closely related to frequency modulation (FM) and is commonly used for carrier synchronization and indirect frequency demodulation. A PLL system consists of three major components which are a Voltage-controlled oscillator (VCO), phase detector (PD), and loop filter. The phase-locked loop will automatically adjust its frequency and phase based on an input error voltage and attempt to lock onto a reference signal based upon the error. This makes the PLL a commonly used system for carrier synchronization, indirect frequency demodulation, clocking, buffering, and jitter removal in digital and analog systems.

IV. REFERENCES

Haykin, S., “Analog and Digital Communications 2nd

Edition” John Wiley & Sons, Haboken, NJ, 007.

Truxal, J. G., Automatic Feedback Control System Synthesis, McGraw-Hill, New York, 1955.

Gardner, F. M., Phase Lock Techniques, Wiley, New York, Second Edition, 1967.


Figure 7a: Initial Design of FM Modulation and FM Demodulation using a PLL system.

Ee443 phase locked loop - paper - schwappach and brandy

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