Ee443 phase locked loop - presentation - schwappach and brandy

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Phase-locked loop (PLL) By: Loren Schwappach & Crystal Brandy Prepared for: Dr. Jing Guo CTU EE443 Communications 1 September 2010

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Transcript of Ee443 phase locked loop - presentation - schwappach and brandy

Page 1: Ee443   phase locked loop - presentation - schwappach and brandy

Phase-locked loop (PLL)By:

Loren Schwappach & Crystal Brandy

Prepared for:

Dr. Jing Guo

CTU – EE443 – Communications 1

September 2010

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Overview

• What is a PLL?

• Modeling a PLL

• Properties of PLLs

• Simulating and Testing a PLL

• Other Applications of PLLs

• Questions

• References

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What is a phase-locked loop?

• A negative feedback control system whose operation is closely linked to frequency modulation (FM).

• Automatically adjusts the frequency, and phase of a control signal to match a reference signal.

• Commonly used for carrier synchronization and indirect frequency demodulation.

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What is a phase-locked loop? Continued...

• A change in the input signal shows up as a change in phase between the input signal and the VCO frequency.

• Consists of 3 major components– Voltage-controlled oscillator (VCO)

• Performs frequency modulation on its own carrier signal

– Phase Detector• Multiplies an incoming FM wave by the output of the VCO

– Loop filter• Removes the high-frequency components contained in the

multiplier’s output.

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Phase Detector:

s(t)

eo(t)

ed(t)

s t = 𝐴𝑐cos 2πfct+ φ1(t)

𝜑1 𝑡 = 2𝜋𝑘𝑓 𝑚 𝜏 𝑡

0

𝑒𝑜 𝑡 = 𝐴𝑣𝑠𝑖𝑛 2𝜋𝑓𝑐𝑡 + 𝜑2(𝑡)

𝜑2 𝑡 = 2𝜋𝑘𝑑 𝑣 𝜏 𝑡

0

𝑒𝑑 𝑡 =1

2 𝑘𝑑𝐴𝑐𝐴𝑣 sin 4πfct+φ1(t)+φ2(t) +

1

2 𝑘𝑑𝐴𝑐𝐴𝑣 sin φ1(t)-φ2(t)

low-frequency componenthigh-frequency component

𝑒𝑓 𝑡 ≈1

2 𝑘𝑑𝐴𝑐𝐴𝑣 sin φ1(t)-φ2(t)

Phase Detector Loop Filter Loop Amplifier

Voltage Controlled Oscillator (VCO)

v(t)

eo(t)

FM waves(t)

Voltage Controlled Oscillator

Phase-Locked Loop (PLL) for FM Demodulation:

ed(t) ef(t)

ev(t)

Modeling a PLL:

• The error signal produced is proportional to phase error.

• The error signal also represents whether the correction should increase or decrease the VCO frequency.

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Why use a VCO?:A VCO produces an output whose frequency deviation depends upon the input voltage.

What does that sound like?

That’s right.. An FM signal. So you can model a VCO the same.

𝑉𝐶𝑂𝑜𝑢𝑡𝑝𝑢𝑡 = 𝐴𝑣 sin 𝑤𝑐𝑡 + 𝜃𝑡

𝑑𝜃(𝑡)

𝑑𝑡= 2𝜋𝐾𝑣𝑒𝑣(𝑡)

𝜃(𝑡) = 2𝜋𝐾𝑣 𝑒𝑣(𝑡)𝑡

0

𝑑𝜏

VCO’s can be implemented in numerous ways. Crystal Oscillators, RLC oscillators, etc are just the beginning.

Modeling a PLL: Continued...

Example of a commonly used VCO

VCO time-domain equation:ftuning(t) = Kv * vin(t)

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𝜑1 𝑡

𝜑2 𝑡

1

2𝑘𝑑𝐴𝑐𝐴𝑣 ∑ Loop Filter, h(t)

Linearized Mathematical Model of PLL (Locked PLL):

Loop Amplifier2𝜋𝐾𝑣 (𝛼)𝑡

0

𝑑𝜏

ed(t) ef(t)

ev(t)

𝜑𝑒 𝑡 = (𝜑1 𝑡 − 𝜑2 𝑡 ) = 0

𝑑𝜑1(𝑡)

𝑑𝑡=

𝑑𝜑2(𝑡)

𝑑𝑡

2𝜋𝐾𝑣𝑒𝑣 𝑡 = 2𝜋𝐾𝑓𝑚 𝑡

Demodulated signal

𝜑1 𝑡

𝜑2 𝑡

1

2𝑘𝑑𝐴𝑐𝐴𝑣 Sin(α)∑ Loop Filter

Non-Linear Mathematical Model of PLL:

Loop Amplifier2𝜋𝐾𝑣 (𝛼)𝑡

0

𝑑𝜏

ed(t) ef(t)

ev(t)

Assume PLL is locked, then: Now we can use a linearized model.

𝜑𝑒 𝑡 = (𝜑1 𝑡 − 𝜑2 𝑡 ) = 0

Modeling a PLL: Continued...

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Properties of phase-locked loops:

• Step response: ability to phase/frequency step on its input.

• Setting Time: amount of time needed to lock-on after receiving an input.

• Phase Jitter: Short-term frequency instability causing small, rapid movements in phase. Often referred to as phase noise.

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Things to test: 1. Initial Design2. What happens when kf << 1e2 (smaller bandwidth)3. What happens when kf >> 1e2 (larger bandwidth)4. What happens when LP Filter cutoff is < 1e4 (Hz)5. What happens when LP Filter cutoff is > 1e4 (Hz)6. What happens when we use a 1st order Butterworth.

Testing a simple PLL Design (Using Simulink):Suppose we are given a composite sinusoidal wave:

And we would like to frequency modulate and demodulate this wave with a 10kHz carrier, using a Phase-locked loop feed back system for demodulation. The transmission bandwidth (BT) is not allowed to exceed 3 kHz.

s t = 5 cos 36 × 2πt + 2sin(180 × 2πt)

∆𝑓 = 𝑘𝑓 × 𝐴𝑚

𝛽 =∆𝑓

𝑓𝑚

𝐵𝑇 = 2 × ∆𝑓 + 2 × 𝑓𝑚

𝐵𝑇 = 2 × 𝑘𝑓 × 𝐴𝑚 + 2 × 𝑓𝑚

𝑘𝑓 = 𝛽 × 𝑓𝑚

𝐴𝑚

Design Considerations:Carrier frequency (fc) = 10e3 (Hz),BT < 3e3 (Hz) so kf < 132 (Hz/V) {using max values},Let kf = 1e2 (Hz/V) then Beta = approx 5.5 (wideband)Let LP filter cutoff at approx 1e4 (Hz)

Simulating and Testing a PLL...

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Simulating and Testing a PLL...Test #1: Initial PLL Design

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Observations:A: It worked! The FM signal was successfully demodulated using phase-locked loop feedback.

B: The kf value of 1e2 (Hz/V) provided enough sensitivity to accurately reproduce the message while keeping the BT < 3e3 (Hz).

C: The Loop Filter produced a clean output signal and removed the high frequency component produced by the phase detector (multiplier).

Simulating and Testing a PLL...Test #1: Initial PLL Design

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Simulating and Testing a PLL...Test #2: kf << 1e2

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Observations:A: It failed! The FM signal was not successfully demodulated.

B: The kf value of 1e1 (Hz/V) (B < .1), was not sensitive enough to accurately reproduce the message signal in the time domain. Furthermore, the second message component (180 Hz) displayed major attenuation compared to the first message component (36 Hz). (See previous slide for comparison).

C: The Loop Filter produced a clean output signal and removed the high frequency components produced by the phase detector (multiplier).

Simulating and Testing a PLL...Test #2: kf << 1e2

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Simulating and Testing a PLL...Test #3: kf >> 1e2

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Observations:A: It failed! The FM signal was not successfully demodulated.

B: The kf value of 1e3 (Hz/V) (B > 50), was sensitive enough to accurately reproduce the message signal in the time domain. However, the increased value of kf pushed the transmission bandwidth way above the carrier frequency and exceeding our bandwidth requirement.

C: The Loop Filter would need to be adjusted (If the BT didn’t exceed the carrier, which it did) to account for the increased frequency components.

Simulating and Testing a PLL...Test #3: kf >> 1e2

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Simulating and Testing a PLL...Test #4: Cutoff frequency < 1e4

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Observations:A: It failed! The FM signal was not successfully demodulated.

B: The kf value of 1e2 (Hz/V) provided enough sensitivity to accurately reproduce the message while keeping the BT < 3e3 (Hz).

C: The Loop Filter failed! The LP cutoff frequency of 1 kHz was to low and removed several of the pieces (starting at the carrier) needed to accurately represent the message.

Simulating and Testing a PLL...Test #4: Cutoff frequency < 1e4

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Simulating and Testing a PLL...Test #5: Cutoff frequency > 1e4

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Observations:A: It failed! The FM signal was not successfully (cleanly) demodulated.

B: The kf value of 1e2 (Hz/V) provided enough sensitivity to accurately reproduce the message while keeping the BT < 3e3 (Hz).

C: The Loop Filter failed! The LP cutoff frequency of 1.5 kHz was to high and allowed several of the unwanted high frequency components into the system.

Simulating and Testing a PLL...Test #5: Cutoff frequency > 1e4

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Simulating and Testing a PLL...Test #6: Using a 1st order Butterworth

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Observations:A: It failed! The FM signal was not successfully (cleanly) demodulated.

B: The kf value of 1e2 (Hz/V) provided enough sensitivity to accurately reproduce the message while keeping the BT < 3e3 (Hz).

C: The Loop Filter failed! The first order Butterworth filter allowed several of the unwanted high frequency components into the system.

Simulating and Testing a PLL...Test #6: Using a 1st order Butterworth

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Other Applications of PLLs:

• Control Systems

• Frequency Synthesizers

• Jitter reducers

• Digital PLLs

• Clock Generation

• Zero Delay Buffers

• Spread Spectrum Frequency Synthesizers

• Demodulators (QPSK, QAM, FM, FSK, SSB)

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Conclusion:

A phase locked loop is a negative feedback control system whose operation can be used to demodulate an FM signal.

The phase-locked loop will automatically adjust it’s frequency and phase based on an input error voltage and attempt to lock onto a reference signal.

Commonly used for carrier synchronization, indirect frequency demodulation, clocking, buffering, and jitter removal.

Finally: If you would like to further enhance your understanding of phase-locked loops, there is an excellent YouTube video by Professor Surendra Prasad, Department of Electrical Engineering ,IIT Delhi. You can find it at: http://www.youtube.com/watch?v=NeRdsWYqWFU

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Questions:

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References:

Haykin, S., “Analog and Digital Communications 2nd Edition” John Wiley & Sons, Haboken, NJ, 2007.

Truxal, J. G., Automatic Feedback Control System Synthesis, McGraw-Hill, New York, 1955.

Gardner, F. M., Phase Lock Techniques, Wiley, New York, Second Edition, 1967.