Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

VDD

GND

Select mask

(dark field &

clear field)

P-well mask

(dark field)

Note body contacts:

• p-well to GND

• n-substrate to VDD

CMOS Inverter Layout

PMOS

W/L=9l/2l

NMOS

W/L=3l/2l

Active

(clear field)

Gate

(clear field)

Contact

(dark field)

Metal

(clear field)

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

Visualizing Layouts and Cross-Sections with SIMPLer

SIMPL is a CAD tool created by Prof. Neureuther’s group

• allows IC designers to visualize device cross-sections

corresponding to a fabrication process and physical layout.

A Berkeley undergraduate student, Harlan Hile, created a

mini-version of SIMPL (called SIMPLer) for EE40.

• It’s a JAVA program -> can be run on any computer,

as well as on a web server.

• A 3D version SIMPL-GL can be accessed at

http://cuervo2.eecs.berkeley.edu/Volcano/simpl_gl/main.htm

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

Define active areas; etch Si trenches

Fill trenches (deposit SiO2 then CMP)

Twin Well + STI CMOS Process

Form wells (implantation + thermal anneal)

Grow gate oxide

Deposit poly-Si and pattern gate electrodes

Implant source/drain and body-contact regions

Activate dopants (thermal anneal)

Deposit insulating layer (SiO2); planarize (CMP)

Open contact holes; deposit & pattern metal layer

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

9

3D view of a CMOS inverter after contact etch.

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

10

Well Engineering

P-tub

N-tub

Twin Tub

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

11

Twin Well CMOS Process Flow

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

12

C(x)

x

Conventional well (depth and profile

controlled by diffusion drive-in)

Retrograde well (depth and profile

controlled by implantation

energy and dose)

Retrograde Well

- formed by high energy (>200keV) implantation

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

13

1) Very low thermal budget for well formation

(no need for diffusion drive-in)

2) Retrograde Well is formed AFTER field oxidation

small lateral diffusion and localized high conc under FOX

Conventional vs Retrograde Well

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

14

Example: Formation of Channel Stop and Retrograde Well

in a single step

Channel stopRetrograde well

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

15

Multiple Implants for Well Engineering

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

N Cheung EE243 Sp2010 Lec 116

Channel Engineering

Shallow

Oxide

Trench

Isolation

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

17

Generic Silicon-on-Insulator (SOI) CMOS Process Flow

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

18

SOI Process Flow (continued)

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

19

Smallest feature

printable by

lithography

SiO2

CVD oxide CVD oxide

n+ n+ n+ n+

poly-Si gate

Thermal

gate oxide

Oxide spacer

Angled

Implant

n+ pocket

Normal

S/D implant

TiSi2

Self-Aligned Channel V-gate by Optical Lithography

(SALVO) Process

* Sub-50nm channels

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

20

or

SALVO Process Flow

Chang et al, IEDM 2000

See Homework Problem

Professor N Cheung, U.C. Berkeley

Lecture 19EE143 F2010

21

SUMMARY OF IC PROCESS INTEGRATION MODULE

•Self aligned techniques: channel stop, Source/Drain,

LDD, SALICIDE

•How to read process flow descriptions and cross-sections

•Generic NMOS Process with LOCOS

•Generic CMOS Process with LOCOS and single well

•Modified Processes:

•Shallow Trench Isolation (STI), Twin Wells, Retrograde

Well, SOI CMOS