EE090-Digital Technique 3-Th-Inst.pdf

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SRI LANKA INSTITUTE of ADVANCED TECHNOLOGICAL EDUCATION

Training Unit

Digital Technique 3Theory

No: EE 090

INDUSTRIETECHNIKINDUSTRIETECHNIK

ELECTRICAL and ELECTRONIC

ENGINEERING

Instructor Manual


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Training Unit

Digital Technique 3

Theoretical Part

No.: EE 090

Edition: 2008All Rights Reserved

Editor: MCE Industrietechnik Linz GmbH & CoEducation and Training Systems, DM-1Lunzerstrasse 64 P.O.Box 36, A 4031 Linz / AustriaTel. (+ 43 / 732) 6987 3475Fax (+ 43 / 732) 6980 4271Website: www.mcelinz.com


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DIGITAL TECHNIQUE 3

CONTENTS Page

LEARNING OBJECTIVES...................................................................................................3

1 BOOLEAN ALGEBRA ..................................................................................................4

1.1 Basic laws of the Boolean algebra.......................................................................4

1.1.1 Commutative law (principle).............................................................................4

1.1.2

Associative law (principle) ................................................................................5

1.1.3

Law (principle) of Distributivity .........................................................................7

1.2 Summarization of the theorems .........................................................................14

2 SYNTHESISING OF LOGIC ORCUITS ACCORDING TO A TASK...........................16

2.1.1

Disjunctive normal form..................................................................................17

2.1.2

Conjunctive normal form ................................................................................19

2.2 Important tips for the solution of logic circuit problems ......................................20

2.3

Karnaugh-Veitch diagram (KV diagram) ............................................................21

2.3.1 KV diagram for two input variables ................................................................21

2.3.2

KV diagram for three Input variables..............................................................22

2.3.3 KV diagram for four Input variables................................................................23

3

CALCULATION TECHNIQUE ....................................................................................25

3.1 Adding Circuits (adder) ......................................................................................25

3.2 Arithmetic circuits ...............................................................................................28


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DIGITAL TECHNIQUE 3

LEARNING OBJECTIVES

The trainee should...

enumerate and explain the basic principles of Boolean Algebra

apply the logical basic functions in NOR and NAND technique, with the help of the

De'Morgan Law

on the basis of a task develop a truth table and a function

with the help of Boolean Algebra, simplify a function and convert into a logic circuit

with the help of the KV diagram, simplify circuit functions of up to a maximum of four

Input variables

derive a half-adder with the help of the addition rules

develop a digital adder from a half-adder


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DIGITAL TECHNIQUE 3

1 BOOLEAN ALGEBRA

The Boolean algebra (logic algebra, switching algebra) has been named after the English

mathematician George Boole (1815 - 1864).

By it, the mathematical treatment of circuit tasks in digital technology is understood. To

simplify the circuits, or reduce the cost of circuits or to find solutions with certain defined

gates we can use the laws of the Boolean algebra.

1.1 Basic laws of the Boolean algebra

1.1.1 Commutative law (principle)

3 X 4 = 12 3 + 4 = 7

4 x 3 = 12 4 + 3 = 7

Principle of factor permutation Principle of summand

NOTE:

The commutative principle corresponds to the principles of factor permutation and

summand permutation in mathematics. It says that the inputs of AND and OR gates can

be exchanged.

Q = A B

Q = B A

Q = A V B

Q = B V A


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1.1.2 Associative law (principle)

For AND function:


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For OR function:

NOTE:

Variables which are associated with each other by an AND or OR function may be

combined.


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1.1.3 Law (principle) of Distributivity

For AND function:


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Truth table:

For OR function

Circuit:


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Circuit:

Truth table:

NOTE:

The principle of distributivity resembles the parenthesis rules in mathematics.


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Circuit:

Truth table:

NOTE:This rule says that an OR gate with two negated inputs can be used instead of a NAND

gate.


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Circuit:

Truth table:

NOTE:

This rule says that an AND gate with two negated inputs can be used instead of a NOR

gate.


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Circuit:

Circuit:

Truth table:

NOTE: This rule means that an AND gate can be replaced by a NOR gate with two

negated inputs.


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Circuit:

Circuit:

Truth table:

NOTE:

This rule means that an OR gate can be replaced by a NAND gate with two negated

inputs.


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1.2 Summarization of the theorems

1. Double negation of a logic variable

2. Negation

AND and/or OR linkage of a logic variable and its negation.

3. Absorption (from Latin: absorbere, to eat up):

AND and/or OR linkage of a logic variable with the constant "OH and/or "1",

4. Tautology (from Greek: the same)

AND and/or OR linkage of a logic variable with itself.

5. Commutative law:


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6. Law of association:

7. Law of Distributivity:

8. De Morgan's law:

9. Special functions:


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2 SYNTHESISING OF LOGIC ORCUITS ACCORDING TO A TASK

A synthesising of logic circuits according to a task is to be understood as the conversion

of a required task into a functioning logic circuit.

First, the problem must be transferred to a truth fable.

Example: Heating control

The burner Q shall be switched an when the circulating pump A is working and the

temperature sensor B for the warm water supply or the room temperature sensor C

responds.

Truth table (Function table):

Minterme:

These lines of the truth table which have a 1 at the output Q.

Maxterme:

These lines which have a 0 at the output Q.


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There are two ways for establishing the output function Q according to the truth table:

2.1.1 Disjunctive normal form

Each line of the truth table which has a "1" at the output Q is connected in series (AND

function).

The associated input variables (A, B, C, ...) which have a "1" signal are written directly,

those that have a "0" signal, are written as negated.

If several lines have a "1" at the output Q, then they are connected in parallel (OR

function).

Logic diagram:


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Simplification of the Logic function:

Circuit:

Distributivity law:


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Circuit:

2.1.2 Conjunctive normal form

For all lines of the truth fable which have a "0" at the output, the parallel connection (OR

function) will apply, with the Input variables being inverted.

The corresponding line groups are then connected in series (AND function).

Normally, formulation is preferably done after the disjunctive normal method, as the

expressions are usually shorter and can be more easily simplified.


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2.2 Important tips for the solution of logic circuit problems

For the solution of digital circuit problems, the solution steps should always follow a

certain sequence:

1. Exact determination of the Input and output variables.

2. Preparation of a truth fable (sometimes very comprehensive).

3. Reading the logic function from the truth table:

a) disjunctive normal form,

b) conjunctive normal form.

4. Presentation of the function and simplification, using the laws of the logic algebra and

the KV diagram

5. Logic circuit.


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2.3 Karnaugh-Veitch diagram (KV diagram)

Two minterms are considered to be neighbouring if they differ in only one logic variable.

Example:

If the disjunctive normal form contains two neighbouring minterms, a simplification will

always be possible.

In two neighbouring minterms always that variable is omitted which is present as negated

in one minterm, and as not negated in the other.

The Karnaugh-Veitch procedure consists in graphically drawing minterms in such a way

so that all neighbouring minterms are situated together.

Example for shortening in the KV diagram:

2.3.1 KV diagram for two input variables


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Solution with the Boolean algebra

2.3.2 KV diagram for three Input variables


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2.3.3 KV diagram for four Input variables

Example 1:


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Example 2:

NOTE:

Only blocks of two, four, eight, etc, can be comprised and abbreviated.


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3 CALCULATION TECHNIQUE

3.1 Adding Circuits (adder)

For the addition of binary digits several circuit possibilities are available, Always one of

these adding circuits is necessary for each binary digit. The circuit may be derived from

the addition rules.

Truth fable: Function:

Logic diagram: Simplified symbol:


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The circuit - also called "half-adder - supplies one carry-over C but it does not consider

any carry-overs that come from the preceding digit.

A full adder (digital adder) is associated with an additional Input which receives the carry-

over from the preceding digit. A full adder may be built from two half adders.

Truth table:

A, B = summands

Cn-1 = carry-over from the preceding digit

Si = sum of the 1sthalf adder

Cl, C2, Cn = Carry-overs

S2 = sum


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Logic diagram:

Simplified symbol:


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3.2 Arithmetic circuits

If a complete calculated value has to be obtained, then for each binary digit the

appropriate number of full adders has to be connected in such a way that each step

accepts the carry-over from the preceding digit.

Consequently, any desired number of full adders could be connected. Practically, usually

there are mathematical quantities with a word length of 4 bit.

Logic diagram:


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Exercises:

1. Driving a 7-segment display via conjunctive normal form.

Task:

Design a logical circuit (truth table, function, and logic diagram), with which c 7-

segment display module is able to display the figures 0 - 9.

Truth table: 7-segment display

Function (conjunctive normal form)


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Logic diagram:


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2. Driving a 7-segment display via disjunctive normal form.

Task:

Design a logical circuit (truth table, function, KV diagram, and logic Diagram), with

which a 7-segment display module can display the figures 0-9.

Truth table:


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Functions (disjunctive normal form):


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KV diagrams:


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Simplified functions:


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Logic diagram:


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EE090 - Digital Technique 3

Theoretical Test


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DIGITAL TECHNIQUE 3

TEST 1

1. Describe the Law of Commutativity.

2. Describe the Law of Associativity.

3. Take the function from this logic diagram and simplify it in accordance with the Law of

Distributivity.

4. Transform the function Antivalency into the NOR technique.

5. Transform the function Equivalency into the NAND technique.

6. From this truth table, write the disjunctiive and the conjunctive normal forms.


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7. Simplify this function and name the law of the Boolean algebra.

8. Simplify this function with the help of the KV diagram.

9. Simplify this function with the help of the KV diagram.

10. Draw a half-adder (truth table, function, binary circuit).

11. Explain the farm "Minterme".

12. Name two examples for the application of the associative law (function and logic

circuit)

13. Take the function from this logic diagram and simplify it according to the Law of

Distributivity.


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14. Transform the function Antivalency into the NAND technique.

15. Design a logic circuit with the outputs:

Q1 = A < B

Q2 = A = 13

Q3 = A > B

16. The output of a logic circuit should be "1" when any two of three inputs become "1"

Write the function for the output, convert the function into NAND-technique and draw

the KV diagram.

17. From the truth fable (inputs A B C), develop the disjunctive normal form and simplify it

with the help of the KV diagram.

18. Draw a full adder consisting of AND-OR and NOT functions.

19. Prepare the truth table of a full adder.


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20. From this truth table, develop the disjunctive normal form and simplify it with the help

of the KV diagram.


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DIGITAL TECHNIQUE 3

TEST 1

(Solution)

1. It corresponds to the mathematical rules of summand and factor interchange and it

says that the Inputs of AND and/or OR gates can be interchanged.

2. Variables which are linked with each other via an AND and/or OR function can be

compiled.

3.

4.

5.


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6. Disjunctive normal form

Conjunctive normal form

7.

8.

9.


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10. Truth table: Function:

Logic diagram:

11. Minternnes are those lines in the truth fable which have the result "1" at the output "Q".


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12.

13.

14. Disjunctive normal form Conjunctive normal form


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15.

16.


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17.

18.


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19.

20.


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