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EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 [email protected].
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Transcript of EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 [email protected].
![Page 2: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/2.jpg)
Contents
• Literature review• Schematic• Netlist• Design Optimization• Waveforms of test cases• Power consumption at the maximum
operating frequency
![Page 3: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/3.jpg)
Literature Review
• Sklansky adder belongs to tree adder family.• The difference between Sklansky adder and
other tree adders is prefix network.• Compare to other tree adders, Sklansky adder
has minimum logic levels, wiring tracks, but maxinum fanout. Also, it has largest delay at the same condition.
![Page 4: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/4.jpg)
Literature review
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15:014:013:012:011:010:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0
Structure of 16 bit Sklansky Adder(Black square is dot operator
Grey square is empty dot operatorWhite triangle is buffer)
![Page 5: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/5.jpg)
Reference List
• D.Harris, “ A Taxonomy of Parallel Prefix Networks, Signals ”, Systems and Computers, 2003. Conference Record of the Thirty-Seventh Asilomar Conference on, 2, 2213-2217 Vol.2,2003
• J. Sklansky, “Conditional-sum addition logic,” IRE Trans. Electronic Computers, vol. EC-9, pp. 226-231, June 1960.
• J M. Rabaey, A. Chandrakasan, B. Nikolic, “ Digital Integrated Circuits-A Design Perspective (Second Edition)”, Prentice Hall, 2003
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Schematic of adder• Precomputation (Generating Propagate value
P and Generate value G). • Gi:i=Ai·Bi
• Pi:i=Ai B⊕ i
![Page 7: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/7.jpg)
Schematic of adder
• Bubble shifted Dot operator
![Page 8: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/8.jpg)
Schematic of adder• Empty empty dot operator
![Page 9: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/9.jpg)
Schematic of adder• Bubble shifted empty dot operator
![Page 10: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/10.jpg)
Schematic of adder• Overall view of adder
![Page 11: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/11.jpg)
HSPICE netlist see attached file
• Sizing:• NMOS: L=50nm, W=90nm• PMOS: L=50nm, W=135nm• Temperature: 25°C
![Page 12: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/12.jpg)
Design Optimization
• Sizing the gate to minimum size (90nm) can reduce area and power
• By using bubble shifting, we save totally 28 inverters, and 4 inverters on the critical path
• Adding the buffer can effectively reduce delay. Setting stage=1, fanout=4
![Page 13: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/13.jpg)
Waveforms of test cases
• Worst case: For Sklansky adder, the worst case happens when inputs are 7FFF+0001. Since G will propagate from A_0 to S_15 which is the critical path.
![Page 14: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/14.jpg)
Waveforms of test cases• Worst case 7FFF+0001• A_0-A_15 B_0-B_15 Cout,S_0-S_15,
![Page 15: EE 5323 Project 16 Bit Sklansky Adder Phase 1 Report Yuan Xu 4139225 xuxxx488@umn.edu.](https://reader036.fdocuments.us/reader036/viewer/2022062314/56649f565503460f94c7a77b/html5/thumbnails/15.jpg)
Waveforms of test cases• Other cases( FFFF+0001, 7FFF+0001, 3FFF+0001, 1FFF+0001, 0FFF+0001, 07FF+0001,• 03FF+0001• A_0-A_15 B_0-B_15 Cout,S_0-S_15
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Power consumption at the maxinum operating frequency, V=1.1V
• Worst case Delay= 4.11E-10 S• Ptotal=4.50E-05W
• Pmax=1.64E-03W