EE 421 Digital Electronic Project · EE 421 Digital Electronic Andrew M. Tran Section 1001 November...

EE 421 Digital Electronic Andrew M. Tran Section 1001 November 30, 2015

Department of Electrical and Computer Engineering

EE 421 Digital Electronic

Project

Problems

(Design a Negative Power Supply)

All calculations have been verified with Cadence

EE 421 Digital Electronics Andrew M. TranProfessor R. Jacob Baker, PhD. PE November 30, 2015

Department of Electrical and Computer Engineering 1 of 20

v Project Design Requirements

Ø Bandgap Voltage Reference: First begin by laying out the Bandgap Voltage Reference.

Ø Design Sensing Circuit: Design a sensing circuit with an input voltage �� with an adjustable set-

point output ��. Using the Bandgap Voltage Reference with hysteresis incorporate in the

sensing circuit.

§ Constraints

· The sensing circuit should not use no more than 50 �� and no less than 10 �� of

current.

· For the output �� must senses values of the following:

¨ Logic 1 for �� > −2.5 �

¨ Logic 1 for �� < −2.5 �

· The hysteresis of the sensing circuit must be at least 100 �� but less than 200 ��.

· Characterize the design for the following

¨ Power Supply Regulation: 4.5 � ≤ �� ≤ 5.5 �

¨ Operating Temperature: 0℃ ≤ �� ≤ 100℃

· Simulations of the circuit using the symbol view with two pins �� and ��.

Ø Design Ring Oscillator & Charge Pump: Design of enable Ring Oscillator with integrated buffers

that drives a Charge Pump.

§ Constraints

· The Charge Pump must be able to source -2.5 with a load current ranging from

0 �� 200 ��. The output of the Charge Pump will be the input �� of the Sensing Circuit.

· Characterize the design for the following

¨ Power Supply Regulation: 4.5 � ≤ �� ≤ 5.5 �

¨ Operating Temperature: 0℃ ≤ �� ≤ 100℃

¨ Current loads ranging: 0 �� ≤ �� ≤ 200 ��

Ø Final Design: Create symbol of then whole circuit with one pin ��.

§ Constraints

· Show how robust the design with varying current loads and temperatures.

· Discuss the efficiency of the design.



v Band Gap

Ø Schematics and Symbol Views

§ Schematics View

§ Symbol View

Ø Simulations

§ This simulation shows that varying �� from 3.0 � to 6.0 �.

§ The simulation shows that between 4.0 � to 5.5 � the band gap outputs a very

stable 1.25 � which is within operational condition.



Ø Layout

§ DRC of Layout

§ LVS of Extracted



v Ring Oscillator

Ø Calculations

�� =1

�(�� − ��)=

1

��(0.7) · (�� + ��52� �� + ��

�� 170.667 31

182.448 29

195.963 27

211.640 25

230.043 23

251.952 21

278.473 19

§ Choosing � = 21 was chosen because it provided 251 MHz oscillation


§ Schematics View

§ Symbol View



Ø Simulations

§ Simulation with a 40 �� delay time to test for the Enable.

�� = (40.67 �� − 45.5697)�� ≈ 204.09 ��

§ Due to additional impedances this only gives roughly 204.09 ��. Losing about 46.91 ��.

This was factored in when choosing the number a stages.

Ø Layout

§ DRC of Layout



§ LVS of Extracted

v Charge Pump

Ø Calculations

§ Here is an equation that relates �� with ��, �� an ��.

��2

= [��][(�� − 0.9 �) − (0 − (−3.4 �)] · [��2

]

§ Since this is a two stage and the current flows in and out from two pins and the �� only

pulse at half the period. The twos cancel out. Leaving the following.

§ Keeping �� = 300 �� and �� = 200 ��

�� =[��]

[(�� − 0.9 �) − (0 − (−3.4 �)][��]

��

4.5 7.50

5.0 2.14

5.5 1.25

§ The value chosen was 2.14 �� because it was in the mid-range.

§ Using this about value the PMOS can be size creating a PMOS capacitor.

��

��= �� →

2.14 ��

2.5 ��= 857.14 ��

�� = � = � → �857.14�� = 29.277 �� ≈ 30 ��

� = � = 30 ��



§ Wanting the charge pump to be very stable the �� to be 70 times the size of ��.

�� = 70 · 30 �� ≈ 250 ��


§ Schematics View

§ Symbol View



Ø Simulations

§ The negative charge pump is being simulated with a current pulse with a 2.5 �� pulse width

and a period of 5 �� with a 300 �� load.

§ In this simulation the Ring Oscillator with enable is supplying the clock.

§ Looking at the simulation, the negative charge pump reaches −2.5 � in about 800 ��.

Ø Layout

§ DRC of Layout



· LVS of Extracted

v Leve Shifter

Ø Calculations

§ Remember the sensing circuit can only pull no more than 50 �� and no less than 10 �� of

current. So designing around the midpoint to allow for any swing.

�� = �� + ��

2� → �

50 �� + 10 ��

2� = 30 ��

§ For nice resisters picking 25 �� will yield whole number values.

§ For calculating the first set of resistance

�� = ��

�� → �

1.25 �

25 �� = 50 �Ω

§ Using voltage division to calculate the total resistances.

�� = �� − �� · �

�� → �

(2.5 � − (−2.5 �)) · 50 �Ω

1.25 �� = 200 �Ω




§ Schematics View

§ Symbol View

Ø Simulations

§ The simulation of the level shifter shows that the voltages are shifting correctly. Looking at

�� it voltage is roughly 1.25 �.



Ø Layout

§ DRC of Layout

§ LVS of Extracted



v Differential Amplifier

Ø Calculations

§ The gain can be calculated with the slope formula.

� = �� − �� − ��

� → �4.304 � − 1.565 �

1.28137 � − 1.17744 �� = 26.35 ≈ 26

� = 26


§ Schematics View

§ Symbol View



Ø Simulations

§ The differential amplifier was simulated using a DC sweep that increment �� pin from

1 � to 1.5 � with a 1 �� step.

Ø Layout

§ DRC of Layout



§ LVS of Extracted

v Comparator

Ø Calculations

§ The gain can be calculated with the slope formula.

� = �� − �� − ��

� → �3.02 � − 159.4 ��

1.280 � − 1.064 �� = 14.09 ≈ 14

� = 14


§ Schematics View



§ Symbol View

Ø Simulations

§ The comparator was simulated using a DC sweep that increment �� pin from 1 � to

1.5 � with a 1 �� step.

§ Since there is a delay in the circuit, which can account for hysteresis that is needed.

§ Additionally, the buffer on the comparator can be adjusted to change the switching point

voltage.

§ As the �� reaches 1.25 there is a small rise in �� output, this shows that the switching

point is rising faster.

§ The comparator topology chosen for this differential amplifier is a set of two comparators

tied together in series. This will increase the gain of the comparators and thus decrease the

lengths of the MOSFETS needed for hysteresis.



Ø Layout

§ DRC of Layout

§ LVS of Extracted



v Top Level

Ø Efficiency

§ Power supply by �� should be equal to the power delivered to the load for ideal case.

§ Since there are losses in the circuit the most likely values for efficiency should be less then

one.


§ Schematics View

§ Symbol View

Ø Simulations

§ All the following parametric simulation shows varying all the following temperature

from 0℃ ≤ �� ≤ 100℃, �� from 4.5 � ≤ �� ≤ 5.5 � and Load from 0 �� ≤

�� ≤ 200 ��.

§ This is a zoom out view of the top level circuit simulation.



§ This is a zoom in view of the top level circuit simulation highlighting current from the charge

pump. Under all conditions the circuit drains between 25 �� to 28 ��

§ This is a zoom in view of the top level circuit simulation highlighting voltage from the charge

pump. Under all conditions the circuit outputs between −2.66 � to −2.48 �



§ This is a non- parametric simulation under normal operating conditions. Looking at the

enable signal is operating with a delay due to the built-in hysteresis.

§ This simulations shows how enabling circuit sends a signal to the ring oscillator, which is

sharpened by the buffer, which drives the charge pump. The charge pump then sends a

signal to the enabling circuit to see if more charge is needed to be pumped.

Ø Layout

§ DRC of Layout



§ LVS of Extracted

EE 421 Digital Electronic Project · EE 421 Digital Electronic Andrew M. Tran Section 1001 November...

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