EE 382M VLSI–II: Advanced Circuit Design Lecture 12: I/O...

The University of Texas at AustinEE382M VLSI-II Class Notes Foil # 1

EE 382MVLSI–II: Advanced Circuit Design

I/O & ESD Design

Byron Krauter, IBM


Outline

2

• Logic Requirements• Other Complications• Transmission Line Behavior• Basic CMOS I/O and Receiver Design• Actual CMOS I/O and Receiver Design

– Impedance Matching & Slew Rate Control– Mixed Voltages– ESD and other extreme conditions

• Increasing Bandwidth– Source Synchronous I/O or Co-transmitted Clock– Pipelined Bus or Bus Pumping– Dual Data Rate– Simultaneous Bi-Directional– Pattern Based Driver Compensation


Logic Requirements


Logic Requirements

4

• Send 1’s and 0’s chip to chip– Can be accomplished with simple inverters??

Chip A Chip B


Complications• Pin Count Limitations

– Bi-directional signaling– Simultaneous switching noise

• Transmission Line Behavior– Limited net topologies work– Terminations required– Skin effect– Dielectric loss

• Other Noises– Reflections – Discontinuity noise– Crosstalk and connector noise

• Mixed Voltages • ESD and Other Handling Complications

5


Transmission Line Behavior


But First A Few Words onCommon Ground Interconnect

Models


Example - Two Wires & One Source• Twin lead transmission line modeled as a single section

and driven by a Thevenin source

0.5*Cwire0.5*Cwire

Rwire

Rwire

Rsource

L22

L11

M12


Example - Two Wires & One Source• Being concerned with local potentials only (i.e. capacitor

potentials) inductances and resistances can be combined

0.5*Cwire0.5*Cwire

Rwire RwireRsource L22L11

M12

0.5*Cwire0.5*Cwire 2*Rwire

Rsource L11+ L22 - 2*M12


Example - Three Wires & Two Sources• When multiple wires form a cutset, treat one wire as a

reference lead and fold it into the other wires*.

* Brian Young, “Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages”

Rg

Lgg

0.5*C1g

R1Rs1 L11

M1g

0.5*C2g

R2Rs2 L22

M2g

0.5*C12

0.5*C12

0.5*C1g

0.5*C2g

M12

Cutset


Example - Three Wires & Two Sources• Resulting loop impedance model for three parallel wires

driven by two Thevenin sources

0.5*C12

0.5*C2g

0.5*C1g

R1+RgRs1L11+Lgg-2M1g

0.5*C12

M12-M1g-M2g+Lgg

i2Rg

R2+RgRs2L22+Lgg-2M1g

0.5*C1g

i1Rg

0.5*C1g

v1

v2

mutual resistances


Transmission Line Behavior• On and off chip signals can always be modeled with lumped

RLC circuits

• Wire segments are modeled with π or t segments

• L, R, C, and G can be frequency dependent

• But inductance is not always important


Transmission Line Behavior

13

• Inductance is important when– Driver source impedance Rs is low

Rs < Zo where Zo = characteristic impedance of line

– Driver rise time τr is fast

τr < 2.5 τfwhere τf = time of flight

– Line loss is lowR << jωL or (R / 2Zo) << 1

• Can be restated for point to point nets asRsCtot < 1/2 RlineCline < τf

Wave frontdecays exponentially

with this constant


When Inductance is Important• Nets ring and net delays become unpredictable unless:

– Net topologies are constrained• Point to point nets• Periodically loaded nets • Near and far end clusters

– Nets are driven appropriately• Not to strong and not to weak• Not to fast and not to slow

– Nets are terminated appropriately• Source termination• Far end termination

– Resistance to Vdd or Gnd or any Thevenin Voltage • AC termination = RC circuit• Active hold clamps• Diode or Schottky diode clamps

14


Transmission Line Behavior• Perfectly source terminated point to point, loss-less net

15

V(t)

Rs = Zoτf

time

far end

near end

Zo = LC

τf = LC

τf


Transmission Line Behavior• Under driven point to point, loss-less net

16

Rs = 3Zoτf Zo = L

C

τf = LC

V(t)

time

far end

near end

ApproximatesRC step response


Transmission Line Behavior• Over driven point to point, loss-less net

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Rs = 1/3 Zoτf Zo = L

C

τf = LC

V(t)

time

far end

near end


Reflection and Transmission

18

Γv = ZL - ZoZL+ Zo

Γv = 1, ZL= ∞0, ZL= Zo

-1, ZL= 0

Τv = 1 + Γv = 2ZLZL+ Zo

With incident wave Vinc traveling down the line

Voltage reflection coefficient

Voltage transmission coefficient


Equivalent Circuits Along Line

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Rs

ZoVs

near end

Zo2Vinc

Zo along line

ZL2Vinc

Zo far end

Vinc+

-

Zdiscontinuity


Discontinuities Along Line

20

C

L

Vs

Rs = Zo

Vs

Rs = Zo

Vs=11

1/21/2 (1- e-2t/ZoC)

Vs=11

1/21- 1/2(1- e-2Zot/L)


Well Behaved Net Topologies• Point to Point Nets

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Rs = Zoτf

Source terminated

Rs << Zoτf

Far end terminated

Rterm ≅ ZoVterm


Well Behaved Net Topologies• Periodically Loaded Nets

22

Source terminated: Near end switches last

Rs = Zeff

CL CL CL CL

With periodic loadingZeff = L

C + nCL

τf = L(C+nCL)


Well Behaved Net Topologies• Periodically Loaded Nets

23

Far end terminated: Near end switches first

Rs << Zeff

CL CL CL CL

With periodic loadingZeff = L

C + nCL

τf = L(C+nCL)

Rterm ≅ ZeffVterm


Well Behaved Net Topologies• Near end (or Star) cluster

24

Rs = Zo/N


Well Behaved Net Topologies• Far-end cluster

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Rs = Zo/N Zo/N


Well Behaved Net Topologies• Double far-end terminated bus

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CL CL CL CL

Vterm

Rs << Zo

Vterm

CL


Ideal Transmission Lines

27

γ =Z = LC ω LC

I(z)

V(z)

tiL

zV

tVC

zi

∂∂

−=∂∂

∂∂

−=∂∂

2

2

2

2

tVLC

zV

∂∂

=∂∂

Steady State Solution:])VV[

1(ReI

]VV[ReV

)()(

)()(

eeee

tzjtzj

tzjtzj

Zωγωγ

ωγωγ

+−−−+

+−−−+

+=

+=

where

IdealTelegrapher’s Equation


Transmission Lines with Loss

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j γ (ω) = (jωL + R) jωCZ(ω) = jωL + RjωC

≅ LC (1 - j R/2ω L) ≅ (1 - j R/2ω L)jω LC

02)(

ZRLC += ωωγ

00 2

)(ZC

RjZZω

ω −=


Waveforms Along a Low Loss Line

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(1- e-R*length/2Zo)1

Vs

Rs << Zo

τfwhere τf = length / velocity

With complex impedance & complex propagation constanthigh speed wavefront decays exponentially & distorts


Distortionless Transmission Line

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j γ (ω) = (jωL + R)(jωC + G)Z(ω) = jωL + RjωC + G

= LC

= ( jω + R /L)LC

Oliver Heaviside (1887)

LRCG // =


Waveforms Along a Distortionless Line

31

(1- e-R*length/Zo)1

Vs

Rs << Zo


With real impedance and complex propagation constanthigh speed wavefront decays exponentially but without distortion


Basic CMOS I/O and Receiver Design


Bidirection CMOS I/O Buffer

33

data

enable Pad

0 101

data

enable

Hi ZHi Z0

1


CMOS I/O Receiver• Any two input gate that

– Has good noise immunity– Provides on-chip control when off-chip inputs float

• Example: two input nand

34

0 101

data

enable

X

111 0

X1

data

enablePad

out


Actual CMOS I/O and Receiver Design


Actual CMOS I/O Design• Output Impedance Control• Slew Rate Control• Mixed Voltage Designs

– Input Design for Higher Voltages– Output Design for Higher Voltages

• Dual Power Supplies• Floating Well Designs• Open Source Signaling

• Other Circuits– Differential I/O Circuits– Hysteresis Receivers

• ESD Circuits

36


Output Impedance Control• Device “resistances” are too variable for source

termination– Devices are non-linear – Variations due to Vdd, Temp, and process variations

alone are >2X in linear region!

• Output stages must be designed to reduce this variation– On-chip resistors designs – Logically tunable designs

37


Impedance Control Using On-Chip Resistors• Given a precise on-chip resistor, this design provides the

best impedance control

38

data

enable

Pad


Tunable Impedance Control• Stacked device settings can be preset or dynamically

controlled

39

n1 n2 n3

data

enable Pad

p3p2p1


Slew Rate Control• Output stage slew rate is controlled to reduce noise

– Cross talk noise– Simultaneous switching noise– Reflections at discontinuities

• Slew rate control is accomplished by controlling the pre-driver delay and/or pre-driver strength

40


Slew Rate Control• Output stage is divided and pre-drive signal is designed to

sequentially arrive at the different sections

41

data

enable Pad

δ δ

δ δ


Slew Rate Control & Impedance Control• Pre-driver design might even permit crossover currents to

guarantee impedance even during switching

42

data

enable Pad

δ δ

δ δ


Feedback Slew Rate Control I/O Buffer

data

enablePad

(Motorola 68332, McDermott, Carter)


Mixed Voltage Designs• Needed when chips have different supply voltages• Low voltage circuits can be damaged by high voltage

inputs• High voltage circuits suffer delay & noise problems when

receiving low voltage signals

44

Vdd1

newertechnology

Vdd2Bi-directionalI/O Buffers

oldertechnology

Vdd1 < Vdd2


Input Design for Higher Voltages• Modifications for gate oxide & ESD protection

45

ESD Diodes

Pad

ESD Diodes

Pad

Receiving Same Level Receiving Higher Level

change beta ratio


Pass Gate Behavior• nfet and pfet pass gates can be used to limit voltages

46

0

Vdd

V1

V1 - Vtn

0

Vdd

V1

V1 - Vtp


Dual Supply Designs• Separately power I/O circuits at a lower voltage

– No additional process steps required– Extra design to avoid performance penalty – ESD & simultaneous switching noise compromised

47

Vdd1

newertechnology

Vdd2Bi-directionalI/O Buffers

oldertechnology

Vdd1


Output Stage at a Lower Voltage• Slow rising delay due to low overdrive on pfet• Reduced drive = reduced noise immunity on nand receiver

48

ESD Diodes

data

inhibit

Vdd1

Pad

Vdd1 or Vdd2

enable

Vdd2

The University of Texas at AustinEE382M VLSI-II Class Notes Foil # 49 49

Output Stage at a Lower Voltage• Improve rising delay with nfet pull up• Change p/n beta ratio on nand to lower switch point

ESD Diodes

data

inhibit

1.2 Volts

Pad

1.2 or 1.8 Volts

enable

1.8 Volts

change beta ratio


Dual Supply Designs• Separately power the I/O circuits at a higher voltage

– More complicated circuits– ESD & simultaneous switching noise compromised

50

1.8 Volts

oldertechnology

1.2 Volts Bi-directionalI/O Buffers

newertechnology

1.8 Volts


Output Stage at a Higher Voltage• Slow rising delay due to low overdrive on pfet• Reduced drive = reduced noise immunity on nand receiver

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data

enable

Vdd1

Pad

Vdd2

Vdd2

Vdd1

LevelShifter

Vbias


Floating Well Designs • Enabled output stage sends lower voltage - Vdd1• Disabled output stage tolerates higher voltage - Vdd2

52

data

enablePad

Vdd1

Vdd1

Vdd1

Vdd1


Open Drain Signaling• Avoids complexity of multiple chip power supplies

– Off-chip termination resistors pull net up– On-chip nfet devices pull net down

• Increases transmission line design complexity• Wired OR functionality

53

CL CL CL CL

VttVtt

CL

Driving Chip


Other Circuits• Differential I/O Circuits

– Reduces simultaneous switching noise– Improves receiver common mode noise immunity– Receives smaller signal levels– “Pseudo” to full differential possible

• Hysteresis Receivers– High noise immunity– Excellent for low-speed asynchronous test & control

signals

• Hold Clamps

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Differential Output Buffers

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Pseudo Differential Outputs

Differential Outputsout

out

out out

Vbias

Vdd


Differential Transmission Lines

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Pseudo = two lines

Zo

ZoDifferential = coupled pair

coupled

Zeff < Zo

Zeff < Zo


Differential Far End Termination

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Pseudo Differential Termination

Vtt

R = Zo Vtt

R = ZoDifferential Termination

R = 2 Zo


Differential Receivers

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Pseudo Differential Receiver

Differential Receiverout

out

out out

Vbias

Vdd


Self Biased Differential Receiver• Combines best of nfet and pfet differential receivers

59

out out

Nbias

Vdd

out out

Pbias

Vdd


Self Biased Differential Receiver• Combines best of nfet and pfet differential receivers

– Rail to rail output swing– Excellent common mode noise rejection

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out

Vdd

(Bazes, JSSC 91)

or reference


Hysteresis Input Receivers• Separates rising & fall edge dc transfer curves

inhibit

Pad

weak feedback inverter

Vin

Vout

VoutVin

risingfalling

and only

Pad Vin Vout


Hold Clamps

• Weak clamps hold tri-stated source terminated nets

• Stronger clamps will actively terminate the net– Can be slower than passive termination schemes

Padweak feedback inverter

Vdd

I/O


ESD Design• Pins subjected to ESD (electrostatic discharge) events

during test & handling• Over-voltages can also occur during functional operation

– System power-on– Hot-plugging

• ESD discharge can occur between any two pins – I/O to I/O– I/O to Vdd or Gnd

• Pins are measured against standard ESD tests– Human body model– Machine model– Charged Device Model

• ESD performance depends on many parameters other circuits don’t care about

63


ESD Circuits• Non-breakdown based circuits

– Diodes– Bipolar Junction Transistor– MOS FET

• Breakdown based circuits– Thick Field Oxide Device – SCR (silicon controlled rectifier)

64

Primary ESD Circuit inCMOS Designs

Most Diode Circuitsare really Bipolar Circuits


Dual Diode ESD Circuits

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ESD Diodes

Pad

ESD Diodes

Pad

Single Supply Design Mixed voltage design


FET ESD Circuits: non-breakdown mode

66

ESD Diodes

Pad

nfet in “diode”configuration


FET ESD Circuits: breakdown mode

67

ESD Diodes

Pad

nfet protectsby clamping voltage

after device snapbackV

Isnapback

secondbreakdown

Vgs > Vt


Diode ESD Circuits• fet devices are parasitic npn & pnp bipolar circuits

68

ESD Diodes

Pad

ESD bipolar devices

Pad

• vertical pnp device to substrate

• horizontal npn device to guard rings (before trench isolation)

• low vdd to gnd impedance to due on-chip capacitance provide additional discharge paths


Parasitic Bipolar Circuits• fet devices are parasitic npn & pnp bipolar circuits

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• vertical pnp device to substrate


ESD Test Models• Human Body Model

– Requirements 2 - 4 kVolts– Positive or negative discharge between any two pins

70

VHBM DUT

C = 100 pF

R = 1.5 KΩ

i(t)

timet = 2-10 nsec

ipeak = VHBM/1500


ESD Test Models• Machine Model

– Requirements 200 - 400 Volts– Positive or negative discharge between any two pins

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VMM DUT

C = 200 pF

R < 8.5 Ω

L = 0.5 - 0.75 μH


ESD Performance Factors• Diode symmetry is important

– Bipolar conduction increases with temperature– Hot spots conduct more, heat up more, conduct more,

… and finally burn out• Layout corners are rounded to reduce electric fields• Decoupling capacitance needed between all supplies• Functional performance requirements impose ESD size &

load capacitance constraints• Parasitic bipolar effects abound• Breakdown clamps don’t scale

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Increasing Bandwidth


Common Clock Transfers

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• Chip to chip transfers controlled by common bus clock• Equal length card routes to each chip & on-chip PLL’s

minimize clock skew

clocksource

PLL

Chip A

PLL Chip B


Common Clock Transfers

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clocksource

PLL

Chip A

PLLChip B

Tclk - A

TtofTdrive

TAclk

Tclk - B

TBclk

Treceive Tsetup

max(Tclk - A+TAclk +Tdrive+ Ttof+ Treceive + Tsetup ) - min(TBclk - Tclk - B) < Tcycle

Cycle time to meet setup time


Source Synchronous I/O

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• Send source clock with source data

• Resolve clock phase differences with τ1, τ2, & τ3

clocksource

PLL

Chip A

PLL

Chip Bτ3

τ2τ1


Bus Pumping

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• With Ttof > Tcycle, multiple bits are present on the wire

clocksource

PLL

Chip A

PLL

Chip Bτ3

τ2τ1


Dual Data Rate

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• Conventional source synchronous design– Data launched & captured on single clock edge – Clock switches at f– Maximium data rate = 1/2 * f

• Dual data rate - if clock can switch at f, why not data?– Data is launched & captured on both clock edges – Clock switches f– Maximum data rate = f

Conventional Dual Data Rate

Data

Clock


Simultaneous Bidirectional Signaling • Two chips send & receive data simultaneously on a

point to point net• Waveforms superimpose on the transmission line• Each chip selects it’s receiver reference voltage based

on the data it sent• Sending data is subtracted from total waveform

Chip A

3/4 Vdd1/4 Vdd

Chip B

3/4 Vdd1/4 Vdd


Pattern Based Driver Compensation • Incident waveforms along a long-lossy lines attenuate • Slow “RC” like response to final level

(1- e-R*length/2Zo)1/2

Vs

Rs = Zo


With complex impedance and propagation constanthigh speed wavefront decays exponentially


Pattern Based Driver Compensation

• Adjust driver strength based on bits sent in earlier cycles

• Example: When driving low to high– Drive harder if previous bits sent = 00– Drive weaker if previous bits sent = 10

1 0 0 1 0 0

Without Compensation

1 0 0 1 0 0

Drive harder

With Compensation

ReceiverSwitch Point


Increasing Bandwidth

• Preceding techniques cannot be achieved through clever circuit design alone

• Requires good packaging technology & net design– Good termination– Minimal capacitive & inductive discontinuities– Low cross-talk– Low simultaneous switching noise


SerDes Architecture


PCI-Express Interface

EE 382M VLSI–II: Advanced Circuit Design Lecture 12: I/O...

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